Ðþí  U5   H  NÐ   (            e  Nˆ                                                                        samtec VIN|ING FPGA       1   !samtec,vining altr,socfpga-cyclone5 altr,socfpga       aliases          ,/soc/serial0@ffc02000            4/soc/serial1@ffc03000            </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000             X/soc/ethernet@ff702000           b/soc/ethernet@ff700000        cpus                                       laltr,socfpga-smp       cpu@0            !arm,cortex-a9            zcpu          †             Š            ›         cpu@1            !arm,cortex-a9            zcpu          †            Š            ›            pmu@ff111000             !arm,cortex-a9-pmu            £            ´       °          ±            ¿               †ÿ    ÿ0          interrupt-controller@fffed000            !arm,cortex-a9-gic            Ò             ã         †ÿþÐ    ÿþÁ             ›         soc                                   !simple-bus           zsoc          £             ø   amba             !simple-bus                                     ø   pdma@ffe01000            !arm,pl330 arm,primecell          †ÿà          `   ´       h          i          j          k          l          m          n          o            ÿ           
         	  apb_pclk                  <        $dma          ›   5         base_fpga_region             !fpga-region         0                                  can@ffc00000             !bosch,d_can          †ÿÀ           0   ´       ƒ          „          …          †           
                 7      	  9disabled          can@ffc01000             !bosch,d_can          †ÿÀ          0   ´       ‡          ˆ          ‰          Š           
   	              8      	  9disabled          clkmgr@ffd04000          !altr,clk-mgr             †ÿÐ@       clocks                               osc1            @             !fixed-clock         M}x@         ›   
      osc2            @             !fixed-clock          ›         f2s_periph_ref_clk          @             !fixed-clock          ›         f2s_sdram_ref_clk           @             !fixed-clock          ›         main_pll@40                                   @             !altr,socfpga-pll-clock          
   
         †   @         ›      mpuclk@48           @             !altr,socfpga-perip-clk          
           ]   à       	         †   H         ›         mainclk@4c          @             !altr,socfpga-perip-clk          
           ]   ä       	         †   L         ›         dbg_base_clk@50         @             !altr,socfpga-perip-clk          
      
        ]   è       	         †   P         ›         main_qspi_clk@54            @             !altr,socfpga-perip-clk          
            †   T         ›         main_nand_sdmmc_clk@58          @             !altr,socfpga-perip-clk          
            †   X         ›         cfg_h2f_usr0_clk@5c         @             !altr,socfpga-perip-clk          
            †   \         ›            periph_pll@80                                     @             !altr,socfpga-pll-clock          
   
               †   €         ›      emac0_clk@88            @             !altr,socfpga-perip-clk          
            †   ˆ         ›         emac1_clk@8c            @             !altr,socfpga-perip-clk          
            †   Œ         ›         per_qsi_clk@90          @             !altr,socfpga-perip-clk          
            †            ›          per_nand_mmc_clk@94         @             !altr,socfpga-perip-clk          
            †   ”         ›         per_base_clk@98         @             !altr,socfpga-perip-clk          
            †   ˜         ›         h2f_usr1_clk@9c         @             !altr,socfpga-perip-clk          
            †   œ         ›            sdram_pll@c0                                      @             !altr,socfpga-pll-clock          
   
               †   À         ›      ddr_dqs_clk@c8          @             !altr,socfpga-perip-clk          
            †   È         ›   !      ddr_2x_dqs_clk@cc           @             !altr,socfpga-perip-clk          
            †   Ì         ›   "      ddr_dq_clk@d0           @             !altr,socfpga-perip-clk          
            †   Ð         ›   #      h2f_usr2_clk@d4         @             !altr,socfpga-perip-clk          
            †   Ô         ›   $         mpu_periph_clk          @             !altr,socfpga-perip-clk          
           e            ›   4      mpu_l2_ram_clk          @             !altr,socfpga-perip-clk          
           e         l4_main_clk         @             !altr,socfpga-gate-clk           
           s   `             ›         l3_main_clk         @             !altr,socfpga-perip-clk          
           e         l3_mp_clk           @             !altr,socfpga-gate-clk           
           ]   d               s   `            ›         l3_sp_clk           @             !altr,socfpga-gate-clk           
           ]   d            l4_mp_clk           @             !altr,socfpga-gate-clk           
              ]   d              s   `            ›   +      l4_sp_clk           @             !altr,socfpga-gate-clk           
              ]   d              s   `            ›   ,      dbg_at_clk          @             !altr,socfpga-gate-clk           
           ]   h               s   `            ›         dbg_clk         @             !altr,socfpga-gate-clk           
           ]   h              s   `         dbg_trace_clk           @             !altr,socfpga-gate-clk           
           ]   l               s   `         dbg_timer_clk           @             !altr,socfpga-gate-clk           
           s   `         cfg_clk         @             !altr,socfpga-gate-clk           
           s   `         h2f_user0_clk           @             !altr,socfpga-gate-clk           
           s   `   	      emac_0_clk          @             !altr,socfpga-gate-clk           
           s                 ›   &      emac_1_clk          @             !altr,socfpga-gate-clk           
           s                ›   (      usb_mp_clk          @             !altr,socfpga-gate-clk           
           s               ]   ¤                ›   6      spi_m_clk           @             !altr,socfpga-gate-clk           
           s               ]   ¤               ›   3      can0_clk            @             !altr,socfpga-gate-clk           
           s               ]   ¤               ›         can1_clk            @             !altr,socfpga-gate-clk           
           s               ]   ¤   	            ›   	      gpio_db_clk         @             !altr,socfpga-gate-clk           
           s               ]   ¨             h2f_user1_clk           @             !altr,socfpga-gate-clk           
           s             sdmmc_clk           @             !altr,socfpga-gate-clk           
                 s               |       ‡         ›         sdmmc_clk_divided           @             !altr,socfpga-gate-clk           
           s               e            ›   .      nand_x_clk          @             !altr,socfpga-gate-clk           
                 s       	         ›         nand_ecc_clk            @             !altr,socfpga-gate-clk           
           s       	         ›   0      nand_clk            @             !altr,socfpga-gate-clk           
           s       
        e            ›   /      qspi_clk            @             !altr,socfpga-gate-clk           
                  s                ›   1      ddr_dqs_clk_gate            @             !altr,socfpga-gate-clk           
   !        s   Ø          ddr_2x_dqs_clk_gate         @             !altr,socfpga-gate-clk           
   "        s   Ø         ddr_dq_clk_gate         @             !altr,socfpga-gate-clk           
   #        s   Ø         h2f_user2_clk           @             !altr,socfpga-gate-clk           
   $        s   Ø               fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           †ÿ@                   a        
         	  9disabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             †ÿP                   `        
         	  9disabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             †ÿ`                   b        
         	  9disabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           †ÿÂP€         	  9disabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            †ÿp`    ÿ¹              ´       ¯            ›         stmmac-axi-config           †           –           ¦                                    ›   '      ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         °   %   `             †ÿp               ´       s           Ãmacirq          Ó                
   &      
  stmmaceth                        
  $stmmaceth           ß           ú   €                   $           2   '      	  9disabled          ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         °   %   `            †ÿp               ´       x           Ãmacirq          Ó                
   (      
  stmmaceth                 !      
  $stmmaceth           ß           ú   €                   $           2   '        9okay            Brgmii           K   )        V   *                f        |  '  '  '   mdio0                                      !snps,dwmac-mdio    ethernet-phy@1           †           ‘            ž            «            ¸            Å            Ò            ß            ì            ù              D                      D         ›   )            gpio@ff708000                                      !snps,dw-apb-gpio             †ÿp€            
   +              9        9okay       gpio-controller@0            !snps,dw-apb-gpio-port            +        ;           G            †              ã         Ò            ´       ¤            ›   *         gpio@ff709000                                      !snps,dw-apb-gpio             †ÿp            
   +              :        9okay       gpio-controller@0            !snps,dw-apb-gpio-port            +        ;           G            †              ã         Ò            ´       ¥            ›   9         gpio@ff70a000                                      !snps,dw-apb-gpio             †ÿp             
   +              ;        9okay       gpio-controller@0            !snps,dw-apb-gpio-port            +        ;           G            †              ã         Ò            ´       ¦            ›   8         i2c@ffc04000                                       !snps,designware-i2c          †ÿÀ@                  ,        
   ,         ´       ž           9okay       pca9557@1f           !nxp,pca9557          †            +        ;         lm75@48          !lm75             †   H      at24@50          !atmel,24c01         U            †   P      i2cswitch@70             !nxp,pca9548                                    †   p   i2c@0                                      †          i2c@1                                      †         i2c@2                                      †         i2c@3                                      †         i2c@4                                      †         i2c@5                                      †         i2c@6                                      †      eeprom@51            !atmel,24c01         U            †   Q         i2c@7                                      †      eeprom@51            !atmel,24c01         U            †   Q               i2c@ffc05000                                       !snps,designware-i2c          †ÿÀP                  -        
   ,         ´       Ÿ           9okay            M †    at24@50          !atmel,24c02         U            †   P         i2c@ffc06000                                       !snps,designware-i2c          †ÿÀ`                  .        
   ,         ´                 	  9disabled          i2c@ffc07000                                       !snps,designware-i2c          †ÿÀp                  /        
   ,         ´       ¡         	  9disabled          eccmgr           !altr,socfpga-ecc-manager                                       ø   l2-ecc@ffd08140          !altr,socfpga-l2-ecc          †ÿÐ@            ´       $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           †ÿÐD           ^   -         ´       ²          ³            cache-controller@fffef000            !arm,pl310-cache          †ÿþð             ´       &            c        q           }                                  ž           ¬            »        Ï           ã            ü                       '            ›         l3regs@0xff800000            !altr,l3regs syscon           †ÿ€           dwmmc0@ff704000          !altr,socfpga-dw-mshc             †ÿp@             ´       ‹                                                
   +   .        biu ciu               6      	  9disabled             ;        E            O         a      nand@ff900000                                      !altr,socfpga-denali-nand             †ÿ     ÿ¸             rnand_data denali_reg             ´                  
   /      0        nand nand_x ecc               $      	  9disabled          sram@ffff0000         
   !mmio-sram            †ÿÿ              ›   -      spi@ff705000          !   !intel,socfpga-qspi cdns,qspi-nor                                       †ÿpP    ÿ               ´       —           |   €        Œ           œ            
   1              %        9okay       flash@0                                   !micron,n25q128 jedec,spi-nor             †            ±õá          Ã        Ò           á           ñ              2           2                   +         flash@1                                   !micron,mt25qu02g jedec,spi-nor           †           ±õá          Ã        Ò           á           ñ              2           2                   +            rstmgr@ffd05000         9            !altr,rst-mgr             †ÿÐP            F            ›         snoop-control-unit@fffec000          !arm,cortex-a9-scu            †ÿþÀ          sdr@ffc25000             !altr,sdr-ctl syscon          †ÿÂP                  =         ›   2      sdramedac            !altr,sdram-edac         Y   2         ´       '         spi@fff00000             !snps,dw-apb-ssi                                    †ÿð              ´       š           i           
   3              2        $spi       	  9disabled          spi@fff01000             !snps,dw-apb-ssi                                    †ÿð             ´       ›           i           
   3              3        $spi       	  9disabled          sysmgr@ffd08000          !altr,sys-mgr syscon          †ÿÐ€   @         pÿÐ€Ä         ›   %      timer@fffec600           !arm,cortex-a9-twd-timer          †ÿþÆ             ´                
   4      timer0@ffc08000          !snps,dw-apb-timer            ´       §            †ÿÀ€            
   ,        timer                 *        $timer         timer1@ffc09000          !snps,dw-apb-timer            ´       ¨            †ÿÀ            
   ,        timer                 +        $timer         timer2@ffd00000          !snps,dw-apb-timer            ´       ©            †ÿÐ             
   
        timer                 (        $timer         timer3@ffd01000          !snps,dw-apb-timer            ´       ª            †ÿÐ            
   
        timer                 )        $timer         serial0@ffc02000             !snps,dw-apb-uart             †ÿÀ              ´       ¢           €           Š           
   ,        —   5      5           œtx rx                 0      serial1@ffc03000             !snps,dw-apb-uart             †ÿÀ0             ´       £           €           Š           
   ,        —   5      5           œtx rx                 1      usbphy          ¦             !usb-nop-xceiv           9okay             ›   7      usb@ffb00000          
   !snps,dwc2            †ÿ°    ÿÿ         ´       }           
   6        otg               "        $dwc2            ±   7      	  ¶usb2-phy            9okay            Àhost          usb@ffb40000          
   !snps,dwc2            †ÿ´    ÿÿ         ´       €           
   6        otg               #        $dwc2            ±   7      	  ¶usb2-phy            9okay            Àperipheral        watchdog@ffd02000            !snps,dw-wdt          †ÿÐ              ´       «           
   
              &        9okay          watchdog@ffd03000            !snps,dw-wdt          †ÿÐ0             ´       ¬           
   
              '      	  9disabled             chosen          Èearlyprintk         Ñserial0:115200n8          memory@0             zmemory           †    @         gpio-keys         
   !gpio-keys      hps_temp0           ÝBTN_0           O   8              ã         hps_hkey0         
  ÝGP_SWITCH           O   8              ã        hps_hkey1           ÝRESET_SWITCH            O   8              ã        hps_hkey2           ÝPOWER_DOWN          O   8              ã   t      hps_hkey3           ÝSENSE           O   *   	           ã           regulator-usb-nrst           !regulator-fixed       	  îusb_nrst            ý LK@         LK@        a   9               - p         >         Q         	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 ethernet0 ethernet1 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate clk-phase snps,wr_osr_lmt snps,rd_osr_lmt snps,blen altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth snps,axi-config phy-mode phy-handle snps,reset-gpio snps,reset-active-low snps,reset-delays-us rxd0-skew-ps rxd1-skew-ps rxd2-skew-ps rxd3-skew-ps txd0-skew-ps txd1-skew-ps txd2-skew-ps txd3-skew-ps txen-skew-ps txc-skew-ps rxdv-skew-ps rxc-skew-ps gpio-controller #gpio-cells snps,nr-gpios pagesize iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address spi-max-frequency m25p,fast-read cdns,page-size cdns,block-size cdns,read-delay cdns,tshsl-ns cdns,tsd2d-ns cdns,tchsh-ns cdns,tslch-ns #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names dr_mode bootargs stdout-path label linux,code regulator-name regulator-min-microvolt regulator-max-microvolt startup-delay-us enable-active-high regulator-always-on 