     8     (                                           #    raspberrypi,5-model-b brcm,bcm2712                                   &            7Raspberry Pi 5     clocks     clk-osc           fixed-clock          =             Josc          ]7         m         clk-vpu           fixed-clock          =             ],      
   Jvpu-clock            m         clk-uart              fixed-clock          =             ]           Juart-clock           m   
      clk-emmc2             fixed-clock          =             ]          Jemmc2-clock          m            cpus                                      m      cpu@0            ucpu           arm,cortex-a76                        psci                            @                                    @                                 m      l2-cache-l0           cache                           @                                                      m            cpu@1            ucpu           arm,cortex-a76                       psci                            @                                    @                                 m      l2-cache-l1           cache                           @                                                      m            cpu@2            ucpu           arm,cortex-a76                       psci                            @                                    @                                 m      l2-cache-l2           cache                           @                                                      m            cpu@3            ucpu           arm,cortex-a76                       psci                            @                                    @                                 m      l2-cache-l3           cache                           @                                                      m            l3-cache              cache                            @                                          m            psci             smc           arm,psci-1.0 arm,psci-0.2         reserved-memory                                           m      atf@0                                          linux,cma             shared-dma-pool                          $         -        ?            @            m            soc@107c000000            simple-bus                                                         m      mmc@fff000        &    brcm,bcm2712-sdhci brcm,sdhci-brcmstb                `           	  Lhost cfg            V                 a           hsw_sdio          t                      	                                               m         timer@7c003000            brcm,bcm2835-system-timer            | 0          0  V       @          A          B          C            ] B@         m         mailbox@7c013880              brcm,bcm2835-mbox            |8   @        V       !                        m         interrupt-controller@7cd00000             brcm,bcm2836-l1-intc             |              m         serial@7d001000           arm,pl011 arm,primecell          }             V       y           a   
           huartclk apb_pclk             4        okay             m         interrupt-controller@7d517000             brcm,bcm7271-l2-intc             }Qp            V                                    gpio@7d517c00         $    brcm,bcm7445-gpio brcm,brcmstb-gpio          }Q|    @                 ,           8               m         interrupt-controller@7fff9000             arm,gic-400                                                           m            timer             arm,armv8-timer       <  V                              
                aliases          N/soc@107c000000/serial@7d001000       chosen          Wserial10:115200n8            m         memory@0             umemory                       (         sd-io-1v8-reg             regulator-gpio        
  cvdd-sd-io           r w@         2Z                                                       w@    2Z             m         sd-vcc-reg            regulator-fixed         cvcc-sd          r 2Z         2Z                                             m   	      __symbols__         /clocks/clk-osc         /clocks/clk-vpu         /clocks/clk-uart            /clocks/clk-emmc2           &/cpus           +/cpus/cpu@0         0/cpus/cpu@0/l2-cache-l0         </cpus/cpu@1         A/cpus/cpu@1/l2-cache-l1         M/cpus/cpu@2         R/cpus/cpu@2/l2-cache-l2         ^/cpus/cpu@3         c/cpus/cpu@3/l2-cache-l3         o/cpus/l3-cache          x/reserved-memory            }/reserved-memory/linux,cma          /soc@107c000000         /soc@107c000000/mmc@fff000          /soc@107c000000/timer@7c003000        !  /soc@107c000000/mailbox@7c013880          .  /soc@107c000000/interrupt-controller@7cd00000            /soc@107c000000/serial@7d001000         /soc@107c000000/gpio@7d517c00         .  /soc@107c000000/interrupt-controller@7fff9000           /chosen         /sd-io-1v8-reg          /sd-vcc-reg          	compatible #address-cells #size-cells interrupt-parent model #clock-cells clock-output-names clock-frequency phandle device_type reg enable-method d-cache-size d-cache-line-size d-cache-sets i-cache-size i-cache-line-size i-cache-sets next-level-cache cache-level cache-unified ranges no-map reusable linux,cma-default alloc-ranges reg-names interrupts clocks clock-names mmc-ddr-3_3v vqmmc-supply vmmc-supply bus-width sd-uhs-sdr50 sd-uhs-ddr50 sd-uhs-sdr104 #mbox-cells arm,primecell-periphid status interrupt-controller #interrupt-cells gpio-controller #gpio-cells brcm,gpio-bank-widths serial10 stdout-path regulator-name regulator-min-microvolt regulator-max-microvolt regulator-boot-on regulator-always-on regulator-settling-time-us gpios states enable-active-high clk_osc clk_vpu clk_uart clk_emmc2 cpus cpu0 l2_cache_l0 cpu1 l2_cache_l1 cpu2 l2_cache_l2 cpu3 l2_cache_l3 l3_cache rmem cma soc sdio1 system_timer mailbox local_intc uart10 gio_aon gicv2 chosen sd_io_1v8_reg sd_vcc_reg 