  e   8  ^   (              ^                             !    bananapi,bpi-r64 mediatek,mt7622                                     +            7Bananapi BPI-R64          	   =embedded       opp-table             operating-points-v2           J         U      opp-300000000            ]    À         d ~      opp-437500000            ]    `         d B@      opp-600000000            ]    #F          d       opp-812500000            ]    0m          d       opp-1025000000           ]    =B@         d 0      opp-1137500000           ]    C`         d O      opp-1262500000           ]    K@8         d       opp-1350000000           ]    Pw]         d 0         cpus                         +       cpu@0            rcpu           arm,cortex-a53           ~                              	         cpu intermediate                                     psci             M|m                                                         U   	      cpu@1            rcpu           arm,cortex-a53           ~                             	         cpu intermediate                                     psci             M|m                                                         U   
      l2-cache              cache                                U            dummy40m              fixed-clock          bZ         *             U         oscillator            fixed-clock         *             }x@        7clkxtal          U          psci              arm,psci-0.2             smc       pmu           arm,cortex-a53-pmu          J                 	           U   	   
      reserved-memory                      +            h   secmon@43000000          ~    C                   o         thermal-zones      cpu-thermal         v                              trips      cpu-passive                              Epassive          U         cpu-active                              Eactive           U         cpu-hot          S                   Ehot          U         cpu-crit                             	   Ecritical             cooling-maps       map0                          	   
      map1                          	   
      map2                          	   
               timer             arm,armv8-timer                   0  J                              
        infracfg@10000000              mediatek,mt7622-infracfg syscon          ~                      *                       U         pwrap@10001000            mediatek,mt7622-pwrap            ~            P        pwrap                           	   spi wrap                          pwrap           J                  okay            default               regulators            mediatek,mt6380-regulator      buck-vcore1         vcore1          - 	'        E DV        ]  j         r                  U         buck-vcore          vcore           - 	'        E DV        ]  j         r               buck-vrf            vrf         - O        E X        ]             r               ldo-vm          vm          -         E \        ]             r                  U         ldo-va          va          - !        E 2Z        ]             r               ldo-vphy            vphy            - w@        E w@        ]             r               ldo-vddr            vddr            -         E         ]             r               ldo-vt          vt          - !        E 2Z        ]             r                     pericfg@10002000              mediatek,mt7622-pericfg syscon           ~                      *                       U         power-controller@10006000             mediatek,mt7622-scpsys syscon                       ~     `              0  J                                                                  M         hif_sel          U         ir-receiver@10009000              mediatek,mt7622-cir          ~                     J                               8         clk bus         okay            default                  interrupt-controller@10200620         .    mediatek,mt7622-sysirq mediatek,mt6577-sysirq                                            ~                       U         efuse@10206000        %    mediatek,mt7622-efuse mediatek,efuse             ~     `                             +      calib@198            ~              U            clock-controller@10209000             mediatek,mt7622-apmixedsys           ~                     *            U         clock-controller@10210000             mediatek,mt7622-topckgen             ~    !                 *            U         rng@1020f000          (    mediatek,mt7622-rng mediatek,mt7623-rng          ~                                     rng       pinctrl@10211000              mediatek,mt7622-pinctrl           ~    !             P              
  base eint                                             g                 J                                          U      asm_sel                     Z                   emmc-pins-default            U   '   mux         emmc            'emmc emmc_rst         conf-cmd-dat          ,  .NDL0 NDL1 NDL2 NDL3 NDL4 NDL5 NDL6 NDL7 NRB          3         @      conf-clk            .NCLE             M         emmc-pins-uhs            U   (   mux         emmc            'emmc          conf-cmd-dat          ,  .NDL0 NDL1 NDL2 NDL3 NDL4 NDL5 NDL6 NDL7 NRB          3        \            @      conf-clk            .NCLE            \            M         eth-pins       mux         eth         'mdc_mdio rgmii_via_gmac2             i2c1-pins            U      mux         i2c         'i2c1_0           i2c2-pins            U      mux         i2c         'i2c2_0           i2s1-pins      mux         i2s       0  'i2s_out_mclk_bclk_ws i2s1_in_data i2s1_out_data       conf          *  .I2S1_IN I2S1_OUT I2S_BCLK I2S_WS I2S_MCLK           \            M         irrx-pins            U      mux         ir          'ir_1_rx          irtx-pins      mux         ir          'ir_1_tx          parallel-nand-pins           U   "   mux         flash         	  'par_nand             pcie0-pins           U   4   mux         pcie          -  'pcie0_pad_perst pcie0_1_waken pcie0_1_clkreq             pcie1-pins           U   6   mux         pcie          -  'pcie1_pad_perst pcie1_0_waken pcie1_0_clkreq             pmic-bus-pins            U      mux         pmic          	  'pmic_bus             pwm-pins             U      mux         pwm       <  'pwm_ch1_0 pwm_ch2_0 pwm_ch3_2 pwm_ch4_1 pwm_ch5_0 pwm_ch6_0          wled-pins      mux         led         'wled             sd0-pins-default             U   +   mux         sd          'sd_0          conf-cmd-data         *  .I2S2_OUT I2S4_IN I2S3_IN I2S2_IN I2S4_OUT            3        \            @      conf-clk          	  .I2S3_OUT            \            M      conf-cd         .TXD3             @         sd0-pins-uhs             U   ,   mux         sd          'sd_0          conf-cmd-data         *  .I2S2_OUT I2S4_IN I2S3_IN I2S2_IN I2S4_OUT            3         @      conf-clk          	  .I2S3_OUT             M         serial-nand-pins             U   #   mux         flash           'snfi             spic0-pins           U      mux         spi         'spic0_0          spic1-pins           U   %   mux         spi         'spic1_0          spi-nor-pins       mux         flash           'spi_nor          uart0-pins           U      mux         uart            'uart0_0_tx_rx            uart2-pins           U      mux         uart            'uart2_1_tx_rx            watchdog-pins            U      mux       	  watchdog          	  'watchdog                watchdog@10212000         (    mediatek,mt7622-wdt mediatek,mt6589-wdt          ~    !                 default                    okay          rtc@10212800          %    mediatek,mt7622-rtc mediatek,soc-rtc             ~    !(                J                                  rtc       interrupt-controller@10300000             arm,gic-400                                       @   ~    1             2             4              6                   U         cci@10390000              arm,cci-400                      +            ~    9                 h        9        slave-if@1000             arm,cci-400-ctrl-if       	  kace-lite             ~            slave-if@4000             arm,cci-400-ctrl-if         kace          ~  @          slave-if@5000             arm,cci-400-ctrl-if syscon          kace          ~  P             U         pmu@9000              arm,cci-400-pmu,r1           ~     P       <  J       :          ;          <          =          >            adc@11001000              mediatek,mt7622-auxadc           ~                                     main            z            U         serial@11002000       *    mediatek,mt7622-uart mediatek,mt6577-uart            ~                      J       [                  @            	   baud bus            okay            default                  serial@11003000       *    mediatek,mt7622-uart mediatek,mt6577-uart            ~     0                J       \                  @            	   baud bus          	  disabled          serial@11004000       *    mediatek,mt7622-uart mediatek,mt6577-uart            ~     @                J       ]                  @            	   baud bus          	  disabled            default                  serial@11005000       *    mediatek,mt7622-uart mediatek,mt6577-uart            ~     P                J       ^                  @            	   baud bus          	  disabled          pwm@11006000              mediatek,mt7622-pwm          ~     `                           J       M         @         <      	                                          '   top main pwm1 pwm2 pwm3 pwm4 pwm5 pwm6          okay            default                  i2c@11007000              mediatek,mt7622-i2c           ~     p                             J       T                                   
      	   main dma                         +          	  disabled          i2c@11008000              mediatek,mt7622-i2c           ~                                 J       U                                   
      	   main dma                         +            okay            default                  i2c@11009000              mediatek,mt7622-i2c           ~                                  J       V                                   
      	   main dma                         +            okay            default                  spi@1100a000              mediatek,mt7622-spi          ~                     J       v                        A               parent-clk sel-clk spi-clk                       +            okay            default                  thermal@1100b000                         mediatek,mt7622-thermal          ~                     J       N                                 therm auxadc                                                           calibration-data             U         serial@1100c000       '    mediatek,mt7622-btif mediatek,mtk-btif           ~                     J       Z                                                okay       bluetooth             mediatek,mt7622-bluetooth                                       ref          nand-controller@1100d000              mediatek,mt7622-nfc          ~                     J       `                                 nfi_clk pad_clk            !                     +          	  disabled            default            "      spi@1100d000              mediatek,mt7622-snand            ~                     J       `                                 nfi_clk pad_clk         (   !                     +            okay            default            #         U   $   flash@0       	    spi-nand             ~            8           I           (   $   partitions            fixed-partitions                         +      partition@0         Zbl2          ~                `      partition@80000         Zfip          ~                `      partition@280000            Zubi          ~ (                   ecc@1100e000              mediatek,mt7622-ecc          ~                     J       _                           nfiecc_clk          okay             U   !      spi@11014000          (    mediatek,mt7622-nor mediatek,mt8173-nor          ~    @                             ?         spi sf                       +          	  disabled          spi@11016000              mediatek,mt7622-spi          ~    `                J       z                        B               parent-clk sel-clk spi-clk                       +          	  disabled            default            %      serial@11019000       *    mediatek,mt7622-uart mediatek,mt6577-uart            ~                    J       Y                  @            	   baud bus          	  disabled          clock-controller@11220000             mediatek,mt7622-audsys syscon            ~    "                  *            U   &   audio-controller              mediatek,mt7622-audio           J                          	  jafe asys                        P      Q      k      l      Y      Z      [      \      _      `      a      b      g      h      i      j   &      &   	   &   
   &      &      &      &      &      &      &      &   '   &   (   &       &   .   &      &           infra_sys_audio_clk top_audio_mux1_sel top_audio_mux2_sel top_audio_a1sys_hp top_audio_a2sys_hp i2s0_src_sel i2s1_src_sel i2s2_src_sel i2s3_src_sel i2s0_src_div i2s1_src_div i2s2_src_div i2s3_src_div i2s0_mclk_en i2s1_mclk_en i2s2_mclk_en i2s3_mclk_en i2so0_hop_ck i2so1_hop_ck i2so2_hop_ck i2so3_hop_ck i2si0_hop_ck i2si1_hop_ck i2si2_hop_ck i2si3_hop_ck asrc0_out_ck asrc1_out_ck asrc2_out_ck asrc3_out_ck audio_afe_pd audio_afe_conn_pd audio_a1sys_pd audio_a2sys_pd             z      F      G      c      d              1      2                            mmc@11230000              mediatek,mt7622-mmc          ~    #                 J       O                        C         source hclk                       hrst            okay            default state_uhs              '           (        ?                                        )           *        z      D              .               mmc@11240000              mediatek,mt7622-mmc          ~    $                 J       P                        8         source hclk                       hrst            okay            default state_uhs              +           ,        ?                            '      Q              )           )        z      E              .      wmac@18000000             mediatek,mt7622-wmac             ~                      J                  0           okay                        clock-controller@1a000000             mediatek,mt7622-ssusbsys             ~                      *                       U   -      usb@1a0c0000          '    mediatek,mt7622-xhci mediatek,mtk-xhci            ~                 G              	  mac ippc            J                                     -      -      -      -            sys_ck ref_ck mcu_ck dma_ck         B   .      /      0           okay            G   )        U   1      t-phy@1a0c4000        .    mediatek,mt7622-tphy mediatek,generic-tphy-v1            ~    @                             +            h        okay       usb-phy@1a0c4800             ~    H                a               -            ref          U   .      usb-phy@1a0c4900             ~    I                a                         ref          U   /      usb-phy@1a0c5000             ~    P                a               -             ref          U   0         clock-controller@1a100800             mediatek,mt7622-pciesys          ~                    *                       U   2      pciecfg@1a140000               mediatek,generic-pciecfg syscon          ~                   pcie@1a143000             mediatek,mt7622-pcie             rpci          ~    0                port0           l                         +           J                	  jpcie_irq          0      2   
   2      2      2   	   2      2         2   sys_ck0 ahb_ck0 aux_ck0 axi_ck0 obff_ck0 pipe_ck0                         }               h                                  okay                                            `                    3                      3                     3                     3           default            4   interrupt-controller                                              U   3         pcie@1a145000             mediatek,mt7622-pcie             rpci          ~    P                port1           l                        +           J                	  jpcie_irq          0      2      2      2       2      2      2         2   sys_ck1 ahb_ck1 aux_ck1 axi_ck1 obff_ck1 pipe_ck1                         }               h       (       (                  okay                                            `                    5                      5                     5                     5           default            6   interrupt-controller                                              U   5         sata@1a200000         '    mediatek,mt7622-ahci mediatek,mtk-ahci           ~                      J                  jhostc         (      2      2      2      2      2            ahb axi asic rbc pm         B   7         	  sata-phy                                        2      2      2           axi sw reg             2      	  disabled          t-phy         .    mediatek,mt7622-tphy mediatek,generic-tphy-v1                        +            h      	  disabled       sata-phy@1a243000            ~    $0                       7         ref         a            U   7         clock-controller@1af00000             mediatek,mt7622-hifsys           ~             p        *            U   =      clock-controller@1b000000             mediatek,mt7622-ethsys syscon            ~                      *                       U   8      dma-controller@1b007000           mediatek,mt7622-hsdma            ~     p                J                      8             hsdma                                              pcie-mirror@10000400          #    mediatek,mt7622-pcie-mirror syscon           ~                      U   <      wed@1020a000              mediatek,mt7622-wed syscon           ~                     J                   U   :      wed@1020b000              mediatek,mt7622-wed syscon           ~                     J                   U   ;      ethernet@1b100000             mediatek,mt7622-eth          ~                   $  J                                    X         ;   8      8      8      8      9       9      9      9         /            \   ethif esw gp0 gp1 gp2 sgmii_tx250m sgmii_rx250m sgmii_cdr_ref sgmii_cdr_fb sgmii_ck eth2pll                           8           9                       :   ;           <        2   =         B                     +            okay       mac@0             mediatek,eth-mac             ~            2500base-x           U   ?   fixed-link            	         O         [         mac@1             mediatek,eth-mac             ~           rgmii            U   >   fixed-link                     O         [         mdio-bus                         +       switch@1f             mediatek,mt7531          ~                               a      5           u      6       ports                        +       port@0           ~            Zwan       port@1           ~           Zlan0          port@2           ~           Zlan1          port@3           ~           Zlan2          port@4           ~           Zlan3          port@5           ~              >        rgmii      fixed-link                     O         [         port@6           ~           Zcpu            ?        2500base-x     fixed-link            	         O         [                     sgmiisys@1b128000              mediatek,mt7622-sgmiisys syscon          ~           0         *            U   9      aliases         /serial@11002000          chosen          serial0:115200n8          0  earlycon=uart8250,mmio32,0x11002000 swiotlb=512       gpio-keys         
    gpio-keys      factory-key         Zfactory                                     wps-key         Zwps                         f            leds          
    gpio-leds      led-0           Zbpi-r64:pio:green                            Y            off       led-1           Zbpi-r64:pio:red                          X            off          memory@40000000          ~    @       @            rmemory        regulator-1p8v            regulator-fixed         fixed-1.8V          - w@        E w@         r         U   *      regulator-3p3v            regulator-fixed         fixed-3.3V          - 2Z        E 2Z                  r         U   )      regulator-5v              regulator-fixed       	  fixed-5V            - LK@        E LK@                  r         U   1         	compatible interrupt-parent #address-cells #size-cells model chassis-type opp-shared phandle opp-hz opp-microvolt device_type reg clocks clock-names operating-points-v2 #cooling-cells enable-method clock-frequency cci-control-port next-level-cache proc-supply sram-supply cache-level cache-unified #clock-cells clock-output-names interrupts interrupt-affinity ranges no-map polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device #reset-cells reg-names resets reset-names status pinctrl-names pinctrl-0 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-always-on regulator-boot-on #power-domain-cells infracfg interrupt-controller #interrupt-cells gpio-controller #gpio-cells gpio-ranges gpio-hog gpios output-high function groups pins input-enable bias-pull-up bias-pull-down drive-strength interface-type #io-channel-cells #pwm-cells clock-div #thermal-sensor-cells mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names reg-shift reg-io-width power-domains ecc-engine nand-ecc-engine spi-tx-bus-width spi-rx-bus-width label read-only interrupt-names assigned-clocks assigned-clock-parents assigned-clock-rates pinctrl-1 max-frequency cap-mmc-highspeed mmc-hs200-1_8v vmmc-supply vqmmc-supply non-removable cap-sd-highspeed cd-gpios mediatek,infracfg phys vusb33-supply vbus-supply #phy-cells linux,pci-domain bus-range interrupt-map-mask interrupt-map phy-names ports-implemented mediatek,phy-mode #dma-cells dma-requests mediatek,ethsys mediatek,sgmiisys mediatek,wed mediatek,pcie-mirror mediatek,hifsys dma-coherent full-duplex pause interrupts-extended reset-gpios ethernet serial0 stdout-path bootargs linux,code color default-state 