  .   8  +   (              *                             "    amd,seattle-overdrive amd,seattle                                    +         3   7AMD Seattle (Rev.B1) Development Board (Overdrive)     interrupt-controller@e1101000             arm,gic-400 arm,cortex-a15-gic            =         R                        +         @   c                                                               g      	           r                              y      v2m@e0080000              arm,gic-v2m-frame                      c                       y            timer             arm,armv8-timer       0   g                              
        smb           simple-bus                       +             r                                   clk100mhz_0           fixed-clock                                 adl3clk_100mhz        clk375mhz             fixed-clock                       Z         ccpclk_375mhz         clk333mhz             fixed-clock                       -@         sataclk_333mhz           y         clk500mhz_0           fixed-clock                       e          pcieclk_500mhz        clk500mhz_1           fixed-clock                       e          dmaclk_500mhz         clk250mhz_4           fixed-clock                       沀         miscclk_250mhz           y         clk100mhz_1           fixed-clock                                 uartspiclk_100mhz            y         sata@e0300000             snps,dwc-ahci            c    0                  g      c                                                  sata@e0d00000            okay              snps,dwc-ahci            c                      g      b                                                          iommu@e0200000            arm,mmu-401          c                                   g      L         L                                  y         iommu@e0c00000            arm,mmu-401          c                                  g      K         K                                  y         i2c@e1000000             okay              snps,designware-i2c          c                       g      e                     i2c@e0050000             okay              snps,designware-i2c          c                      g      T                     serial@e1010000           arm,pl011 arm,primecell          c                      g      H                          uartclk apb_pclk          spi@e1020000             okay              arm,pl022 arm,primecell          c                               g      J                     	  apb_pclk          spi@e1030000             okay              arm,pl022 arm,primecell          c                               g      I                     	  apb_pclk            (                        +       sdcard@0              mmc-spi-slot             c            /1-         A    H        P            `            o                         gpio@e1040000         	   disabled              arm,pl061 arm,primecell                     c                               g      g             =         R                     	  apb_pclk          gpio@e1050000            okay              arm,pl061 arm,primecell                     c                                =         R            g      f                     	  apb_pclk          gpio@e0020000            okay              arm,pl061 arm,primecell                     c                                =         R            g      n                     	  apb_pclk          gpio@e0030000            okay              arm,pl061 arm,primecell                     c                                =         R            g      m                     	  apb_pclk          gpio@e0080000            okay              arm,pl061 arm,primecell                     c                                =         R            g      i                     	  apb_pclk          ccp@e0100000             okay              amd,ccp-seattle-v1a          c                      g                                                 @      B                 pcie@f0000000             pci-host-ecam-generic                        +            R           pci                                    c                                                                                                             !                                  "                                  #                                  $                                  %                                  &                                  '                                  (                                  )                                  *                                  +                      C                                T   r                               @       @                                                                 okay          iommu@e0a00000            arm,mmu-401          c                                  g      M         M                                  y         ccn@e8000000              arm,ccn-504          c                       g      |         kcs@e0010000             okay          	    ipmi-kcs            ipmi             c                      g                                     clk250mhz_0           fixed-clock                       沀         xgmacclk0_dma_250mhz             y   	      clk250mhz_1           fixed-clock                       沀         xgmacclk0_ptp_250mhz             y   
      clk250mhz_2           fixed-clock                       沀         xgmacclk1_dma_250mhz             y         clk250mhz_3           fixed-clock                       沀         xgmacclk1_ptp_250mhz             y         xgmac@e0700000            amd,xgbe-seattle-v1a          P   c    p             x             $            %         `    %              H   g      E         Z         [         \         ]         C            %        ?            M                  ]                 q   
   
                                                                                 	   
        dma_clk ptp_clk         xgmii                                      xgmac@e0900000            amd,xgbe-seattle-v1a          P   c                              $            %        `    %              H   g      D         U         V         W         X         B            %        ?            M                  ]                 q   
   
                                                                                            dma_clk ptp_clk         xgmii                                      iommu@e0600000            arm,mmu-401          c    `                              g      P         P                                  y         iommu@e0800000            arm,mmu-401          c                                  g      O         O                                  y            cpus                         +       cpu-map    cluster0       core0                    core1                       cluster1       core0                    core1                       cluster2       core0                    core1                       cluster3       core0                    core1                          cpu@0           cpu           arm,cortex-a57           c            psci                          @                              *   @        <           I            y         cpu@1           cpu           arm,cortex-a57           c           psci                          @                              *   @        <           I            y         cpu@100         cpu           arm,cortex-a57           c           psci                          @                              *   @        <           I            y         cpu@101         cpu           arm,cortex-a57           c          psci                          @                              *   @        <           I            y         cpu@200         cpu           arm,cortex-a57           c           psci                          @                              *   @        <           I            y         cpu@201         cpu           arm,cortex-a57           c          psci                          @                              *   @        <           I            y         cpu@300         cpu           arm,cortex-a57           c           psci                          @                              *   @        <           I            y         cpu@301         cpu           arm,cortex-a57           c          psci                          @                              *   @        <           I            y            l2-cache0                          @                    R        `            y         l2-cache1                          @                    R        `            y         l2-cache2                          @                    R        `            y         l2-cache3                          @                    R        `            y         l3-cache            q                          @                     R         y         pmu           arm,cortex-a57-pmu        `   g                           	          
                                                    }                              chosen          /smb/serial@e1010000          psci              arm,psci-0.2            smc          	compatible interrupt-parent #address-cells #size-cells model interrupt-controller #interrupt-cells reg interrupts ranges phandle msi-controller dma-ranges #clock-cells clock-frequency clock-output-names clocks iommus dma-coherent status #global-interrupts #iommu-cells clock-names spi-controller num-cs spi-max-frequency voltage-ranges pl022,interface pl022,com-mode pl022,rx-level-trig pl022,tx-level-trig #gpio-cells gpio-controller amd,zlib-support device_type bus-range msi-parent interrupt-map-mask interrupt-map iommu-map reg-size reg-spacing amd,per-channel-interrupt amd,speed-set amd,serdes-blwc amd,serdes-cdr-rate amd,serdes-pq-skew amd,serdes-tx-amp amd,serdes-dfe-tap-config amd,serdes-dfe-tap-enable mac-address phy-mode cpu enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets l2-cache cache-unified next-level-cache cache-level interrupt-affinity stdout-path 