Ðþí  0   H  ´   (            |  l    €                                           Foundation-v8A        $   arm,foundation-aarch64 arm,vexpress                      "            1      chosen           =serial0:115200n8          aliases       /   I/bus@8000000/iofpga-bus@300000000/serial@90000        /   Q/bus@8000000/iofpga-bus@300000000/serial@a0000        /   Y/bus@8000000/iofpga-bus@300000000/serial@b0000        /   a/bus@8000000/iofpga-bus@300000000/serial@c0000        cpus             "            1       cpu@0            icpu       
   arm,armv8            u                 y            Špsci          cpu@1            icpu       
   arm,armv8            u                y            Špsci          cpu@2            icpu       
   arm,armv8            u                y            Špsci          cpu@3            icpu       
   arm,armv8            u                y            Špsci          l2-cache0            cache            ˜             ¤         ²            memory@80000000          imemory            u    €       €      €       €         timer            arm,armv8-timer       0   º                              
           Åõá       pmu          arm,armv8-pmuv3       0   º       <          =          >          ?         spe-pmu       '   arm,statistical-profiling-extension-v1           º               watchdog@2a440000            arm,sbsa-gwdt             u    *D             *E                  º                   Õ         clock-24000000           fixed-clock          á             Ån6          îv2m:clk24mhz             ²         clock-1000000            fixed-clock          á             Å B@         îv2m:refclk1mhz        clock-32768          fixed-clock          á             Å  €          îv2m:refclk32khz       bus@8000000          arm,vexpress,v2m-p1 simple-bus           "            1         x                                                                                                                                       ?     `  ,                                                                                                                                                                                                                                                                         	              	              
              
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        !              !              "              "              #              #              $              $              %              %              &              &              '              '              (              (              )              )              *              *      ethernet@202000000           smsc,lan91c111           u                  º         iofpga-bus@300000000             simple-bus           "            1                             sysreg@10000             arm,vexpress-sysreg          u            serial@90000             arm,pl011 arm,primecell          u 	              º           :              Auartclk apb_pclk          serial@a0000             arm,pl011 arm,primecell          u 
              º           :              Auartclk apb_pclk          serial@b0000             arm,pl011 arm,primecell          u               º           :              Auartclk apb_pclk          serial@c0000             arm,pl011 arm,primecell          u               º           :              Auartclk apb_pclk          virtio@130000            virtio,mmio          u               º   *            interrupt-controller@2f000000            arm,gic-v3                      "            1                   /               M      P   u    /              /              ,               ,              ,ð                  º      	            ²      msi-controller@2f020000          arm,gic-v3-its           b        q            u               psci             arm,psci-1.0             ‘smc          	model compatible interrupt-parent #address-cells #size-cells stdout-path serial0 serial1 serial2 serial3 device_type reg next-level-cache enable-method cache-level cache-unified phandle interrupts clock-frequency timeout-sec #clock-cells clock-output-names ranges #interrupt-cells interrupt-map-mask interrupt-map clocks clock-names interrupt-controller msi-controller #msi-cells 