  -   H  *H   (              *                                                FVP Base RevC            arm,fvp-base-revc arm,vexpress                       "            1      clock-24000000           fixed-clock          =             Jn6          Zv2m:clk24mhz             m         clock-1000000            fixed-clock          =             J B@         Zv2m:refclk1mhz           m         clock-32768          fixed-clock          =             J            Zv2m:refclk32khz          m         regulator-3v3            regulator-fixed          u3V3           2Z          2Z                   m         mcc          arm,vexpress,config-bus                clock-controller             arm,vexpress-osc                            jep         =             Zv2m:oscclk1          m         reset            arm,vexpress-reset                        muxfpga          arm,vexpress-muxfpga                          shutdown             arm,vexpress-shutdown                         reboot           arm,vexpress-reboot             	          dvimode          arm,vexpress-dvimode                             bus@8000000          simple-bus           "            1                                                          ?     x  2                                                                                                                                                                                                                                                                                                             	                  	              
                  
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                !                  !              "                  "              #                  #              $                  $              %                  %              &                  &              '                  '              (                  (              )                  )              *                  *              +                  +              ,                  ,              .                  .      motherboard-bus@8000000          arm,vexpress,v2m-p1 simple-bus           "            1         x                                                                                                                 @rs2    flash@0          arm,vexpress-flash cfi-flash            S                             W         ethernet@202000000           smsc,lan91c111          S                 b         iofpga-bus@300000000             simple-bus           "            1                       !     sysreg@10000             arm,vexpress-sysreg         S               m        }            m         sysctl@20000             arm,sp810 arm,primecell         S                               refclk timclk apb_pclk           =         0   Ztimerclken0 timerclken1 timerclken2 timerclken3                                                                m         aaci@40000           arm,pl041 arm,primecell         S              b                    	  apb_pclk          mmc@50000            arm,pl180 arm,primecell         S              b   	   
                                                                                mclk apb_pclk         kmi@60000            arm,pl050 arm,primecell         S              b                         KMIREFCLK apb_pclk        kmi@70000            arm,pl050 arm,primecell         S              b                         KMIREFCLK apb_pclk        serial@90000             arm,pl011 arm,primecell         S 	             b                         uartclk apb_pclk          serial@a0000             arm,pl011 arm,primecell         S 
             b                         uartclk apb_pclk          serial@b0000             arm,pl011 arm,primecell         S              b                         uartclk apb_pclk          serial@c0000             arm,pl011 arm,primecell         S              b                         uartclk apb_pclk          watchdog@f0000           arm,sp805 arm,primecell         S              b                          wdog_clk apb_pclk         timer@110000             arm,sp804 arm,primecell         S              b                                   timclken1 timclken2 apb_pclk          timer@120000             arm,sp804 arm,primecell         S              b                                  timclken1 timclken2 apb_pclk          virtio@130000            virtio,mmio         S              b   *      rtc@170000           arm,pl031 arm,primecell         S              b                    	  apb_pclk          clcd@1f0000          arm,pl111 arm,primecell         S            	  combined            b                         clcdclk apb_pclk               	   port       endpoint               
                           m               virtio@140000            virtio,mmio         S              b   +      virtio@150000            virtio,mmio         S              b   ,      virtio@200000            virtio,mmio         S               b   .      	  7disabled                   chosen          >serial0:115200n8          aliases       G  J/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@90000        G  R/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@a0000        G  Z/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@b0000        G  b/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@c0000        psci             arm,psci-0.2            jsmc       cpus             "            1       cpu@0           qcpu       
   arm,armv8           S                }psci                          @                                 @                            cpu@100         qcpu       
   arm,armv8           S               }psci                          @                                 @                            cpu@200         qcpu       
   arm,armv8           S               }psci                          @                                 @                            cpu@300         qcpu       
   arm,armv8           S               }psci                          @                                 @                            cpu@10000           qcpu       
   arm,armv8           S               }psci                          @                                 @                            cpu@10100           qcpu       
   arm,armv8           S              }psci                          @                                 @                            cpu@10200           qcpu       
   arm,armv8           S              }psci                          @                                 @                            cpu@10300           qcpu       
   arm,armv8           S              }psci                          @                                 @                            l2-cache0            cache                         @                                         m         l2-cache1            cache                         @                                         m            memory@80000000         qmemory           S                                 reserved-memory          "            1               vram@18000000            shared-dma-pool         S                                m   	         interrupt-controller@2f000000            arm,gic-v3                      "            1                           P  S    /              /              ,               ,              ,                 b      	            m      msi-controller@2f020000         *            arm,gic-v3-its          S    /                  5         m            timer            arm,armv8-timer       0  b                                 
         pmu          arm,armv8-pmuv3         b               spe-pmu       '   arm,statistical-profiling-extension-v1          b               pci@40000000             "            1                       pci-host-ecam-generic           qpci         D               S    @                         P       P                  2                                                                                                                                                                               N                      V                       `         m      iommu@2b400000           arm,smmu-v3         S    +@               0  b       J          O          K          M           eventq gerror priq cmdq-sync             `        {                          m         panel            arm,rtsm-display       port       endpoint                        m   
               	model compatible interrupt-parent #address-cells #size-cells #clock-cells clock-frequency clock-output-names phandle regulator-name regulator-min-microvolt regulator-max-microvolt regulator-always-on arm,vexpress,config-bridge arm,vexpress-sysreg,func freq-range ranges #interrupt-cells interrupt-map-mask interrupt-map arm,v2m-memory-map reg bank-width interrupts gpio-controller #gpio-cells clocks clock-names assigned-clocks assigned-clock-parents cd-gpios wp-gpios max-frequency vmmc-supply interrupt-names memory-region remote-endpoint arm,pl11x,tft-r0g0b0-pads status stdout-path serial0 serial1 serial2 serial3 method device_type enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache cache-level cache-unified no-map interrupt-controller #msi-cells msi-controller bus-range msi-map iommu-map dma-coherent ats-supported #iommu-cells msi-parent 