     8     (            	                               +    hisilicon,hi3660-hikey960 hisilicon,hi3660                                   +         	   7HiKey960       psci              arm,psci-0.2             =smc       cpus                         +       cpu-map    cluster0       core0            D         core1            D         core2            D         core3            D            cluster1       core0            D         core1            D         core2            D         core3            D   	            cpu@0             arm,cortex-a53           Hcpu          T                 Xpsci             f   
         w                 P                                                    n                  cpu@1             arm,cortex-a53           Hcpu          T                Xpsci             f   
         w                 P                                                          cpu@2             arm,cortex-a53           Hcpu          T                Xpsci             f   
         w                 P                                                          cpu@3             arm,cortex-a53           Hcpu          T                Xpsci             f   
         w                 P                                                          cpu@100           arm,cortex-a73           Hcpu          T                Xpsci             f            w                                                                    &                  cpu@101           arm,cortex-a73           Hcpu          T               Xpsci             f            w                                                                           cpu@102           arm,cortex-a73           Hcpu          T               Xpsci             f            w                                                                           cpu@103           arm,cortex-a73           Hcpu          T               Xpsci             f            w                                                                     	      idle-states          psci       cpu-sleep-0           arm,idle-state                                         ,          <                    cluster-sleep-0           arm,idle-state                                        ,  @        <                    cpu-sleep-1           arm,idle-state                                         ,  &        <                    cluster-sleep-1           arm,idle-state                                         ,  T        <                       l2-cache0             cache           M            Y            
      l2-cache1             cache           M            Y                     opp-table-0           operating-points-v2          g               opp00           r    @        y 
`               opp01           r    ;        y 5                opp02           r    SҀ        y                opp03           r    eE@        y B@               opp04           r    m5         y                   opp-table-1           operating-points-v2          g               opp10           r    5ү        y 
`               opp11           r    T@        y 5                opp12           r    k@        y                opp13           r    }         y B@               opp14           r    B        y                   interrupt-controller@e82b0000             arm,gic-400       @   T    +            +              +@             +`                                                        	                    a53-pmu           arm,cortex-a53-pmu        0                                                                    a73-pmu           arm,cortex-a73-pmu        0                                                              	      timer             arm,armv8-timer                   0                                
        soc           simple-bus                       +               crg_ctrl@fff35000              hisilicon,hi3660-crgctrl syscon          T    P                                     crg_rst_controller            hisilicon,hi3660-reset                                          pctrl@e8a09000            hisilicon,hi3660-pctrl syscon            T    蠐                                M      crg_ctrl@fff34000              hisilicon,hi3660-pmuctrl syscon          T    @                         sctrl@fff0a000            hisilicon,hi3660-sctrl syscon            T                                   9      iomcu@ffd7e000            hisilicon,hi3660-iomcu syscon            T                                         reset             hisilicon,hi3660-reset                                          mailbox@e896b000              hisilicon,hi3660-mbox            T    薰                                                                 stub_clock@e896b500           hisilicon,hi3660-stub-clk            T    薵                                                          timer@fff14000            arm,sp804 arm,primecell          T    @                       0          1                                       timer1 timer2 apb_pclk        i2c@ffd71000              snps,designware-i2c          T                           v                        +            ,                        <                  Cdefault         Q              [okay            bLS-I2C0       i2c@ffd72000              snps,designware-i2c          T                            w                        +            ,                        <                  Cdefault         Q              [okay       rt1711h@4e            richtek,rt1711h          T   N        [okay                                      Cdefault         Q      connector             usb-c-connector         bUSB-C           hdual            rdual            }sink            2        2Ad            ports                        +       port@1           T      endpoint                           P               port                         +       endpoint@0           T                           O            adv7533@39          [okay              adi,adv7533          T   9              ports                        +       port@0           T          port@1           T                  i2c@fdf0c000              snps,designware-i2c          T                           Q                        +            ,                7        <      x           Cdefault         Q       !      	  [disabled          i2c@fdf0b000              snps,designware-i2c          T                          :                        +            ,                6        <      `           Cdefault         Q   "   #        [okay            bLS-I2C1       serial@fdf02000           arm,pl011 arm,primecell          T                            J                  h               uartclk apb_pclk            Cdefault         Q   $   %      	  [disabled          serial@fdf00000           arm,pl011 arm,primecell          T                            K           rx tx              &      &                  9      9         uartclk apb_pclk            Cdefault         Q   '   (      	  [disabled          serial@fdf03000           arm,pl011 arm,primecell          T    0                       L           rx tx              &      &                  :               uartclk apb_pclk            Cdefault         Q   )   *      	  [disabled          serial@ffd74000           arm,pl011 arm,primecell          T    @                       r                                 uartclk apb_pclk            Cdefault         Q   +   ,        [okay          	  bLS-UART0          serial@fdf01000           arm,pl011 arm,primecell          T                           M           rx tx              &      &                  ;      ;         uartclk apb_pclk            Cdefault         Q   -   .        [okay       bluetooth             ti,wl1837-st               /                -         serial@fdf05000           arm,pl011 arm,primecell          T    P                       N           rx tx              &      &   	               <      <         uartclk apb_pclk            Cdefault         Q   0   1      	  [disabled          serial@fff32000           arm,pl011 arm,primecell          T                            O                  
               uartclk apb_pclk            Cdefault         Q   2   3        [okay          	  bLS-UART1          dma@fdf30000              hisilicon,k3-dma-1.0             T                                                                                          >         .        9hi3660_dma              &      dma-controller@e804b000           hisilicon,hisi-pcm-asp-dma-1.0           T                                                                        Basp_dma_irq       rtc@fff04000              arm,pl031 arm,primecell          T    @                       .                        	   apb_pclk          gpio@e8a0b000             arm,pl061 arm,primecell          T    蠰                       T            R        b           n   4                                                   	   apb_pclk          L  z TP901 [PMU0_SSI] [PMU1_SSI] [PMU2_SSI] [PMU0_CLKOUT] [JTAG_TCK] [JTAG_TMS]       gpio@e8a0c000             arm,pl061 arm,primecell          T                           U            R        b           n   4                                                   	   apb_pclk          C  z[JTAG_TRST_N] [JTAG_TDI] [JTAG_TDO] NC NC [I2C3_SCL] [I2C3_SDA] NC        gpio@e8a0d000             arm,pl061 arm,primecell          T                           V            R        b           n   4                                             !      	   apb_pclk          G  zNC NC NC GPIO-J GPIO_020_HDMI_SEL GPIO-L GPIO_022_UFSBUCK_INT_N GPIO-G        gpio@e8a0e000             arm,pl061 arm,primecell          T                           W            R        b           n   4                                             "      	   apb_pclk          J  z[CSI0_MCLK] [CSI1_MCLK] NC [I2C2_SCL] [I2C2_SDA] [I2C3_SCL] [I2C3_SDA] NC         gpio@e8a0f000             arm,pl061 arm,primecell          T                           X            R        b           n   4                                             #      	   apb_pclk          A  zNC NC PWR_BTN_N GPIO_035_PMU2_EN GPIO_036_USB_HUB_RESET NC NC NC                v      gpio@e8a10000             arm,pl061 arm,primecell          T                            Y            R        b           n   4       &                                      $      	   apb_pclk          Q  zGPIO-H GPIO_041_HDMI_PD TP904 TP905 NC NC GPIO_046_HUB_VDD33_EN GPIO_047_PMU1_EN          gpio@e8a11000             arm,pl061 arm,primecell          T                           Z            R        b           n   4       .                                      %      	   apb_pclk          A  zNC NC NC GPIO_051_WIFI_EN GPIO-I [SD_DAT1] [SD_DAT2] [UART1_RXD]                x      gpio@e8a12000             arm,pl061 arm,primecell          T                            [            R        b           n   4       6                                      &      	   apb_pclk          y  z[UART1_TXD] [UART0_CTS] [UART0_RTS] [UART0_RXD] [UART0_TXD] [SOC_BT_UART4_CTS_N] [SOC_BT_UART4_RTS_N] [SOC_BT_UART4_RXD]          gpio@e8a13000             arm,pl061 arm,primecell          T    0                       \            R        b           n   4       >                                      '      	   apb_pclk          ?  z[SOC_BT_UART4_TXD] NC [PMU_HKADC_SSI] NC GPIO_068_SEL NC NC NC        gpio@e8a14000             arm,pl061 arm,primecell          T    @                       ]            R        b           n   4       F                                      (      	   apb_pclk            zNC NC NC GPIO-K NC NC NC NC       gpio@e8a15000             arm,pl061 arm,primecell          T    P                       ^            R        b           n   4       N                                      )      	   apb_pclk            zNC NC NC NC NC NC NC NC       gpio@e8a16000             arm,pl061 arm,primecell          T    `                       _            R        b           n   4       V                                      *      	   apb_pclk          $  zNC [PCIE_PERST_N] NC NC NC NC NC NC             ?      gpio@e8a17000             arm,pl061 arm,primecell          T    p                       `            R        b            n   4       ^      4      e                                      +      	   apb_pclk            zNC NC NC     NC       gpio@e8a18000             arm,pl061 arm,primecell          T    血                       a            R        b           n   4       f                                      ,      	   apb_pclk            zNC NC NC NC NC NC NC NC       gpio@e8a19000             arm,pl061 arm,primecell          T    衐                       b            R        b           n   4       n                                      -      	   apb_pclk            zNC NC NC NC NC NC NC NC       gpio@e8a1a000             arm,pl061 arm,primecell          T    衠                       c            R        b           n   4       v                                      .      	   apb_pclk          '  zNC NC NC NC NC NC GPIO_126_BT_EN TP902              /      gpio@e8a1b000             arm,pl061 arm,primecell          T    衰                       d            R        b                                      /      	   apb_pclk            z              gpio@e8a1c000             arm,pl061 arm,primecell          T                           e            R        b                                      0      	   apb_pclk            z              gpio@ff3b4000             arm,pl061 arm,primecell          T    ;@                       f            R        b           n   5                                              1      	   apb_pclk          m  z[UFS_REF_CLK] [UFS_RST_N] [SPI1_SCLK] [SPI1_DIN] [SPI1_DOUT] [SPI1_CS] GPIO_150_USER_LED1 GPIO_151_USER_LED2                >      gpio@ff3b5000             arm,pl061 arm,primecell          T    ;P                       g            R        b           n   5                                             2      	   apb_pclk            zNC NC NC NC           gpio@e8a1f000             arm,pl061 arm,primecell          T                           h            R        b           n   6                                              3      	   apb_pclk          @  z[SD_CLK] [SD_CMD] [SD_DATA0] [SD_DATA1] [SD_DATA2] [SD_DATA3]         gpio@e8a20000             arm,pl061 arm,primecell          T                            i            R        b                               n   7                          4      	   apb_pclk          ^  z[WL_SDIO_CLK] [WL_SDIO_CMD] [WL_SDIO_DATA0] [WL_SDIO_DATA1] [WL_SDIO_DATA2] [WL_SDIO_DATA3]           gpio@fff0b000             arm,pl061 arm,primecell          T                           j            R        b           n   8                                          9          	   apb_pclk          d  z[GPIO_176_PMU_PWR_HOLD] NA [SYSCLK_EN] GPIO_179_WL_WAKEUP_AP GPIO_180_HDMI_INT NA GPIO-F [I2C0_SCL]             J      gpio@fff0c000             arm,pl061 arm,primecell          T                           k            R        b           n   8                                          9         	   apb_pclk          ^  z[I2C0_SDA] [I2C1_SCL] [I2C1_SDA] [I2C1_SCL] [I2C1_SDA] GPIO_189_USER_LED3 GPIO_190_USER_LED4                w      gpio@fff0d000             arm,pl061 arm,primecell          T                           l            R        b           n   8                                          9         	   apb_pclk          t  z[PCM_DI] [PCM_DO] [PCM_CLK] [PCM_FS] [GPIO_196_I2S2_DI] [GPIO_197_I2S2_DO] [GPIO_198_I2S2_XCLK] [GPIO_199_I2S2_XFS]       gpio@fff0e000             arm,pl061 arm,primecell          T                           m            R        b            n   8             8                                         9         	   apb_pclk          z  zNC NC GPIO_202_VBUS_TYPEC GPIO_203_SD_DET GPIO_204_PMU12_IRQ_N GPIO_205_WIFI_ACTIVE GPIO_206_USBSW_SEL GPIO_207_BT_ACTIVE               @      gpio@fff0f000             arm,pl061 arm,primecell          T                           n            R        b           n   8                                          9         	   apb_pclk          L  zGPIO-A GPIO-B GPIO-C GPIO-D GPIO-E [PCIE_CLKREQ_N] [PCIE_WAKE_N] [SPI0_CLK]       gpio@fff10000             arm,pl061 arm,primecell          T                            o            R        b           n   8       $                                   9         	   apb_pclk          B  z[SPI0_DIN] [SPI0_DOUT] [SPI0_CS] GPIO_219_CC_INT NC NC [PMU_INT]                      gpio@fff1d000             arm,pl061 arm,primecell          T                                       R        b                                   9         	   apb_pclk            z              spi@ffd68000              arm,pl022 arm,primecell          T    ր                             +                   t                                 sspclk apb_pclk         Cdefault         Q   :   ;                                     [okay            bLS-SPI0       spi@ff3b3000              arm,pl022 arm,primecell          T    ;0                             +                  8                  5      5         sspclk apb_pclk         Cdefault         Q   <   =                      >               [okay            bHS-SPI1       pcie@f4000000             hisilicon,kirin960-pcie       @   T                  ?                                            dbi apb phy config                                      +            Hpci                                                                                 Bmsi                                                                                                                                                 (               R      S      Q      P      :   pcie_phy_ref pcie_aux pcie_apb_phy pcie_apb_sys pcie_aclk              ?             ufs@ff3b0000          #    hisilicon,hi3660-ufs jedec,ufs-1.1            T    ;             ;                                                    f      e         ref_clk phy_clk                                 <                 rst       dwmmc1@ff37f000           hisilicon,hi3660-dw-mshc             T    7                             +                                     K               ciu biu         , 0         <                 reset              9                   [okay            -            7         H         U         b         o         }           @              Cdefault         Q   A   B   C           D           E      dwmmc2@ff3ff000           hisilicon,hi3660-dw-mshc             T    ?                             +                                     L               ciu biu         <                 reset                      [okay            -                                      Cdefault         Q   F   G   H           I   wlcore@2          
    ti,wl1837            T               J                       watchdog@e8a06000             arm,sp805 arm,primecell          T    `                       ,                                 wdog_clk apb_pclk         watchdog@e8a07000             arm,sp805 arm,primecell          T    p                       -                                 wdog_clk apb_pclk         tsensor@fff30000              hisilicon,hi3660-tsensor             T                                                      K      thermal-zones      cls0-thermal                         d                  !   K      trips      trip-point0         1          =           Opassive       trip-point1         1 $        =           Opassive             L         cooling-maps       map0            H   L        M         0  Z                  map1            H   L        M         0  Z            	               usb3_otg_bc@ff200000          /    hisilicon,hi3660-usb3-otg-bc syscon simple-mfd           T                 usb-phy           hisilicon,hi3660-usb-phy            i            t              M        $f            N         usb@ff100000          
    snps,dwc3            T                                  I         ref bus_early                 I        C@      0  <                                                                           N      	  usb3-phy            otg         super-speed         
utmi                      4         K         d         }                                              host       port                         +       endpoint@0           T               O                  endpoint@1           T              P                        etm@ecc40000          "    arm,coresight-etm4x arm,primecell            T                                  	   apb_pclk             D      out-ports      port       endpoint               Q            V               etm@ecd40000          "    arm,coresight-etm4x arm,primecell            T                                  	   apb_pclk             D      out-ports      port       endpoint               R            W               etm@ece40000          "    arm,coresight-etm4x arm,primecell            T                                  	   apb_pclk             D      out-ports      port       endpoint               S            X               etm@ecf40000          "    arm,coresight-etm4x arm,primecell            T                                  	   apb_pclk             D      out-ports      port       endpoint               T            Y               funnel@ec801000       +    arm,coresight-dynamic-funnel arm,primecell           T                                 	   apb_pclk       out-ports      port       endpoint               U            Z            in-ports                         +       port@0           T       endpoint               V            Q         port@1           T      endpoint               W            R         port@2           T      endpoint               X            S         port@3           T      endpoint               Y            T               etf@ec802000               arm,coresight-tmc arm,primecell          T                                  	   apb_pclk       in-ports       port       endpoint               Z            U            out-ports      port       endpoint               [            h               etm@ed440000          "    arm,coresight-etm4x arm,primecell            T    D                              	   apb_pclk             D      out-ports      port       endpoint               \            a               etm@ed540000          "    arm,coresight-etm4x arm,primecell            T    T                              	   apb_pclk             D      out-ports      port       endpoint               ]            b               etm@ed640000          "    arm,coresight-etm4x arm,primecell            T    d                              	   apb_pclk             D      out-ports      port       endpoint               ^            c               etm@ed740000          "    arm,coresight-etm4x arm,primecell            T    t                              	   apb_pclk             D   	   out-ports      port       endpoint               _            d               funnel@ed001000       +    arm,coresight-dynamic-funnel arm,primecell           T                                  	   apb_pclk       out-ports      port       endpoint               `            e            in-ports                         +       port@0           T       endpoint               a            \         port@1           T      endpoint               b            ]         port@2           T      endpoint               c            ^         port@3           T      endpoint               d            _               etf@ed002000               arm,coresight-tmc arm,primecell          T                                   	   apb_pclk       in-ports       port       endpoint               e            `            out-ports      port       endpoint               f            i               funnel            arm,coresight-static-funnel                      	   apb_pclk       out-ports      port       endpoint               g            k            in-ports                         +       port@0           T       endpoint               h            [         port@1           T      endpoint               i            f               funnel@ec031000       +    arm,coresight-dynamic-funnel arm,primecell           T                                 	   apb_pclk       out-ports      port       endpoint               j            l            in-ports                         +       port@0           T       endpoint               k            g               etf@ec036000               arm,coresight-tmc arm,primecell          T    `                             	   apb_pclk       in-ports       port       endpoint               l            j            out-ports      port       endpoint               m            n               replicator             arm,coresight-static-replicator                      	   apb_pclk       in-ports       port       endpoint               n            m            out-ports                        +       port@0           T       endpoint               o            q         port@1           T      endpoint               p            r               etr@ec033000               arm,coresight-tmc arm,primecell          T    0                             	   apb_pclk       in-ports       port       endpoint               q            o               tpiu@ec032000         !    arm,coresight-tpiu arm,primecell             T                                  	   apb_pclk       in-ports       port       endpoint               r            p               gpio-range                         s      pinmux@e896c000           pinctrl-single           T                   #           2           D            b               s              s      t                4   pmu-pins                                           csi0-pwd-n-pins            D          csi1-pwd-n-pins            L          isp0-pins              X      d      h         isp1-pins              \      l      p         pwr-key-pins                               t      i2c3-pins              ,      0                      i2c4-pins                             pcie-perstn-pins              \         usbhub5734-pins                            uart0-pins                                  $      uart1-pins                                               '      uart2-pins                                               )      uart3-pins                                               +      uart4-pins                                               -      uart5-pins                                               0      uart6-pins                                               2      cam0-rst-pins                        cam1-rst-pins             $             pinmux@ff37e000           pinctrl-single           T    7                2           #           D            b              s                       6   sd-pins       0                                                   A         pinmux@ff3b6000           pinctrl-single           T    ;`        0        #           2           D            b              s                       5   ufs-pins                               spi3-pins                                                <         pinmux@ff3fd000           pinctrl-single           T    ?                #           2           D            b              s                       7   sdio-pins         0                                                   F         pinmux@fff11000           pinctrl-single           T                    #           2           D            b              s       *                8   i2s2-pins               D      H      L      P         slimbus-pins               ,      0         i2c0-pins                                         i2c1-pins                                          i2c7-pins              $      (               "      pcie-pins                             spi2-pins                                                :      i2s0-pins               4      8      <      @            pinmux@e896c800           pinconf-single           T                    #           D       pmu-cfg-pins                                                                                                         i2c3-cfg-pins              8       <                                                                           !      csi0-pwd-n-cfg-pins            P                                                                    csi1-pwd-n-cfg-pins            X                                                                    isp0-cfg-pins              d       p       t                                                                    isp1-cfg-pins              h       x       |                                                                    pwr-key-cfg-pins                                                                                          u      uart1-cfg-pins                                                                                                              (      uart2-cfg-pins                                                                                                              *      uart5-cfg-pins                                                                                                              1      cam0-rst-cfg-pins                                                                                  uart0-cfg-pins                                                                                               %      uart6-cfg-pins                                                                                                              3      uart3-cfg-pins                                                                                                              ,      uart4-cfg-pins                                                                                                             .      cam1-rst-cfg-pins             0                                                                       pinmux@ff3b6800           pinconf-single           T    ;h                #           D       ufs-cfg-pins                                                                                  0         spi3-cfg-pins                                                                                                               =         pinmux@ff3fd800           pinconf-single           T    ?                #           D       sdio-clk-cfg-pins                                                                                         G      sdio-cfg-pins         (                                                                                                          H         pinmux@ff37e800           pinconf-single           T    7                #           D       sd-clk-cfg-pins                                                                                       B      sd-cfg-pins       (                                                                                                          C         pinmux@fff11800           pinconf-single           T                    #           D       i2c0-cfg-pins                                                                                                      i2c1-cfg-pins              $       (                                                                                i2c7-cfg-pins              ,       0                                                                          #      slimbus-cfg-pins               4       8                                                                    i2s0-cfg-pins               @       D       H       L                                                                    i2s2-cfg-pins               P       T       X       \                                                                    pcie-cfg-pins                                                                                         spi2-cfg-pins                                                                                                              ;      usb-cfg-pins                                                                                                     aliases         /soc/dwmmc1@ff37f000            	/soc/dwmmc2@ff3ff000            /soc/serial@fdf02000            /soc/serial@fdf00000            /soc/serial@fdf03000            '/soc/serial@ffd74000            //soc/serial@fdf01000            7/soc/serial@fdf05000            ?/soc/serial@fff32000          chosen          Gserial6:115200n8          memory@0             Hmemory           T                      reserved-memory                      +               ramoops@32000000              ramoops          T    2                  S           _           l            reboot-mode-syscon@32100000           syscon simple-mfd            T    2            reboot-mode           syscon-reboot-mode          x            wfU        wfU         wfU         keys          
    gpio-keys           Cdefault         Q   t   u   key-power                       v              bGPIO Power             t         leds          
    gpio-leds      led-user-1          bgreen:user1            >             
  heartbeat         led-user-2          bgreen:user2            >               none          led-user-3          bgreen:user3            w               mmc0          led-user-4          bgreen:user4            w                        none          led-wlan            byellow:wlan            @               phy0tx          off       led-bt          bblue:bt            @               hci0-power          off          pmic@fff34000             hisilicon,hi6421v530-pmic            T    @                               regulators     LDO3            VOUT3_1V85          	 w@        	 !        	5   x      LDO9            VOUT9_1V8_2V95          	         	 2Z        	5               E      LDO11           VOUT11_1V8_2V95         	         	 2Z        	5         LDO15           VOUT15_3V0          	         	 -         	Q         	c        	5   x      LDO16           VOUT16_2V95         	         	 -        	5  h            D            wlan-en-1-8v              regulator-fixed         wlan-en-regulator           	 w@        	 w@        	w   x               	| p         	            I      firmware       optee             linaro,optee-tz          =smc             	compatible interrupt-parent #address-cells #size-cells model method cpu device_type reg enable-method next-level-cache cpu-idle-states capacity-dmips-mhz clocks operating-points-v2 #cooling-cells dynamic-power-coefficient phandle entry-method local-timer-stop arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us cache-level cache-unified opp-shared opp-hz opp-microvolt clock-latency-ns #interrupt-cells interrupt-controller interrupts interrupt-affinity ranges #clock-cells #reset-cells hisi,rst-syscon #mbox-cells mboxes clock-names clock-frequency resets pinctrl-names pinctrl-0 status label data-role power-role try-power-role source-pdos sink-pdos op-sink-microwatt remote-endpoint adi,dsi-lanes dma-names dmas enable-gpios max-speed #dma-cells dma-channels dma-requests dma-channel-mask dma-no-cci dma-type interrupt-names gpio-controller #gpio-cells gpio-ranges gpio-line-names num-cs cs-gpios reg-names bus-range num-lanes interrupt-map-mask interrupt-map reset-gpios freq-table-hz reset-names hisilicon,peripheral-syscon card-detect-delay bus-width cap-sd-highspeed sd-uhs-sdr12 sd-uhs-sdr25 sd-uhs-sdr50 sd-uhs-sdr104 disable-wp cd-gpios vmmc-supply vqmmc-supply non-removable broken-cd cap-power-off-card #thermal-sensor-cells polling-delay polling-delay-passive sustainable-power thermal-sensors temperature hysteresis trip contribution cooling-device #phy-cells hisilicon,pericrg-syscon hisilicon,pctrl-syscon hisilicon,eye-diagram-param assigned-clocks assigned-clock-rates phys phy-names dr_mode maximum-speed phy_type snps,dis-del-phy-power-chg-quirk snps,lfps_filter_quirk snps,dis_u2_susphy_quirk snps,dis_u3_susphy_quirk snps,tx_de_emphasis_quirk snps,tx_de_emphasis snps,dis_enblslpm_quirk snps,gctl-reset-quirk usb-role-switch role-switch-default-mode #pinctrl-single,gpio-range-cells #pinctrl-cells #gpio-range-cells pinctrl-single,register-width pinctrl-single,function-mask pinctrl-single,gpio-range pinctrl-single,pins pinctrl-single,bias-pulldown pinctrl-single,bias-pullup pinctrl-single,drive-strength mshc1 mshc2 serial0 serial1 serial2 serial3 serial4 serial5 serial6 stdout-path record-size console-size ftrace-size offset mode-normal mode-bootloader mode-recovery wakeup-source linux,code linux,default-trigger panic-indicator default-state regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-boot-on regulator-always-on gpio startup-delay-us enable-active-high 