  &   8  \   (              $                                 hisilicon,hip05-d02                                  +         &   7Hisilicon Hip05 D02 Development Board      psci              arm,psci-0.2             =smc       cpus                         +       cpu-map    cluster0       core0            D         core1            D         core2            D         core3            D            cluster1       core0            D         core1            D         core2            D         core3            D   	         cluster2       core0            D   
      core1            D         core2            D         core3            D            cluster3       core0            D         core1            D         core2            D         core3            D               cpu@20000            Hcpu           arm,cortex-a57           T            Xpsci             f            w         cpu@20001            Hcpu           arm,cortex-a57           T           Xpsci             f            w         cpu@20002            Hcpu           arm,cortex-a57           T           Xpsci             f            w         cpu@20003            Hcpu           arm,cortex-a57           T           Xpsci             f            w         cpu@20100            Hcpu           arm,cortex-a57           T           Xpsci             f            w         cpu@20101            Hcpu           arm,cortex-a57           T          Xpsci             f            w         cpu@20102            Hcpu           arm,cortex-a57           T          Xpsci             f            w         cpu@20103            Hcpu           arm,cortex-a57           T          Xpsci             f            w   	      cpu@20200            Hcpu           arm,cortex-a57           T           Xpsci             f            w   
      cpu@20201            Hcpu           arm,cortex-a57           T          Xpsci             f            w         cpu@20202            Hcpu           arm,cortex-a57           T          Xpsci             f            w         cpu@20203            Hcpu           arm,cortex-a57           T          Xpsci             f            w         cpu@20300            Hcpu           arm,cortex-a57           T           Xpsci             f            w         cpu@20301            Hcpu           arm,cortex-a57           T          Xpsci             f            w         cpu@20302            Hcpu           arm,cortex-a57           T          Xpsci             f            w         cpu@20303            Hcpu           arm,cortex-a57           T          Xpsci             f            w         l2-cache0             cache                                  w         l2-cache1             cache                                  w         l2-cache2             cache                                  w         l2-cache3             cache                                  w            interrupt-controller@8d000000             arm,gic-v3                                   +                                                         P   T                         0                                                         	            w      msi-controller@8c000000           arm,gic-v3-its                                T                    msi-controller@a3000000           arm,gic-v3-its                                T                    msi-controller@b7000000           arm,gic-v3-its                                T                    msi-controller@c6000000           arm,gic-v3-its                                T                       refclk200mhz              fixed-clock                     $          w         timer             arm,armv8-timer       0                                    
         pmu           arm,cortex-a57-pmu                          soc           simple-bus                       +                serial@80300000           snps,dw-apb-uart             T    0                        =           4              ;baudclk apb_pclk            G           Q           ^okay          serial@80310000           snps,dw-apb-uart             T    1                        >           4              ;baudclk apb_pclk            G           Q         	  ^disabled          local-bus@80380000        #    hisilicon,hisi-localbus simple-bus           T    8                 ^okay                         +         (                                         nor-flash@0                      +             numonyx,js28f00a cfi-flash           T                   e      partition@0         pBIOS             T     0        partition@300000            pLinux            T 0           partition@1000000           pRootfs           T               cpld@100000000            hisilicon,hip05-cpld             T                   gpio@802e0000                        +              snps,dw-apb-gpio             T    .                 ^okay       gpio-controller@0             snps,dw-apb-gpio-port            v                                T                                         8            w            gpio@802f0000                        +              snps,dw-apb-gpio             T    /               	  ^disabled       gpio-controller@0             snps,dw-apb-gpio-port            v                                T                                         9               memory@0             Hmemory           T                     aliases         /soc/serial@80300000          chosen          serial0:115200n8          gpio-keys         
    gpio-keys      pwr-button          pPower Button                                t                        	compatible interrupt-parent #address-cells #size-cells model method cpu device_type reg enable-method next-level-cache phandle cache-level cache-unified #interrupt-cells ranges interrupt-controller #redistributor-regions redistributor-stride interrupts msi-controller #msi-cells #clock-cells clock-frequency clocks clock-names reg-shift reg-io-width status bank-width label gpio-controller #gpio-cells ngpios serial0 stdout-path linux,code debounce-interval 