Ðþí  ¦   8  ˆ   (              P                                 Marvell 8080 board        Z   marvell,armada-8080-db marvell,armada-8080 marvell,armada-ap810-octa marvell,armada-ap810                               aliases       /   ,/ap810-ap0/config-space@e8000000/serial@512000        /   4/ap810-ap0/config-space@e8000000/serial@512100        psci             arm,psci-0.2             <smc       ap810-ap0                                     simple-bus           C             T   config-space@e8000000                                     simple-bus           T        è               C      interrupt-controller@3000000             arm,gic-v3           [                                      l               	             T      (   Œ                                              msi-controller@3040000           arm,gic-v3-its            ˜         §            Œ                          timer            arm,armv8-timer       0                                    
         xor@400000        %   marvell,armada-7k-xor marvell,xor-v2             Œ @      A              ²                 ½      xor@420000        %   marvell,armada-7k-xor marvell,xor-v2             Œ B      C              ²      ¡          ½      xor@440000        %   marvell,armada-7k-xor marvell,xor-v2             Œ D      E              ²      ¢          ½      xor@460000        %   marvell,armada-7k-xor marvell,xor-v2             Œ F      G              ²      £          ½      serial@512000            snps,dw-apb-uart             Œ Q              Ê                               Ô            áokay             è Ü       serial@512100            snps,dw-apb-uart             Œ Q!             Ê                               Ô         	   ádisabled                cpus                                       marvell,armada-ap810-octa      cpu@0            øcpu          arm,cortex-a72           Œ            psci          cpu@1            øcpu          arm,cortex-a72           Œ           psci          cpu@100          øcpu          arm,cortex-a72           Œ           psci          cpu@101          øcpu          arm,cortex-a72           Œ          psci          cpu@200          øcpu          arm,cortex-a72           Œ           psci          cpu@201          øcpu          arm,cortex-a72           Œ          psci          cpu@300          øcpu          arm,cortex-a72           Œ           psci          cpu@301          øcpu          arm,cortex-a72           Œ          psci             chosen          serial0:115200n8          memory@0             ømemory           Œ            €            	model compatible #address-cells #size-cells serial0 serial1 method interrupt-parent ranges #interrupt-cells interrupt-controller interrupts reg phandle msi-controller #msi-cells msi-parent dma-coherent reg-shift reg-io-width status clock-frequency device_type enable-method stdout-path 