  \   8  U   (            +  U                             $    mediatek,mt2712-evb mediatek,mt2712                                  +         !   7MediaTek MT2712 evaluation board          	   =embedded       opp-table-0           operating-points-v2           J         U      opp00            ]    #         d B@      opp01            ]    )׫         d B@      opp02            ]    /D8@         d B@         opp-table-1           operating-points-v2           J         U      opp00            ]    #         d B@      opp01            ]    )׫         d B@      opp02            ]    /D8@         d B@      opp03            ]    5w"@         d B@      opp04            ]    ;@         d B@         cpus                         +       cpu-map    cluster0       core0            r         core1            r            cluster1       core0            r               cpu@0            vcpu           arm,cortex-a35                                     %         cpu intermediate                                        	   
         U         cpu@1            vcpu           arm,cortex-a35                       psci                          %         cpu intermediate                                        	   
         U         cpu@200          vcpu           arm,cortex-a72                       psci                         '         cpu intermediate                                        	   
         U         idle-states          psci       cpu-sleep-0           arm,idle-state                        d           P                  '            U   	      cluster-sleep-0           arm,idle-state                       ^           P                  '           U   
            psci              arm,psci-0.2             smc       dummy26m              fixed-clock         >        N             U         dummyclk              fixed-clock         >        N             U         oscillator-26m            fixed-clock         N            >        [clk26m           U   *      oscillator-32k            fixed-clock         N            >           [clk32k        oscillator-50m            fixed-clock         N            >        [clkfpc        oscillator-aud0           fixed-clock         N            > c.        [clkaud_ext_i_0        oscillator-aud1           fixed-clock         N            >          [clkaud_ext_i_1        oscillator-aud2           fixed-clock         N            >
@         [clkaud_ext_i_2        oscillator-i2s0           fixed-clock         N            >À        [clki2si0_mck_i        oscillator-i2s1           fixed-clock         N            >À        [clki2si1_mck_i        oscillator-i2s2           fixed-clock         N            >À        [clki2si2_mck_i        oscillator-mclk           fixed-clock         N            >À        [clktdmin_mclk_i       timer             arm,armv8-timer                   0  n                              
        syscon@10000000            mediatek,mt2712-topckgen syscon                                N            U         clock-controller@10001000              mediatek,mt2712-infracfg syscon                               N           y            U         syscon@10003000           mediatek,mt2712-pericfg syscon                0                N            U         syscon@10005000       %    mediatek,mt2712-pctl-a-syscfg syscon                  P                 U         pinctrl@1000b000              mediatek,mt2712-pinctrl                                                                                  n                   U   "   eth-default-pins             U   #   tx_pins           G  H  I  J  K  L                 rx_pins           N  O  P  Q  R  T               mdio_pins             U  V                             eth-sleep-pins           U   $   tx_pins           G   H   I   J   K   L       rx_pins           N   O   P   Q   R   T                 mdio_pins             U   V                             usb0-iddig-pins          U   )   pins_iddig                              usb1-iddig-pins          U   1   pins_iddig                                 power-controller@10006000             mediatek,mt2712-scpsys syscon           (                 `              0         e      i      h                  g         mm mfg venc jpgdec audio vdec           <            U         serial@1000f000       *    mediatek,mt2712-uart mediatek,mt6577-uart                                 n                               	   baud bus            E      
              Jtx rx         	  Tdisabled          rtc@10011000              mediatek,mt2712-rtc                              n                spi@10013000              mediatek,mt2712-spi-slave                0                n                                 spi         [              k            	  Tdisabled          iommu@10205000            mediatek,mt2712-m4u               P                n                                  bclk                                                       syscon@10209000       "    mediatek,mt2712-apmixedsys syscon                                 N         iommu@1020a000            mediatek,mt2712-m4u                               n                                  bclk                                                 syscon@10220000           mediatek,mt2712-mcucfg syscon                "                 N            U         interrupt-controller@10220a80         .    mediatek,mt2712-sysirq mediatek,mt6577-sysirq                                                "
       @         U         interrupt-controller@10510000             arm,gic-400                                       @       Q             R             T             V                 n      	           U         dma-controller@11000400       2    mediatek,mt2712-uart-dma mediatek,mt6577-uart-dma                                                                                                                                              	             	               n       g          h          i          j          k          l          m          n          o          p          q          r                                      apdma                       U         adc@11001000              mediatek,mt2712-auxadc                                                main                       Tokay          serial@11002000       *    mediatek,mt2712-uart mediatek,mt6577-uart                                  n       [                        	   baud bus            E                     Jtx rx           Tokay          serial@11003000       *    mediatek,mt2712-uart mediatek,mt6577-uart                 0                n       \                        	   baud bus            E                    Jtx rx         	  Tdisabled          serial@11004000       *    mediatek,mt2712-uart mediatek,mt6577-uart                 @                n       ]                        	   baud bus            E                    Jtx rx         	  Tdisabled          serial@11005000       *    mediatek,mt2712-uart mediatek,mt6577-uart                 P                n       ^                        	   baud bus            E                    Jtx rx         	  Tdisabled          pwm@11006000              mediatek,mt2712-pwm               `                           n       M         P         f      
                                                	      1   top main pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 pwm8          	  Tdisabled          i2c@11007000              mediatek,mt2712-i2c                p                            n       T                                         	   main dma                         +          	  Tdisabled          i2c@11008000              mediatek,mt2712-i2c                                             n       U                                         	   main dma                         +          	  Tdisabled          i2c@11009000              mediatek,mt2712-i2c                                            n       V                                         	   main dma                         +          	  Tdisabled          spi@1100a000              mediatek,mt2712-spi                      +                                  n       v                        l               parent-clk sel-clk spi-clk        	  Tdisabled          nand-controller@1100e000              mediatek,mt2712-nfc                               n       `                                  nfi_clk pad_clk                                 +          	  Tdisabled          ecc@1100f000              mediatek,mt2712-ecc                               n       _                           nfiecc_clk        	  Tdisabled             U         i2c@11010000              mediatek,mt2712-i2c                                             n       W                                         	   main dma                         +          	  Tdisabled          i2c@11011000              mediatek,mt2712-i2c                                           n       X                                         	   main dma                         +          	  Tdisabled          i2c@11013000              mediatek,mt2712-i2c               0                             n       Z                                         	   main dma                         +          	  Tdisabled          spi@11015000              mediatek,mt2712-spi                      +                 P                n                              l               parent-clk sel-clk spi-clk        	  Tdisabled          spi@11016000              mediatek,mt2712-spi                      +                 `                n                              l               parent-clk sel-clk spi-clk        	  Tdisabled          spi@10012000              mediatek,mt2712-spi                      +                                  n                              l               parent-clk sel-clk spi-clk        	  Tdisabled          spi@11018000              mediatek,mt2712-spi                      +                                 n                              l               parent-clk sel-clk spi-clk        	  Tdisabled          serial@11019000       *    mediatek,mt2712-uart mediatek,mt6577-uart                                n       ~                        	   baud bus            E            	        Jtx rx         	  Tdisabled          stmmac-axi-config                      
                                             U         rx-queues-config            $            :         U      queue0           K        ^            v             tx-queues-config                                 U       queue0                      K        v          queue1                      K        v         queue2                      K        v            ethernet@1101c000         &    mediatek,mt2712-gmac snps,dwmac-4.20a                                n                  macirq           U{}        '   axi apb mac_main ptp_ref rmii_internal        (         "      %                          [                          k      =            >                                                                   )           4           ?            Tokay            Lrgmii-rxid          U   !        `          u   "   W                 '  '        default sleep              #           $   mdio              snps,dwmac-mdio                      +       ethernet-phy@5            ethernet-phy-id0243.0d90                         U   !            mmc@11230000              mediatek,mt2712-mmc              #                 n       O                         *      &      ,         source hclk source_cg bus_clk         	  Tdisabled          mmc@11240000              mediatek,mt2712-mmc              $                 n       P                        c      '         source hclk source_cg         	  Tdisabled          mmc@11250000              mediatek,mt2712-mmc              %                 n       Q                        c      (         source hclk source_cg         	  Tdisabled          usb@11271000          #    mediatek,mt2712-mtu3 mediatek,mtu3                '       0     (              	  mac ippc            n       z              %      &                                n         sys_ck                                       +                    Tokay               '           (        otg                             default            )   usb@11270000          '    mediatek,mt2712-xhci mediatek,mtk-xhci               '                 mac         n       {                                n   *         sys_ck ref_ck           Tokay               +         t-phy@11290000        .    mediatek,mt2712-tphy mediatek,generic-tphy-v2                        +                   )             Tokay       usb-phy@0                               *         ref         '           Tokay             U   %      usb-phy@8000                               *         ref         '           Tokay             U   &      usb-phy@8700                  	             *         ref         '           Tokay             U   3         usb@112c1000          #    mediatek,mt2712-mtu3 mediatek,mtu3                ,       0     -              	  mac ippc            n                     ,      -      .                                n         sys_ck                                       +                    Tokay               /           0        otg          2                 default            1   usb@112c0000          '    mediatek,mt2712-xhci mediatek,mtk-xhci               ,                 mac         n                                       n   *         sys_ck ref_ck           Tokay             t-phy@112e0000        .    mediatek,mt2712-tphy mediatek,generic-tphy-v2                        +                   .             Tokay       usb-phy@0                               *         ref         '           Tokay             U   ,      usb-phy@8000                               *         ref         '           Tokay             U   -      usb-phy@8700                  	             *         ref         '           Tokay             U   .         pcie@112ff000             mediatek,mt2712-pcie             vpci              /                port1           D                        +           n       u         	  pcie_irq                         $         sys_ck1 ahb_ck1            .         
  Upcie-phy1           _                      @      @       0        	  Tdisabled                       i                     `  |                  2                      2                     2                     2      interrupt-controller                                              U   2         pcie@11700000             mediatek,mt2712-pcie             vpci              p                 port0           D                         +           n       s         	  pcie_irq                         #         sys_ck0 ahb_ck0            3         
  Upcie-phy0           _                                               	  Tdisabled                       i                     `  |                  4                      4                     4                     4      interrupt-controller                                              U   4         syscon@13000000           mediatek,mt2712-mfgcfg syscon                                  N         syscon@14000000           mediatek,mt2712-mmsys syscon                                   N            U   6      larb@14021000             mediatek,mt2712-smi-larb                                    5                                       6      6            apb smi          U         smi@14022000              mediatek,mt2712-smi-common                                                   6       6             apb smi          U   5      larb@14027000             mediatek,mt2712-smi-larb                 p                   7                                      6   ,   6   ,         apb smi          U         larb@14030000             mediatek,mt2712-smi-larb                                     7                                      6   .   6   .         apb smi          U         smi@14031000              mediatek,mt2712-smi-common                                                  6   -   6   -         apb smi          U   7      larb@14032000             mediatek,mt2712-smi-larb                                     7                                      6   8   6   8         apb smi          U         syscon@15000000           mediatek,mt2712-imgsys syscon                                  N            U   8      larb@15001000             mediatek,mt2712-smi-larb                                     5                                     8       8             apb smi          U         syscon@15010000           mediatek,mt2712-bdpsys syscon                                 N         syscon@16000000           mediatek,mt2712-vdecsys syscon                                 N            U   9      larb@16010000             mediatek,mt2712-smi-larb                                     5                                     9       9            apb smi          U         syscon@18000000           mediatek,mt2712-vencsys syscon                                 N            U   :      larb@18001000             mediatek,mt2712-smi-larb                                     5                                     :       :            apb smi          U         larb@18002000             mediatek,mt2712-smi-larb                                      5                                     :       :            apb smi          U         syscon@19000000       !    mediatek,mt2712-jpgdecsys syscon                                   N         aliases         /serial@11002000          memory@40000000          vmemory               @                chosen          serial0:921600n8          regulator-vproc-buck0             regulator-fixed         vproc_buck0          B@         B@         U         regulator-vproc-buck1             regulator-fixed         vproc_buck1          B@         B@         U         extcon_iddig              linux,extcon-usb-gpio              "                U   (      extcon_iddig1             linux,extcon-usb-gpio              "                U   0      regulator-usb-p0-vbus             regulator-fixed         p0_vbus          LK@         LK@           "                         U   '      regulator-usb-p1-vbus             regulator-fixed         p1_vbus          LK@         LK@           "                         U   /      regulator-usb-p2-vbus             regulator-fixed         p2_vbus          LK@         LK@           "                         U   +      regulator-usb-p3-vbus             regulator-fixed         p3_vbus          LK@         LK@           "                                  	compatible interrupt-parent #address-cells #size-cells model chassis-type opp-shared phandle opp-hz opp-microvolt cpu device_type reg clocks clock-names proc-supply operating-points-v2 cpu-idle-states enable-method entry-method local-timer-stop entry-latency-us exit-latency-us min-residency-us arm,psci-suspend-param clock-frequency #clock-cells clock-output-names interrupts #reset-cells mediatek,pctl-regmap gpio-controller #gpio-cells interrupt-controller #interrupt-cells pinmux drive-strength input-enable input-disable bias-disable bias-pull-up #power-domain-cells infracfg dmas dma-names status assigned-clocks assigned-clock-parents mediatek,infracfg mediatek,larbs #iommu-cells dma-requests #dma-cells #io-channel-cells #pwm-cells clock-div ecc-engine snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,priority snps,tx-queues-to-use snps,tx-sched-wrr snps,weight interrupt-names mac-address power-domains mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle mediatek,tx-delay-ps snps,reset-gpio snps,reset-delays-us pinctrl-names pinctrl-0 pinctrl-1 reg-names phys mediatek,syscon-wakeup ranges vbus-supply extcon dr_mode wakeup-source mediatek,u3p-dis-msk #phy-cells enable-manual-drd linux,pci-domain phy-names bus-range interrupt-map-mask interrupt-map mediatek,smi mediatek,larb-id serial0 stdout-path regulator-name regulator-min-microvolt regulator-max-microvolt id-gpios enable-active-high regulator-always-on 