     8  L   (            H                               $    mediatek,mt6779-evb mediatek,mt6779                                  +            7MediaTek MT6779 EVB       	   =embedded       psci              arm,psci-0.2             Jsmc       cpus                         +       cpu@0            Qcpu           arm,cortex-a55           ]psci             k             o         cpu@1            Qcpu           arm,cortex-a55           ]psci             k            o         cpu@2            Qcpu           arm,cortex-a55           ]psci             k            o         cpu@3            Qcpu           arm,cortex-a55           ]psci             k            o         cpu@4            Qcpu           arm,cortex-a55           ]psci             k            o         cpu@5            Qcpu           arm,cortex-a55           ]psci             k            o         cpu@6            Qcpu           arm,cortex-a75           ]psci             k            o   	      cpu@7            Qcpu           arm,cortex-a75           ]psci             k            o   
         pmu           arm,armv8-pmuv3                      w                   oscillator-26m            fixed-clock                                clk26m           o         oscillator-32k            fixed-clock                                   clk32k        timer             arm,armv8-timer                   @   w                                             
             soc                      +             simple-bus               interrupt-controller@c000000              arm,gic-v3                                              k                                     w      	                o      ppi-partitions     interrupt-partition-0                                    interrupt-partition-1               	   
            intpol-controller@c53a650         .    mediatek,mt6779-sysirq mediatek,mt6577-sysirq                                              k    SP       P         o         clock-controller@10000000              mediatek,mt6779-topckgen syscon          k                                clock-controller@10001000         #    mediatek,mt6779-infracfg_ao syscon           k                                  o         pinctrl@10005000              mediatek,mt6779-pinctrl          k     P                                                                                                                      I   gpio iocfg_rm iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint                                                                              w                   o         clock-controller@1000c000             mediatek,mt6779-apmixed syscon           k                               pwrap@1000d000            mediatek,mt6779-pwrap            k                      pwrap            w                                 	  !spi wrap          devapc@10207000           mediatek,mt6779-devapc           k     p                 w                        -        !devapc-infra-clock        serial@11002000       *    mediatek,mt6779-uart mediatek,mt6577-uart            k                       w       s                          	  !baud bus            -okay          serial@11003000       *    mediatek,mt6779-uart mediatek,mt6577-uart            k     0                 w       t                          	  !baud bus          	  -disabled          serial@11004000       *    mediatek,mt6779-uart mediatek,mt6577-uart            k     @                 w       u                          	  !baud bus          	  -disabled          clock-controller@11210000             mediatek,mt6779-audio syscon             k    !                           clock-controller@13fbf000             mediatek,mt6779-mfgcfg syscon            k                              syscon@14000000           mediatek,mt6779-mmsys syscon             k                                clock-controller@15020000             mediatek,mt6779-imgsys syscon            k                               clock-controller@16000000             mediatek,mt6779-vdecsys syscon           k                                clock-controller@17000000             mediatek,mt6779-vencsys syscon           k                                clock-controller@1a000000             mediatek,mt6779-camsys syscon            k                                clock-controller@1b000000             mediatek,mt6779-ipesys syscon            k                                   aliases         4/soc/serial@11002000          memory@40000000          Qmemory           k    @               chosen          <serial0:921600n8             	compatible interrupt-parent #address-cells #size-cells model chassis-type method device_type enable-method reg phandle interrupts #clock-cells clock-frequency clock-output-names ranges #interrupt-cells interrupt-controller affinity reg-names gpio-controller #gpio-cells gpio-ranges clocks clock-names status serial0 stdout-path 