  p,   8  iP   (              i                                 sony,xperia-m5 mediatek,mt6795                                   +            7Sony Xperia M5           =handset    aliases          J/soc/ovl@1400c000            O/soc/ovl@1400d000            T/soc/rdma@1400e000           Z/soc/rdma@1400f000           `/soc/rdma@14010000           f/soc/wdma@14011000           l/soc/wdma@14012000           r/soc/color@14013000          y/soc/color@14014000          /soc/split@14018000          /soc/split@14019000          /soc/dpi@1401d000            /soc/dsi@1401b000            /soc/dsi@1401c000            /soc/mmc@11230000            /soc/mmc@11240000            /soc/mmc@11250000            /soc/serial@11002000             /soc/serial@11003000          psci              arm,psci-0.2             smc       cpus                         +       cpu@0            cpu           arm,cortex-a53           psci                                                          cpu@1            cpu           arm,cortex-a53           psci                                                  @        *           7           D   @        V                                cpu@2            cpu           arm,cortex-a53           psci                                                  @        *           7           D   @        V                                cpu@3            cpu           arm,cortex-a53           psci                                                  @        *           7           D   @        V                          	      cpu@100          cpu           arm,cortex-a53           psci                                                  @        *           7           D   @        V                          
      cpu@101          cpu           arm,cortex-a53           psci                                                 @        *           7           D   @        V                                cpu@102          cpu           arm,cortex-a53           psci                                                 @        *           7           D   @        V                                cpu@103          cpu           arm,cortex-a53           psci                                                 @        *           7           D   @        V                                cpu-map    cluster0       core0           c         core1           c         core2           c         core3           c   	         cluster1       core0           c   
      core1           c         core2           c         core3           c               l2-cache0             cache           g                         @        ,            s                 l2-cache1             cache           g                         @        ,            s                    oscillator-26m            fixed-clock                             clk26m                   oscillator-32k            fixed-clock                       }         clk32k                   dummy13m              fixed-clock          ]@                             pmu           arm,cortex-a53-pmu        0                   	          
                                 	      timer             arm,armv8-timer                   0                                
        soc                      +             simple-bus              syscon@10000000            mediatek,mt6795-topckgen syscon                                                    syscon@10001000            mediatek,mt6795-infracfg syscon                                                              syscon@10003000           mediatek,mt6795-pericfg syscon                0                                               syscon@10006000           syscon simple-mfd                 `                      power-controller          !    mediatek,mt6795-power-controller                         +                             power-domain@1                            R        mm                    power-domain@2                            R      U        mm venc                   power-domain@3                            R        mm                    power-domain@0                             R        mm                      
         power-domain@4                            R      e        mm mjc                    power-domain@5                                power-domain@6                                 mfg                      +                  power-domain@7                                   +                  power-domain@8                                  
                     pinctrl@10005000              mediatek,mt6795-pinctrl                P                           
  base eint                                        &        6           B                       N        c                 lcm-pins               6   pins-rst            t  j          emmc-sdr-pins              '   pins-cmd-dat          $  t                           {           e      pins-clk            t             f      pins-rst            t             f         emmc-uhs-pins              (   pins-cmd-dat          $  t                           {                      e      pins-clk            t                        f      pins-rst            t                        f      pins-ds         t                        f         nfc-pins               %   pins-irq            t                     {      pins-fw-ven         t  ^             touchscreen-pins               #   pins-irq            t                     {      pins-rst            t  f                   proximity-pins             &   pins-irq            t                     {         accelerometer-pins             !   pins-irq            t                     {         i2c0-pins                 pins-bus            t  -  .         {         i2c1-pins                  pins-bus            t  }  ~                  i2c2-pins              "   pins-bus            t  +  ,                  i2c3-pins              $   pins-bus            t                      i2c4-pins      pins-bus            t  d  e                  uart0-pins                pins-rx         t  q                  {      pins-tx         t  r                  uart2-pins                pins-rx         t                    {      pins-tx         t               watchdog@10007000             mediatek,mt6795-wdt               p                                                      timer@10008000        ,    mediatek,mt6795-timer mediatek,mt6577-timer                                                             pwrap@1000d000            mediatek,mt6795-pwrap                                 pwrap                                           pwrap                 c         	  spi wrap       pmic              mediatek,mt6331          N        c                        regulators            mediatek,mt6331-regulator      buck-vdvfs11            vdvfs11          
`                 *  0        ?            [                s      buck-vdvfs12            vdvfs12          
`                 *  0        ?            [                s      buck-vdvfs13            vdvfs13          
`                 *  0        ?            [                s      buck-vdvfs14            vdvfs14          
`                 *  0        ?            [                s      buck-vcore2         vcore2           
`                 *  0        ?            [                s      buck-vio18          vio18            w@         w@        *  0        ?            [                s           *      ldo-vtcxo1          vtcxo1           *         *        *             s               ldo-vtcxo2          vtcxo2           *         *        *             s               ldo-avdd32aud           avdd32_aud           *         0         *             s               ldo-vauxa32         vauxa32          *         0         *          ldo-vcama           vcama            `         *        *          ldo-vio28           vio28            *         *        *             s               ldo-vcamaf          vcam_af          O         2Z        *          ldo-vmc         vmc          w@         2Z        *               +      ldo-vmch            vmch             -         2Z        *               ,      ldo-vemc33          vemc33           2Z         2Z        *             s           )      ldo-vgp1            vgp1             O         2Z        *             s      ldo-vsim1           vsim1                     /M`        *             s      ldo-vsim2           vsim2                     /M`        *          ldo-vmipi           vmipi            O         2Z        *             s      ldo-vibr            vibr             O         2Z        *          ldo-vgp4            vgp4             j          !        *             s      ldo-vcamd           vcamd                     `        *             s      ldo-vusb10          vusb             B@                  *             s               ldo-vcamio          vcam_io          O         w@        *          ldo-vsram           vsram            s         s        *             s               ldo-vgp2            vgp2                      `        *             s               ldo-vgp3            vgp3             w@         w@        *             s           3      ldo-vrtc            vrtc             *         *        *             s      ldo-vdig18          vdig18           w@         w@        *             s         rtc           mediatek,mt6331-rtc       keys              mediatek,mt6331-keys       power              t               home               f         mt6332-led            mediatek,mt6332-led                      +       led@0                        backlight-pmic             >               intpol-controller@10200620        .    mediatek,mt6795-sysirq mediatek,mt6577-sysirq            N        c                                                       timer@10200670            mediatek,mt6795-systimer                  p                      @                      clk13m        iommu@10205000            mediatek,mt6795-m4u               P                              bclk                                                                               /      syscon@10209000       "    mediatek,mt6795-apmixedsys syscon                                                     clock-controller@10209f00             mediatek,mt6795-fhctl                                 okay                                                     mailbox@10212000          (    mediatek,mt6795-gce mediatek,mt8173-gce              !                                                 gce         
              -      dsi-phy@10215000              mediatek,mt8173-mipi-tx              !P                           mipi_tx0_pll                                  	  disabled               0      dsi-phy@10216000              mediatek,mt8173-mipi-tx              !`                           mipi_tx1_pll                                  	  disabled               9      interrupt-controller@10221000             arm,gic-400         c                        N      @       "            "              "@             "`                       	                   cci@10390000              arm,cci-400                      +                9                         9        slave-if@1000             arm,cci-400-ctrl-if       	  !ace-lite                         slave-if@4000             arm,cci-400-ctrl-if         !ace            @                     slave-if@5000             arm,cci-400-ctrl-if         !ace            P                     pmu@9000              arm,cci-400-pmu,r1                P       <         :          ;          <          =          >            serial@11002000       *    mediatek,mt6795-uart mediatek,mt6577-uart                                         [                             	  baud bus            0                     5tx rx           okay            ?default         M         serial@11003000       *    mediatek,mt6795-uart mediatek,mt6577-uart                 0                       \                             	  baud bus            0                    5tx rx         	  disabled          dma-controller@11000380       2    mediatek,mt6795-uart-dma mediatek,mt6577-uart-dma                        `             `            `             `            `             `            `             `      `         g          h          i          j          k          l          m          n           W                         apdma            d        x                    serial@11004000       *    mediatek,mt6795-uart mediatek,mt6577-uart                 @                       ]                              	  baud bus            0                    5tx rx           okay            ?default         M         serial@11005000       *    mediatek,mt6795-uart mediatek,mt6577-uart                 P                       ^                 !            	  baud bus            0                    5tx rx         	  disabled          pwm@11006000              mediatek,mt6795-pwm               `                                  M         H        S      	                                                ,  top main pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7       	  disabled          i2c@11007000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                p        p                            T                                        	  main dma                         +            okay            ?default         M         i2c@11008000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                        p                           U                                        	  main dma                         +            okay            ?default         M       accelerometer@10              bosch,bma255                        ?default         M   !      magnetometer@12           bosch,bmm150                         i2c@11009000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                        p                            V                                        	  main dma                         +            okay            ?default         M   "   touchscreen@20            syna,rmi4-i2c                                     +                             ?default         M   #                      Z   rmi4-f01@1                               rmi4-f12@12                                    i2c@11010000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                        p                           W                                        	  main dma                         +            okay            ?default         M   $   nfc@28            nxp,pn544-i2c               (                         ?default         M   %                                ^          proximity@48              sensortek,stk3310               H                         ?default         M   &         i2c@11011000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                       p                            X                                        	  main dma                         +          	  disabled          mmc@11230000              mediatek,mt6795-mmc              #                        O                       \      ]        source hclk source_cg           okay                       '           D           a            x        ?default state_uhs           M   '           (           )           *      mmc@11240000              mediatek,mt6795-mmc              $                        P                       O        source hclk         okay               +           ,      mmc@11250000              mediatek,mt6795-mmc              %                        Q                       O        source hclk         okay               +           ,      mmc@11260000              mediatek,mt6795-mmc              &                        R                       O        source hclk       	  disabled          syscon@14000000           mediatek,mt6795-mmsys syscon                                                        R        ׄ                                  -          -                 -                     .      ovl@1400c000          2    mediatek,mt6795-disp-ovl mediatek,mt8173-disp-ovl                                                                     .              /               -               ovl@1400d000          2    mediatek,mt6795-disp-ovl mediatek,mt8173-disp-ovl                                                                     .              /              -               rdma@1400e000         4    mediatek,mt6795-disp-rdma mediatek,mt8173-disp-rdma                                                                   .              /              -               rdma@1400f000         4    mediatek,mt6795-disp-rdma mediatek,mt8173-disp-rdma                                                                   .              /              -               rdma@14010000         4    mediatek,mt6795-disp-rdma mediatek,mt8173-disp-rdma                                                                   .              /              -                wdma@14011000         4    mediatek,mt6795-disp-wdma mediatek,mt8173-disp-wdma                                                                  .              /              -               wdma@14012000         4    mediatek,mt6795-disp-wdma mediatek,mt8173-disp-wdma                                                                   .              /              -                color@14013000        6    mediatek,mt6795-disp-color mediatek,mt8173-disp-color                0                                                    .              -     0          color@14014000        6    mediatek,mt6795-disp-color mediatek,mt8173-disp-color                @                                                    .              -     @          aal@14015000          2    mediatek,mt6795-disp-aal mediatek,mt8173-disp-aal                P                                                    .              -     P          gamma@14016000        6    mediatek,mt6795-disp-gamma mediatek,mt8173-disp-gamma                `                                                    .              -     `          merge@14017000        6    mediatek,mt6795-disp-merge mediatek,mt8173-disp-merge                p                                  .         split@14018000        6    mediatek,mt6795-disp-split mediatek,mt8173-disp-split                                                  .         split@14019000        6    mediatek,mt6795-disp-split mediatek,mt8173-disp-split                                                  .         ufoe@1401a000         4    mediatek,mt6795-disp-ufoe mediatek,mt8173-disp-ufoe                                                                  .              -               dsi@1401b000          (    mediatek,mt6795-dsi mediatek,mt8173-dsi                                                                  .   $   .   %   0        engine digital hs              0        dphy            okay                         +       panel@0           sharp,ls060t1sx01                           1           2           3        '   4        3      j           ?   5        M   6        ?default    port       endpoint            I   7           8            port       endpoint            I   8           7            dsi@1401c000          (    mediatek,mt6795-dsi mediatek,mt8173-dsi                                                                  .   &   .   '   9        engine digital hs              9        dphy          	  disabled          dpi@1401d000          (    mediatek,mt6795-dpi mediatek,mt8183-dpi                                                                  .   (   .   )              pixel engine pll          	  disabled          pwm@1401e000          2    mediatek,mt6795-disp-pwm mediatek,mt8173-disp-pwm                                              .   !   .            main mm         okay               ?      pwm@1401f000          2    mediatek,mt6795-disp-pwm mediatek,mt8173-disp-pwm                                              .   #   .   "        main mm       	  disabled          mutex@14020000            mediatek,mt8173-disp-mutex                                                                    .           Y   4   5           -                larb@14021000             mediatek,mt6795-smi-larb                                    .       .           apb smi         m   :        z                                    smi@14022000              mediatek,mt6795-smi-common                                                        .            apb smi            :      od@14023000       0    mediatek,mt6795-disp-od mediatek,mt8173-disp-od              0                   .              -     0          larb@15001000             mediatek,mt6795-smi-larb                                     .                  apb smi         m   :        z                                  clock-controller@16000000             mediatek,mt6795-vdecsys                                              ;      larb@16010000             mediatek,mt6795-smi-larb                                  m   :        z              ;       ;           apb smi                                clock-controller@18000000             mediatek,mt6795-vencsys                                              <      larb@18001000             mediatek,mt6795-smi-larb                                     <      <            apb smi         m   :        z                                     backlight             led-backlight              =   >          ,           5      led-controller-display        	    pwm-leds       led-0           backlight-pwm              ?                            =         memory@40000000          memory               @               reserved-memory                      +               secmon@43000000              C                         preloader-region@44800000                D                        bootloader-region@46000000               F        @                    regulator-disp-avdd           regulator-fixed       
  disp_avdd            LK@         LK@                                      1      regulator-disp-avee           regulator-fixed       
  disp_avee            LK@         LK@                                      2      regulator-disp-vddh           regulator-fixed       
  disp_vddh            w@         w@         s                    4         	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl1 rdma0 rdma1 rdma2 wdma0 wdma1 color0 color1 split0 split1 dpi0 dsi0 dsi1 mmc0 mmc1 mmc2 serial0 serial1 method device_type enable-method reg cci-control-port next-level-cache phandle i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets cpu cache-level cache-unified #clock-cells clock-frequency clock-output-names interrupts interrupt-affinity ranges #reset-cells #power-domain-cells clocks clock-names mediatek,infracfg reg-names gpio-controller #gpio-cells gpio-ranges interrupt-controller #interrupt-cells pinmux input-enable bias-pull-up bias-pull-down drive-strength output-high bias-disable timeout-sec resets reset-names regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-enable-ramp-delay regulator-allowed-modes regulator-always-on regulator-boot-on linux,keycodes wakeup-source label mediatek,larbs power-domains #iommu-cells status mediatek,hopping-ssc-percent #mbox-cells #phy-cells interface-type dmas dma-names pinctrl-names pinctrl-0 dma-requests mediatek,dma-33bits #dma-cells #pwm-cells clock-div interrupts-extended syna,startup-delay-ms syna,reset-delay-ms syna,nosleep-mode syna,sensor-type enable-gpios firmware-gpios mediatek,latch-ck mediatek,hs200-cmd-int-delay mediatek,hs400-cmd-int-delay mediatek,hs400-ds-dly3 non-removable pinctrl-1 vmmc-supply vqmmc-supply assigned-clocks assigned-clock-rates mboxes mediatek,gce-client-reg iommus phys phy-names avdd-supply avee-supply vddi-supply vddh-supply reset-gpios backlight remote-endpoint mediatek,gce-events mediatek,smi mediatek,larb-id leds default-brightness-level pwms max-brightness no-map gpio enable-active-high 