     8  {    (            x  z                             $    mediatek,mt8173-evb mediatek,mt8173                                  +         !   7MediaTek MT8173 evaluation board          	   =embedded       aliases          J/soc/ovl@1400c000            O/soc/ovl@1400d000            T/soc/rdma@1400e000           Z/soc/rdma@1400f000           `/soc/rdma@14010000           f/soc/wdma@14011000           l/soc/wdma@14012000           r/soc/color@14013000          y/soc/color@14014000          /soc/split@14018000          /soc/split@14019000          /soc/dpi@1401d000            /soc/dsi@1401b000            /soc/dsi@1401c000            /soc/rdma@14001000           /soc/rdma@14002000           /soc/rsz@14003000            /soc/rsz@14004000            /soc/rsz@14005000            /soc/wdma@14006000           /soc/wrot@14007000           /soc/wrot@14008000           /soc/serial@11002000             /soc/serial@11003000             /soc/serial@11004000            /soc/serial@11005000          opp-table-0           operating-points-v2          
           	   opp-507000000               84        $ x      opp-702000000               )׫        $       opp-1001000000              ;@        $       opp-1105000000              A@        $ eh      opp-1209000000              H@        $       opp-1300000000              M|m         $        opp-1508000000              YA         $       opp-1703000000              e        $ *         opp-table-1           operating-points-v2          
              opp-507000000               84        $ `      opp-702000000               )׫        $ :      opp-1001000000              ;@        $ %      opp-1209000000              H@        $ @      opp-1404000000              SW         $ ]      opp-1612000000              `+         $       opp-1807000000              k        $       opp-2106000000              }        $ *         cpus                         +       cpu-map    cluster0       core0           2         core1           2            cluster1       core0           2         core1           2               cpu@0           6cpu           arm,cortex-a53          B            Fpsci            T           d           s                              cpu intermediate               	                     
                 cpu@1           6cpu           arm,cortex-a53          B           Fpsci            T           d           s                              cpu intermediate               	                     
                 cpu@100         6cpu           arm,cortex-a72          B           Fpsci            T           d           s                              cpu intermediate                                                                 cpu@101         6cpu           arm,cortex-a72          B          Fpsci            T           d           s                              cpu intermediate                                                                 idle-states         psci       cpu-sleep-0           arm,idle-state                                         @        /                          pmu-a53           arm,cortex-a53-pmu          F                 	           Q            pmu-a72           arm,cortex-a72-pmu          F                            Q            psci          #    arm,psci-1.0 arm,psci-0.2 arm,psci          Msmc         d          p          x        oscillator0           fixed-clock                             clk26m                   oscillator1           fixed-clock                       }         clk32k        oscillator2           fixed-clock                                 cpum_ck       thermal-zones      cpu-thermal                                             trips      trip-point0          	                   Epassive       trip-point1          L                   Epassive                  cpu-crit0            8                	   Ecritical             cooling-maps       map0                                               map1                                                        reserved-memory                      +            -   vpu-dma-mem@b7000000              shared-dma-pool         B            P          4            >                    timer             arm,armv8-timer                   0  F                              
           E      soc                      +             simple-bus           -   clock-controller@10000000             mediatek,mt8173-topckgen            B                                          power-controller@10001000              mediatek,mt8173-infracfg syscon         B                                \                    power-controller@10003000             mediatek,mt8173-pericfg syscon          B     0                           \                    syscon@10005000       %    mediatek,mt8173-pctl-a-syscfg syscon            B     P                         pinctrl@1000b000              mediatek,mt8173-pinctrl         B                     i            ~                                     $  F                                            xxx            A   pins1                                        i2c0                  pins1             -  .                  i2c1                   pins1             }  ~                  i2c2               !   pins1             +  ,                  i2c3               %   pins1             j  k                  i2c4               &   pins1                                 i2c6               '   pins1             d  e                  disp_pwm0_pins             ?   pins1             W                  mmc0default            (   pins_cmd_dat          $    9  :  ;  <  =  >  ?  @  B                        pins_clk              A               pins_rst              D                  mmc1default            ,   pins_cmd_dat              I  J  K  L  N                               f      pins_clk              M                          pins_insert                              mmc0               )   pins_cmd_dat          $    9  :  ;  <  =  >  ?  @  B                               e      pins_clk              A                      e      pins_rst              D                  mmc1               -   pins_cmd_dat              I  J  K  L  N                               f      pins_clk              M                      f         usb_iddig_pull_up              6   pins_iddig                              usb_iddig_pull_down    pins_iddig                              spi0               "   pins_spi              E  F  G  H            syscon@10006000       )    mediatek,mt8173-scpsys syscon simple-mfd            B     `           power-controller          !    mediatek,mt8173-power-controller                         +                             power-domain@0          B                  U        mm                    power-domain@1          B                 U      X        mm venc                   power-domain@2          B                 U        mm                    power-domain@3          B                 U        mm                      +         power-domain@4          B                 U      i      
  mm venclt                     power-domain@5          B                     power-domain@6          B                     power-domain@7          B                      mfg                      +                       =      power-domain@8          B                        +                  power-domain@9          B   	                    +                     watchdog@10007000         (    mediatek,mt8173-wdt mediatek,mt6589-wdt         B     p              timer@10008000        ,    mediatek,mt8173-timer mediatek,mt6577-timer         B                     F                              x      pwrap@1000d000            mediatek,mt8173-pwrap           B                     Kpwrap           F                  U              \pwrap                 
            	  spi wrap            h         pmic              mediatek,mt6397         v                                regulators            mediatek,mt6397-regulator      buck_vpca15         vpca15           
`         p          0                    
      buck_vpca7          vpca7            
`         p          0           s      buck_vsramca15        
  vsramca15            
`         p          0               buck_vsramca7         	  vsramca7             
`         p          0                          buck_vcore          vcore            
`         p          0               buck_vgpu           vgpu             
`         p          0           s      buck_vdrm           vdrm             O         \          0               buck_vio18          vio18                      6`          0                    +      ldo_vtcxo           vtcxo                  ldo_va28            va28                   ldo_vcama           vcama            `         *                 ldo_vio28           vio28                  ldo_vusb            vusb               3      ldo_vmc         vmc          w@         2Z                      /      ldo_vmch            vmch             -         2Z                      .      ldo_vemc3v3       	  vemc_3v3             -         2Z                      *      ldo_vgp1            vcamd                     2Z                 ldo_vgp2            vcamio           B@         2Z                 ldo_vgp3            vcamaf           O         2Z                 ldo_vgp4            vgp4             O         2Z                 ldo_vgp5            vgp5             O         -                 ldo_vgp6            vgp6             O         2Z                 ldo_vibr            vibr                       2Z                          cec@10013000              mediatek,mt8173-cec         B    0                F                        	        okay          vpu@10020000              mediatek,mt8173-vpu          B                                  Ktcm cfg_reg         F                        g        main                          ;      intpol-controller@10200620        .    mediatek,mt8173-sysirq mediatek,mt6577-sysirq                                           B                               iommu@10205000            mediatek,mt8173-m4u         B     P                F                                bclk            +           #                          2              :      efuse@10206000            mediatek,mt8173-efuse           B     `                             +      socinfo-data1@40            B   @         socinfo-data2@44            B   D         calib@528           B  (              $         clock-controller@10209000             mediatek,mt8173-apmixedsys          B                                         hdmi-phy@10209100             mediatek,mt8173-hdmi-phy            B             $                      pll_ref         hdmitx_dig_cts          ?   
        N                       `            okay               B      mailbox@10212000              mediatek,mt8173-gce         B    !                 F                                gce         k              8      dsi-phy@10215000              mediatek,mt8173-mipi-tx         B    !P                           mipi_tx0_pll                        `          	  disabled               <      dsi-phy@10216000              mediatek,mt8173-mipi-tx         B    !`                           mipi_tx1_pll                        `          	  disabled               =      interrupt-controller@10221000             arm,gic-400                                       @  B    "            "              "@             "`                 F      	                   auxadc@11001000           mediatek,mt8173-auxadc          B                                   main            w              #      serial@11002000       *    mediatek,mt8173-uart mediatek,mt6577-uart           B                      F       S                 $            	  baud bus            okay          serial@11003000       *    mediatek,mt8173-uart mediatek,mt6577-uart           B     0                F       T                 %            	  baud bus          	  disabled          serial@11004000       *    mediatek,mt8173-uart mediatek,mt6577-uart           B     @                F       U                 &            	  baud bus          	  disabled          serial@11005000       *    mediatek,mt8173-uart mediatek,mt6577-uart           B     P                F       V                 '            	  baud bus          	  disabled          i2c@11007000              mediatek,mt8173-i2c          B     p        p                     F       L                                        	  main dma            default                                 +          	  disabled          i2c@11008000              mediatek,mt8173-i2c          B             p                    F       M                                        	  main dma            default                                  +            okay       da9211@68             dlg,da9211          B   h   regulators     BUCKA           VBUCKA           
`         0                  C#          '                          BUCKB           VBUCKB           
`         0                  -          '                          i2c@11009000              mediatek,mt8173-i2c          B             p                     F       N                                        	  main dma            default            !                     +          	  disabled          spi@1100a000              mediatek,mt8173-spi                      +            B                     F       n                 4      \              parent-clk sel-clk spi-clk          okay            default            "                  thermal@1100b000                          mediatek,mt8173-thermal         B                     F       F                               therm auxadc            U                 #                   '   $        3calibration-data                     spi@1100d000              mediatek,mt8173-nor         B                     D      \        T                 !      r              spi sf axi                       +          	  disabled          i2c@11010000              mediatek,mt8173-i2c          B             p                    F       O                                        	  main dma            default            %                     +          	  disabled          i2c@11011000              mediatek,mt8173-i2c          B            p                     F       P                                        	  main dma            default            &                     +          	  disabled          i2c@11012000              mediatek,mt8173-hdmi-ddc            F       Q           B                                   ddc-i2c       i2c@11013000              mediatek,mt8173-i2c          B    0        p                     F       R                            #            	  main dma            default            '                     +          	  disabled          audio-controller@11220000             mediatek,mt8173-afe-pcm         B    "                 F                  h            P              d      e      y                                          b  infra_sys_audio_clk top_pdn_audio top_pdn_aud_intbus bck0 bck1 i2s0_m i2s1_m i2s2_m i2s3_m i2s3_b           D      m      n        T                  mmc@11230000              mediatek,mt8173-mmc         B    #                 F       G                       _        source hclk         okay            default state_uhs              (        k   )        u                                                              *           +               mmc@11240000              mediatek,mt8173-mmc         B    $                 F       H                       R        source hclk         okay            default state_uhs              ,        k   -        u                    #         4        A                     .           /      mmc@11250000              mediatek,mt8173-mmc         B    %                 F       I                       R        source hclk       	  disabled          mmc@11260000              mediatek,mt8173-mmc         B    &                 F       J                       u        source hclk       	  disabled          usb@11271000          #    mediatek,mt8173-mtu3 mediatek,mtu3           B    '       0     (              	  Kmac ippc            F       @           J   0      1      2           h                    ^           sys_ck ref_ck           O                              +            -        okay            f   3        t   4           5        otg                  default            6   usb@11270000          '    mediatek,mt8173-xhci mediatek,mtk-xhci          B    '                 Kmac         F       s           h                    ^           sys_ck ref_ck           okay            f   3        t   7         t-phy@11290000            mediatek,mt8173-u3phy           B    )                              +            -        okay       usb-phy@11290800            B    )                              ref         `           okay               0      usb-phy@11290900            B    )	                           ref         `           okay               1      usb-phy@11291000            B    )                              ref         `           okay               2         syscon@14000000           mediatek,mt8173-mmsys syscon            B                      h              D      U        ׄ                    \              8          8                 8                     9      rdma@14001000         -    mediatek,mt8173-mdp-rdma mediatek,mt8173-mdp            B                        9      9           h                 :              ;      rdma@14002000             mediatek,mt8173-mdp-rdma            B                         9      9           h                 :         rsz@14003000              mediatek,mt8173-mdp-rsz         B     0                   9           h            rsz@14004000              mediatek,mt8173-mdp-rsz         B     @                   9           h            rsz@14005000              mediatek,mt8173-mdp-rsz         B     P                   9           h            wdma@14006000             mediatek,mt8173-mdp-wdma            B     `                   9           h                 :         wrot@14007000             mediatek,mt8173-mdp-wrot            B     p                   9           h                 :         wrot@14008000             mediatek,mt8173-mdp-wrot            B                        9           h                 :         ovl@1400c000              mediatek,mt8173-disp-ovl            B                     F                  h                 9              :               8               ovl@1400d000              mediatek,mt8173-disp-ovl            B                     F                  h                 9              :              8               rdma@1400e000             mediatek,mt8173-disp-rdma           B                     F                  h                 9              :              8               rdma@1400f000             mediatek,mt8173-disp-rdma           B                     F                  h                 9              :              8               rdma@14010000             mediatek,mt8173-disp-rdma           B                     F                  h                 9              :              8                wdma@14011000             mediatek,mt8173-disp-wdma           B                    F                  h                 9              :              8               wdma@14012000             mediatek,mt8173-disp-wdma           B                     F                  h                 9              :              8                color@14013000            mediatek,mt8173-disp-color          B    0                F                  h                 9              8     0          color@14014000            mediatek,mt8173-disp-color          B    @                F                  h                 9              8     @          aal@14015000              mediatek,mt8173-disp-aal            B    P                F                  h                 9              8     P          gamma@14016000            mediatek,mt8173-disp-gamma          B    `                F                  h                 9              8     `          merge@14017000            mediatek,mt8173-disp-merge          B    p                h                 9         split@14018000            mediatek,mt8173-disp-split          B                    h                 9         split@14019000            mediatek,mt8173-disp-split          B                    h                 9         ufoe@1401a000             mediatek,mt8173-disp-ufoe           B                    F                  h                 9              8               dsi@1401b000              mediatek,mt8173-dsi         B                    F                  h                 9   $   9   %   <        engine digital hs           U   9           J   <        dphy          	  disabled          dsi@1401c000              mediatek,mt8173-dsi         B                    F                  h                 9   &   9   '   =        engine digital hs           J   =        dphy          	  disabled          dpi@1401d000              mediatek,mt8173-dpi         B                    F                  h                 9   (   9   )              pixel engine pll            okay       port       endpoint               >           C            pwm@1401e000              mediatek,mt8173-disp-pwm            B                                  9   !   9            main mm         okay            default            ?      pwm@1401f000              mediatek,mt8173-disp-pwm            B                                  9   #   9   "        main mm       	  disabled          mutex@14020000            mediatek,mt8173-disp-mutex          B                     F                  h                 9              8                  
   5   6      larb@14021000             mediatek,mt8173-smi-larb            B                       @        h                 9      9           apb smi                  smi@14022000              mediatek,mt8173-smi-common          B                     h                 9      9           apb smi            @      od@14023000           mediatek,mt8173-disp-od         B    0                   9              8     0          hdmi@14025000             mediatek,mt8173-hdmi            B    P                F                      9   ,   9   -   9   .   9   /        pixel pll bclk spdif            default            A        J   B        hdmi            +   9  	         D      s        T   B        okay       ports                        +       port@0          B       endpoint               C           >         port@1          B      endpoint               D           I               larb@14027000             mediatek,mt8173-smi-larb            B    p                   @        h                 9   2   9   2        apb smi                  clock-controller@15000000             mediatek,mt8173-imgsys syscon           B                                    E      larb@15001000             mediatek,mt8173-smi-larb            B                        @        h                 E      E           apb smi                  clock-controller@16000000             mediatek,mt8173-vdecsys syscon          B                                    F      vcodec@16020000           mediatek,mt8173-vcodec-dec          B                                                      0            @            P            h            p            x                          (  Kmisc ld top cm ad av pp hwd hwq hwb hwg         F                @     :       :   !   :   %   :   &   :   '   :   "   :   #   :   $           ;        @   F        h             @        
      >      l      W      M            i      N      Z  vcodecpll univpll_d2 clk_cci400_sel vdec_sel vdecpll vencpll venc_lt_sel vdec_bus_clk_src         (  D      i      l      W      
              T      N      >      M                    XU/       larb@16010000             mediatek,mt8173-smi-larb            B                        @        h                  F      F           apb smi                  clock-controller@18000000             mediatek,mt8173-vencsys syscon          B                                    G      larb@18001000             mediatek,mt8173-smi-larb            B                        @        h                 G      G           apb smi                  vcodec@18002000           mediatek,mt8173-vcodec-enc          B                      F                X     :   `   :   a   :   b   :   c   :   d   :   i   :   j   :   k   :   l   :   m   :   n           ;              X      	  venc_sel            D      X        T      M        h            jpegdec@18004000              mediatek,mt8173-jpgdec          B     @                F                     G      G           jpgdec-smi jpgdec           h                 :   g   :   h      clock-controller@19000000         !    mediatek,mt8173-vencltsys syscon            B                                    H      larb@19001000             mediatek,mt8173-smi-larb            B                        @        h                 H      H           apb smi                  vcodec@19002000           mediatek,mt8173-vcodec-enc-vp8          B                      F                H     :      :      :      :      :      :      :      :      :              ;              i        venc_lt_sel         D      i        T      N        h               memory@40000000         6memory          B    @                chosen        connector             hdmi-connector          Qhdmi             Ed      port       endpoint               I           D            extcon_iddig              linux,extcon-usb-gpio           W                     5      regulator-usb-p1              regulator-fixed       	  usb_vbus             LK@         LK@        `                   e           7      regulator-usb-p0              regulator-fixed         vbus             LK@         LK@        `      	             e           4         	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl1 rdma0 rdma1 rdma2 wdma0 wdma1 color0 color1 split0 split1 dpi0 dsi0 dsi1 mdp-rdma0 mdp-rdma1 mdp-rsz0 mdp-rsz1 mdp-rsz2 mdp-wdma0 mdp-wrot0 mdp-wrot1 serial0 serial1 serial2 serial3 opp-shared phandle opp-hz opp-microvolt cpu device_type reg enable-method cpu-idle-states #cooling-cells dynamic-power-coefficient clocks clock-names operating-points-v2 capacity-dmips-mhz proc-supply sram-supply entry-method local-timer-stop entry-latency-us exit-latency-us min-residency-us arm,psci-suspend-param interrupts interrupt-affinity cpu_suspend cpu_off cpu_on #clock-cells clock-frequency clock-output-names polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution ranges alignment no-map arm,no-tick-in-suspend #reset-cells mediatek,pctl-regmap gpio-controller #gpio-cells interrupt-controller #interrupt-cells pinmux input-enable bias-pull-down bias-disable output-low bias-pull-up drive-strength #power-domain-cells mediatek,infracfg domain-supply reg-names resets reset-names power-domains interrupts-extended regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-always-on regulator-enable-ramp-delay status memory-region mediatek,larbs #iommu-cells mediatek,ibias mediatek,ibias_up #phy-cells #mbox-cells #io-channel-cells clock-div pinctrl-names pinctrl-0 regulator-min-microamp regulator-max-microamp mediatek,pad-select #thermal-sensor-cells mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names assigned-clocks assigned-clock-parents pinctrl-1 bus-width max-frequency cap-mmc-highspeed mediatek,hs200-cmd-int-delay mediatek,hs400-cmd-int-delay mediatek,hs400-cmd-resp-sel-rising vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr25 cd-gpios phys mediatek,syscon-wakeup vusb33-supply vbus-supply extcon dr_mode wakeup-source assigned-clock-rates mboxes mediatek,gce-client-reg iommus mediatek,vpu phy-names remote-endpoint #pwm-cells mediatek,gce-events mediatek,smi mediatek,syscon-hdmi mediatek,vdecsys label id-gpios gpio enable-active-high 