     8      (                                           $    mediatek,mt8183-evb mediatek,mt8183                                  +         !   7MediaTek MT8183 evaluation board          	   =embedded       aliases          J/soc/i2c@11007000            O/soc/i2c@11011000            T/soc/i2c@11009000            Y/soc/i2c@1100f000            ^/soc/i2c@11008000            c/soc/i2c@11016000            h/soc/i2c@11005000            m/soc/i2c@1101a000            r/soc/i2c@1101b000            w/soc/i2c@11014000            |/soc/i2c@11015000            /soc/i2c@11017000            /soc/ovl@14008000            /soc/ovl@14009000            /soc/ovl@1400a000            /soc/rdma@1400b000           /soc/rdma@1400c000           /soc/serial@11002000          opp-table-cluster0            operating-points-v2                           opp0-793000000               /D8@          	                  opp0-910000000               6=          
}                  opp0-1014000000              <pi          
                  opp0-1131000000              Ci                            opp0-1248000000              Jb           5                   opp0-1326000000              O	'          ~>                  opp0-1417000000              Tu@          P                  opp0-1508000000              YA           A            	      opp0-1586000000              ^p          6            
      opp0-1625000000              `ۈ@          
                  opp0-1677000000              c@          5                  opp0-1716000000              fH           f                  opp0-1781000000              j'@                            opp0-1846000000              n          B@                  opp0-1924000000              r                             opp0-1989000000              v@                               opp-table-cluster1            operating-points-v2                       $   opp1-793000000               /D8@          
`                  opp1-910000000               6=                            opp1-1014000000              <pi          q                  opp1-1131000000              Ci          X                  opp1-1248000000              Jb           5                   opp1-1326000000              O	'                            opp1-1417000000              Tu@          P                  opp1-1508000000              YA           Y            	      opp1-1586000000              ^p                      
      opp1-1625000000              `ۈ@          t                  opp1-1677000000              c@          5                  opp1-1716000000              fH           ~                  opp1-1781000000              j'@                            opp1-1846000000              n          B@                  opp1-1924000000              r                             opp1-1989000000              v@                               opp-table-cci             operating-points-v2                          opp-273000000                E@          	                  opp-338000000                %x          
}                  opp-403000000                J          
                  opp-463000000                                            opp-546000000                 L          5                   opp-624000000                %1|           ~>                  opp-689000000                )N@          P                  opp-767000000                -}          A            	      opp-845000000                2]@          6            
      opp-871000000                3g          
                  opp-923000000                7          5                  opp-962000000                9V          f                  opp-1027000000               =6                            opp-1092000000               A           B@                  opp-1144000000               D0                             opp-1196000000               GI                                cci           mediatek,mt8183-cci                               cci intermediate                                       "      cpus                         +       cpu-map    cluster0       core0                    core1                    core2                    core3                       cluster1       core0                    core1                    core2                    core3                          cpu@0           cpu           arm,cortex-a53          *            .psci            <          O                                     cpu intermediate                         _   T        y              @                                 @                      !                      "                             cpu@1           cpu           arm,cortex-a53          *           .psci            <          O                                     cpu intermediate                         _   T        y              @                                 @                      !                      "                             cpu@2           cpu           arm,cortex-a53          *           .psci            <          O                                     cpu intermediate                         _   T        y              @                                 @                      !                      "                             cpu@3           cpu           arm,cortex-a53          *           .psci            <          O                                     cpu intermediate                         _   T        y              @                                 @                      !                      "                             cpu@100         cpu           arm,cortex-a73          *           .psci            <           O      #                              cpu intermediate                $        _           y              @                                 @                      %                      "           &                  cpu@101         cpu           arm,cortex-a73          *          .psci            <           O      #                              cpu intermediate                $        _           y              @                                 @                      %                      "           &                  cpu@102         cpu           arm,cortex-a73          *          .psci            <           O      #                              cpu intermediate                $        _           y              @                                 @                      %                      "           &                  cpu@103         cpu           arm,cortex-a73          *          .psci            <           O      #                              cpu intermediate                $        _           y              @                                 @                      %                      "           &                  idle-states         psci       cpu-sleep             arm,idle-state                             3           D           T                     cluster-sleep-0           arm,idle-state                            3           D          T                    cluster-sleep-1           arm,idle-state                            3           D          T              #         l2-cache0             cache           e           {              @                    q            !      l2-cache1             cache           e           {              @                    q            %         opp-table-0           operating-points-v2                       ^   opp-300000000                           	h      opp-320000000                           	      opp-340000000                C           	<      opp-360000000                u*           	Ҧ      opp-380000000                W           	      opp-400000000                ׄ           
z      opp-420000000                           
      opp-460000000                k           
L      opp-500000000                e           
}      opp-540000000                 /           
`      opp-580000000                "           
4      opp-620000000                $s                 opp-653000000                &@          YF      opp-698000000                )                opp-743000000                ,IG                opp-800000000                /                    pmu-a53           arm,cortex-a53-pmu              '                    (      pmu-a73           arm,cortex-a73-pmu              '                    )      psci              arm,psci-1.0            5smc       fixed-factor-clock-13m            fixed-factor-clock                          *                              clk13m              5      oscillator            fixed-clock                             clk26m              *      timer             arm,armv8-timer             '      @                                               
             soc                      +             simple-bus              efuse@8000000         %    mediatek,mt8183-efuse mediatek,efuse            *                                   +         	  disabled          interrupt-controller@c000000              arm,gic-v3                         '               P  *                                @              A             B                        	                   '   ppi-partitions     interrupt-partition-0                                   (      interrupt-partition-1                                   )            syscon@c530000            mediatek,mt8183-mcucfg syscon           *    S                                      interrupt-controller@c530a80          .    mediatek,mt8183-sysirq mediatek,mt6577-sysirq                                   '        *    S
       P                  cpu-debug@d410000         &    arm,coresight-cpu-debug arm,primecell           *    A                     +   .      	   apb_pclk                     cpu-debug@d510000         &    arm,coresight-cpu-debug arm,primecell           *    Q                     +   .      	   apb_pclk                     cpu-debug@d610000         &    arm,coresight-cpu-debug arm,primecell           *    a                     +   .      	   apb_pclk                     cpu-debug@d710000         &    arm,coresight-cpu-debug arm,primecell           *    q                     +   .      	   apb_pclk                     cpu-debug@d810000         &    arm,coresight-cpu-debug arm,primecell           *                         +   .      	   apb_pclk                     cpu-debug@d910000         &    arm,coresight-cpu-debug arm,primecell           *                         +   .      	   apb_pclk                     cpu-debug@da10000         &    arm,coresight-cpu-debug arm,primecell           *                         +   .      	   apb_pclk                     cpu-debug@db10000         &    arm,coresight-cpu-debug arm,primecell           *                         +   .      	   apb_pclk                     syscon@10000000            mediatek,mt8183-topckgen syscon         *                                           syscon@10001000            mediatek,mt8183-infracfg syscon         *                                               +      syscon@10003000           mediatek,mt8183-pericfg syscon          *     0                               Q      pinctrl@10005000              mediatek,mt8183-pinctrl         *     P                                                                                                                                   D  iocfg0 iocfg1 iocfg2 iocfg3 iocfg4 iocfg5 iocfg6 iocfg7 iocfg8 eint          #        3           ?   ,                                                             ,   i2c0                =   pins_i2c            K  R  S        R            i2c1                I   pins_i2c            K  Q  T        R            i2c2                ?   pins_i2c            K  g  h        R            i2c3                G   pins_i2c            K  2  3        R            i2c4                >   pins_i2c            K  i  j        R            i2c5                L   pins_i2c            K  0  1        R            spi0                @   pins_spi            K  U  V  W  X         g         mmc0default             T   pins_cmd_dat          $  K  {    }    ~        z         t               pins_clk            K  |               pins_rst            K                    mmc0                U   pins_cmd_dat          $  K  {    }    ~        z         t           
           e      pins_clk            K  |           
           f      pins_ds         K             
           f      pins_rst            K             
                  mmc1default             X   pins_cmd_dat            K       "  !           t               pins_clk            K           t               pins_pmu            K                        mmc1                Y   pins_cmd_dat            K       "  !                      t           e      pins_clk            K                        f         t         spi1                H   pins_spi            K                 g         spi2                J   pins_spi            K         ^         g         spi3                K   pins_spi            K                 g         spi4                M   pins_spi            K                 g         spi5                N   pins_spi            K                 g         pwm1                F   pins_pwm            K  Z            syscon@10006000       )    mediatek,mt8183-scpsys syscon simple-mfd            *     `           power-controller          !    mediatek,mt8183-power-controller                         +                           E   power-domain@0          *                      +   /   +   7         audio audio1 audio2                   power-domain@1          *              +                  power-domain@2          *                        +                  power-domain@3          *                        +                          -   power-domain@4          *                     power-domain@5          *                     power-domain@6          *              +                        power-domain@7          *         X            .       .      .      .      .      .      .      .      .      .   	      5   mm mm-0 mm-1 mm-2 mm-3 mm-4 mm-5 mm-6 mm-7 mm-8 mm-9               +           /                     +                  power-domain@8          *         @            0       0   	   0      0      0      0      0         .   cam cam-0 cam-1 cam-2 cam-3 cam-4 cam-5 cam-6              +           /                  power-domain@9          *   	               "   1   	   1            isp isp-0 isp-1            +           /                  power-domain@10         *   
           /                  power-domain@11         *              /                  power-domain@12         *         @         &      #   2       2      2      2      2      2         -   vpu vpu1 vpu-0 vpu-1 vpu-2 vpu-3 vpu-4 vpu-5               +           /                     +                  power-domain@13         *                  $         vpu2               +                  power-domain@14         *                  %         vpu3               +                              watchdog@10007000             mediatek,mt8183-wdt         *     p                               R      syscon@1000c000       "    mediatek,mt8183-apmixedsys syscon           *                                    B      pwrap@1000d000            mediatek,mt8183-pwrap           *                     pwrap                                    )   +         	   spi wrap       pmic              mediatek,mt6358                                ,         adc           mediatek,mt6358-auxadc                   audio-codec           mediatek,mt6358-sound                     regulators            mediatek,mt6358-regulator      buck_vdram1         2vdram1          A          Y L        q  0                                          buck_vcore          2vcore           A          Y         q  j                                         buck_vpa            2vpa         A          Y 7        q  P                                buck_vproc11            2vproc11         A          Y         q  j                                               &      buck_vproc12            2vproc12         A          Y         q  j                                                     buck_vgpu           2vgpu            A 	h        Y         q  j                                     3                     -      buck_vs2            2vs2         A          Y L        q  0                           buck_vmodem         2vmodem          A          Y         q  j                                        buck_vs1            2vs1         A B@        Y '{l        q  0                           ldo_vdram2          2vdram2          A 	'        Y w@                ldo_vsim1           2vsim1           A         Y /M`                ldo_vibr            2vibr            A O        Y 2Z           <      ldo_vrf12           2vrf12           A O        Y O           x      ldo_vio18           2vio18           A w@        Y w@          
                     W      ldo_vusb            2vusb            A -        Y /M`                         ldo_vcamio          2vcamio          A w@        Y w@          E      ldo_vcamd           2vcamd           A         Y w@          E      ldo_vcn18           2vcn18           A w@        Y w@                ldo_vfe28           2vfe28           A *        Y *                ldo_vsram_proc11            2vsram_proc11            A          Y         q  j                          ldo_vcn28           2vcn28           A *        Y *                ldo_vsram_others            2vsram_others            A          Y         q  j                          ldo_vsram_gpu         
  2vsram_gpu           A P        Y B@        q  j                      -                     3      ldo_vxo22           2vxo22           A !        Y !           x               ldo_vefuse          2vefuse          A         Y                 ldo_vaux18          2vaux18          A w@        Y w@                ldo_vmch            2vmch            A ,@         Y 2Z           <            Z      ldo_vbif28          2vbif28          A *        Y *                ldo_vsram_proc12            2vsram_proc12            A          Y         q  j                          ldo_vcama1          2vcama1          A w@        Y -          E      ldo_vemc            2vemc            A ,@         Y 2Z           <            V      ldo_vio28           2vio28           A *        Y *                ldo_va12            2va12            A O        Y O                         ldo_vrf18           2vrf18           A w@        Y w@           x      ldo_vcn33           2vcn33           A 2Z        Y 5g                ldo_vcama2          2vcama2          A w@        Y -          E      ldo_vmc         2vmc         A w@        Y 2Z           <            [      ldo_vldo28          2vldo28          A *        Y -                ldo_vaud28          2vaud28          A *        Y *                ldo_vsim2           2vsim2           A         Y /M`                   rtc           mediatek,mt6358-rtc       keys              mediatek,mt6358-keys       power              t               home               f               keyboard@10010000         .    mediatek,mt8183-keypad mediatek,mt6779-keypad           *                                           *         kpd       	  disabled          scp@10500000              mediatek,mt8183-scp          *    P             \             	  sram cfg                                  +            main               4      	  disabled                b      timer@10017000        ,    mediatek,mt8183-timer mediatek,mt6765-timer         *    p                                      5      iommu@10205000            mediatek,mt8183-m4u         *     P                                  -   6   7   8   9   :   ;   <        <               `      mailbox@10238000              mediatek,mt8183-gce         *    #       @                           I               +            gce             _      auxadc@11001000       .    mediatek,mt8183-auxadc mediatek,mt8173-auxadc           *                         +   #         main                       okay                A      serial@11002000       *    mediatek,mt8183-uart mediatek,mt6577-uart           *                             [               *   +         	   baud bus            okay          serial@11003000       *    mediatek,mt8183-uart mediatek,mt6577-uart           *     0                       \               *   +         	   baud bus          	  disabled          serial@11004000       *    mediatek,mt8183-uart mediatek,mt6577-uart           *     @                       ]               *   +         	   baud bus          	  disabled          i2c@11005000              mediatek,mt8183-i2c          *     P                                    W               +   W   +   *      	   main dma                                    +          	  disabled          i2c@11007000              mediatek,mt8183-i2c          *     p                                    Q               +   
   +   *      	   main dma                                    +            okay            Udefault         c   =               i2c@11008000              mediatek,mt8183-i2c          *                                         R               +      +   *   +   G         main dma arb                                    +            okay            Udefault         c   >         B@      i2c@11009000              mediatek,mt8183-i2c          *                                        S               +      +   *   +   I         main dma arb                                    +            okay            Udefault         c   ?               spi@1100a000              mediatek,mt8183-spi                      +            *                            x                  6         +            parent-clk sel-clk spi-clk          okay            Udefault         c   @        m          thermal-sensor@1100b000                      mediatek,mt8183-thermal         *                         +   	   +   #         therm auxadc               +                   L              A           B           C        calibration-data                e      svs@1100bc00              mediatek,mt8183-svs         *                                           +   	         main               D   C      (  svs-calibration-data t-calibration-data       pwm@1100e000              mediatek,mt8183-disp-pwm            *                                          E                                +   5         main mm       pwm@11006000              mediatek,mt8183-pwm         *     `                         0      +      +      +      +      +      +            top main pwm1 pwm2 pwm3 pwm4            okay            c   F        Udefault       i2c@1100f000              mediatek,mt8183-i2c          *                                         T               +      +   *      	   main dma                                    +            okay            Udefault         c   G               spi@11010000              mediatek,mt8183-spi                      +            *                            |                  6         +   8         parent-clk sel-clk spi-clk          okay            Udefault         c   H        m          i2c@11011000              mediatek,mt8183-i2c          *                                       U               +   9   +   *      	   main dma                                    +            okay            Udefault         c   I               spi@11012000              mediatek,mt8183-spi                      +            *                                              6         +   ;         parent-clk sel-clk spi-clk          okay            Udefault         c   J        m          spi@11013000              mediatek,mt8183-spi                      +            *    0                                         6         +   <         parent-clk sel-clk spi-clk          okay            Udefault         c   K        m          i2c@11014000              mediatek,mt8183-i2c          *    @                                                  +   H   +   *   +   G         main dma arb                                    +          	  disabled          i2c@11015000              mediatek,mt8183-i2c          *    P                                                   +   J   +   *   +   I         main dma arb                                    +          	  disabled          i2c@11016000              mediatek,mt8183-i2c          *    `                                    V               +   D   +   *   +   E         main dma arb                                    +            okay            Udefault         c   L         B@      i2c@11017000              mediatek,mt8183-i2c          *    p                                                  +   F   +   *   +   E         main dma arb                                    +          	  disabled          spi@11018000              mediatek,mt8183-spi                      +            *                                             6         +   K         parent-clk sel-clk spi-clk          okay            Udefault         c   M        m          spi@11019000              mediatek,mt8183-spi                      +            *                                             6         +   L         parent-clk sel-clk spi-clk          okay            Udefault         c   N        m          i2c@1101a000              mediatek,mt8183-i2c          *                                       X               +   b   +   *      	   main dma                                    +          	  disabled          i2c@1101b000              mediatek,mt8183-i2c          *                                        Y               +   c   +   *      	   main dma                                    +          	  disabled          usb@11201000          #    mediatek,mt8183-mtu3 mediatek,mtu3           *            .      >              	  mac ippc                   H              O      P               +   =   +   Z         sys_ck ref_ck              Q      e                     +                  	  disabled       usb@11200000          '    mediatek,mt8183-xhci mediatek,mtk-xhci          *                      mac                I               +   =   +   Z         sys_ck ref_ck         	  disabled             audio-controller@11220000              mediatek,mt8183-audiosys syscon         *    "                                S   mt8183-afe-pcm            mediatek,mt8183-audio                                R         	  audiosys               E         D      S      S      S      S      S      S      S      S      S      S      S      S   
   S   	   S      S       +   /   +   7                  0            H            L            K            O      t      u      v      w      x      y      z      {      |      }      ~         *     w   aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adc_adda6_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_i2s1_bclk_sw aud_i2s2_bclk_sw aud_i2s3_bclk_sw aud_i2s4_bclk_sw aud_tdm_clk aud_tml_clk aud_infra_clk mtkaif_26m_clk top_mux_audio top_mux_aud_intbus top_syspll_d2_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d8 top_mux_aud_eng2 top_apll2_d8 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_clk26m_clk           mmc@11230000              mediatek,mt8183-mmc          *    #                                     M                     +      +            source hclk source_cg           okay            Udefault state_uhs           c   T            U        *           4          B         T         c         r                           (           V           W                            U               mmc@11240000              mediatek,mt8183-mmc          *    $                                     N                  	   +      +   (         source hclk source_cg           okay            Udefault state_uhs           c   X            Y        *           4                                              '                    Z           [         .                        dsi-phy@11e50000              mediatek,mt8183-mipi-tx         *                         B                       D            mipi_tx0_pll               \        calibration-data                a      efuse@11f10000        %    mediatek,mt8183-efuse mediatek,efuse            *                                  +      socinfo-data1@4c            *   L         socinfo-data2@60            *   `         calib@180           *                 C      calib@190           *                 \      calib@580           *     d            D         t-phy@11f40000        .    mediatek,mt8183-tphy mediatek,generic-tphy-v2                        +                                okay       usb-phy@0           *                   *         ref         D           O           okay                O      usb-phy@700         *     	             *         ref         D           okay                P         syscon@13000000           mediatek,mt8183-mfgcfg syscon           *                                    E               ]      gpu@13040000          '    mediatek,mt8183b-mali arm,mali-bifrost          *            @       $                                     _job mmu gpu             ]               E      E      E           ocore0 core1 core2               ^           -      syscon@14000000           mediatek,mt8183-mmsys syscon            *                                               _          _                 _                      .      dma-controller0@14001000              mediatek,mt8183-mdp3-rdma           *                        _                                  E               .      .              `               _              _                            mdp3-rsz0@14003000            mediatek,mt8183-mdp3-rsz            *     0                   _     0                              .         mdp3-rsz1@14004000            mediatek,mt8183-mdp3-rsz            *     @                   _     @                              .         dma-controller@14005000           mediatek,mt8183-mdp3-wrot           *     P                   _     P                  !           E               .              `                    mdp3-wdma@14006000            mediatek,mt8183-mdp3-wdma           *     `                   _     `                  "           E               .   )           `         ovl@14008000              mediatek,mt8183-disp-ovl            *                                          E               .              `               _               ovl@14009000              mediatek,mt8183-disp-ovl-2l         *                                          E               .              `              _               ovl@1400a000              mediatek,mt8183-disp-ovl-2l         *                                          E               .              `              _               rdma@1400b000             mediatek,mt8183-disp-rdma           *                                          E               .              `                         _               rdma@1400c000             mediatek,mt8183-disp-rdma           *                                          E               .              `                         _               color@1400e000        6    mediatek,mt8183-disp-color mediatek,mt8173-disp-color           *                                          E               .              _               ccorr@1400f000            mediatek,mt8183-disp-ccorr          *                                          E               .              _               aal@14010000              mediatek,mt8183-disp-aal            *                                          E               .              _                gamma@14011000            mediatek,mt8183-disp-gamma          *                                         E               .              _               dither@14012000           mediatek,mt8183-disp-dither         *                                          E               .              _                dsi@14014000              mediatek,mt8183-dsi         *    @                                     E               .      .       a         engine digital hs              .              a        dphy          	  disabled       port       endpoint                dpi@14015000              mediatek,mt8183-dpi         *    P                                     E               .   "   .   !   B            pixel engine pll          	  disabled       port       endpoint                mutex@14016000            mediatek,mt8183-disp-mutex          *    `                                     E                            _     `          larb@14017000             mediatek,mt8183-smi-larb            *    p                   /            .      .              E            apb smi             6      smi@14019000              mediatek,mt8183-smi-common          *                         .       .       .      .            apb smi gals0 gals1            E               /      mdp3-ccorr@1401c000           mediatek,mt8183-mdp3-ccorr          *                       _                       1            .   +      syscon@15020000           mediatek,mt8183-imgsys syscon           *                                    1      larb@15021000             mediatek,mt8183-smi-larb            *                       /            1   	   1   	   .            apb smi gals               E   	            ;      larb@1502f000             mediatek,mt8183-smi-larb            *                       /            1      1      .   	         apb smi gals               E   	            8      syscon@16000000           mediatek,mt8183-vdecsys syscon          *                                     c      video-codec@16020000              mediatek,mt8183-vcodec-dec          *                                                      0            @            P            h            p            x                          (  misc ld top cm ad av pp hwd hwq hwb hwg                         8     `       `   !   `   "   `   #   `   $   `   %   `   &           b           c           E   
            c             vdec          larb@16010000             mediatek,mt8183-smi-larb            *                        /            c       c            apb smi            E   
            7      syscon@17000000           mediatek,mt8183-vencsys syscon          *                                     d      larb@17010000             mediatek,mt8183-smi-larb            *                        /            d       d             apb smi            E               :      jpeg-encoder@17030000         +    mediatek,mt8183-jpgenc mediatek,mtk-jpgenc          *                                          `      `              E               d            jpgenc        syscon@19000000            mediatek,mt8183-ipu_conn syscon         *                                     2      syscon@19010000           mediatek,mt8183-ipu_adl syscon          *                              syscon@19180000       !    mediatek,mt8183-ipu_core0 syscon            *                              syscon@19280000       !    mediatek,mt8183-ipu_core1 syscon            *    (                          syscon@1a000000           mediatek,mt8183-camsys syscon           *                                     0      larb@1a001000             mediatek,mt8183-smi-larb            *                        /            0       0       .            apb smi gals               E               <      larb@1a002000             mediatek,mt8183-smi-larb            *                         /            0   	   0   	   .            apb smi gals               E               9         thermal-zones      cpu-thermal            d        )          7   e            G     trips      trip-point0         Y 	        e           Epassive       trip-point1         Y 8        e           Epassive             f      cpu-crit            Y 8        e        	   Ecritical             cooling-maps       map0            p   f      0  u                             map1            p   f      0  u                                   soc-thermal         )                     7   e           G     trips      trip-alert          Y L        e           Epassive       trip-crit           Y         e        	   Ecritical                gpu-thermal         )                     7   e           G     trips      trip-alert          Y L        e           Epassive       trip-crit           Y         e        	   Ecritical                md1-thermal         )                     7   e           G     trips      trip-alert          Y L        e           Epassive       trip-crit           Y         e        	   Ecritical                cpu-little-thermal          )                     7   e           G     trips      trip-alert          Y L        e           Epassive       trip-crit           Y         e        	   Ecritical                cpu-big-thermal         )                     7   e           G     trips      trip-alert          Y L        e           Epassive       trip-crit           Y         e        	   Ecritical                tsabb-thermal           )                     7   e           G     trips      trip-alert          Y L        e           Epassive       trip-crit           Y         e        	   Ecritical                   memory@40000000         memory          *    @                chosen          serial0:921600n8          reserved-memory                      +               memory@50000000           shared-dma-pool         *    P                              4         thermal-sensor            murata,ncp03wf104            w@         p                       A             	compatible interrupt-parent #address-cells #size-cells model chassis-type i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 i2c7 i2c8 i2c9 i2c10 i2c11 ovl0 ovl-2l0 ovl-2l1 rdma0 rdma1 serial0 opp-shared phandle opp-hz opp-microvolt required-opps clocks clock-names operating-points-v2 proc-supply cpu device_type reg enable-method capacity-dmips-mhz cpu-idle-states dynamic-power-coefficient i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells mediatek,cci entry-method local-timer-stop arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts #clock-cells clock-div clock-mult clock-output-names clock-frequency ranges status #interrupt-cells interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux mediatek,pull-up-adv bias-disable input-enable bias-pull-up bias-pull-down drive-strength output-high #power-domain-cells mediatek,infracfg domain-supply mediatek,smi interrupts-extended #io-channel-cells mediatek,dmic-mode regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-enable-ramp-delay regulator-always-on regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread linux,keycodes wakeup-source memory-region mediatek,larbs #iommu-cells #mbox-cells pinctrl-names pinctrl-0 mediatek,pad-select #thermal-sensor-cells resets mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names power-domains #pwm-cells phys mediatek,syscon-wakeup reset-names pinctrl-1 bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply assigned-clocks assigned-clock-parents non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 cap-sdio-irq no-mmc keep-power-in-suspend #phy-cells mediatek,discth interrupt-names power-domain-names mali-supply mboxes mediatek,gce-client-reg mediatek,gce-events iommus #dma-cells mediatek,rdma-fifo-size phy-names mediatek,scp mediatek,vdecsys polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution stdout-path no-map pullup-uv pullup-ohm pulldown-ohm io-channels 