  D   8  L   (                                           -    google,pico-sku2 google,pico mediatek,mt8183                                     +            7Google pico6 board           =convertible    aliases          J/soc/i2c@11007000            O/soc/i2c@11011000            T/soc/i2c@11009000            Y/soc/i2c@1100f000            ^/soc/i2c@11008000            c/soc/i2c@11016000            h/soc/i2c@11005000            m/soc/i2c@1101a000            r/soc/i2c@1101b000            w/soc/i2c@11014000            |/soc/i2c@11015000            /soc/i2c@11017000            /soc/ovl@14008000            /soc/ovl@14009000            /soc/ovl@1400a000            /soc/rdma@1400b000           /soc/rdma@1400c000           /soc/serial@11002000             /soc/mmc@11230000            /soc/mmc@11240000         opp-table-cluster0            operating-points-v2                           opp0-793000000               /D8@          	                  opp0-910000000               6=          
}                  opp0-1014000000              <pi          
                  opp0-1131000000              Ci                            opp0-1248000000              Jb           5                   opp0-1326000000              O	'          ~>                  opp0-1417000000              Tu@          P                  opp0-1508000000              YA           A            	      opp0-1586000000              ^p          6            
      opp0-1625000000              `ۈ@          
                  opp0-1677000000              c@          5                  opp0-1716000000              fH           f                  opp0-1781000000              j'@                            opp0-1846000000              n          B@                  opp0-1924000000              r                             opp0-1989000000              v@                               opp-table-cluster1            operating-points-v2                       $   opp1-793000000               /D8@          
`                  opp1-910000000               6=                            opp1-1014000000              <pi          q                  opp1-1131000000              Ci          X                  opp1-1248000000              Jb           5                   opp1-1326000000              O	'                            opp1-1417000000              Tu@          P                  opp1-1508000000              YA           Y            	      opp1-1586000000              ^p                      
      opp1-1625000000              `ۈ@          t                  opp1-1677000000              c@          5                  opp1-1716000000              fH           ~                  opp1-1781000000              j'@                            opp1-1846000000              n          B@                  opp1-1924000000              r                             opp1-1989000000              v@                               opp-table-cci             operating-points-v2                          opp-273000000                E@          	                  opp-338000000                %x          
}                  opp-403000000                J          
                  opp-463000000                                            opp-546000000                 L          5                   opp-624000000                %1|           ~>                  opp-689000000                )N@          P                  opp-767000000                -}          A            	      opp-845000000                2]@          6            
      opp-871000000                3g          
                  opp-923000000                7          5                  opp-962000000                9V          f                  opp-1027000000               =6                            opp-1092000000               A           B@                  opp-1144000000               D0                             opp-1196000000               GI                                cci           mediatek,mt8183-cci                               cci intermediate                                      "      cpus                         +       cpu-map    cluster0       core0           $         core1           $         core2           $         core3           $            cluster1       core0           $         core1           $         core2           $         core3           $               cpu@0           (cpu           arm,cortex-a53          4            8psci            F          Y                                     cpu intermediate                        i   T                      @                                 @                      !                      "                             cpu@1           (cpu           arm,cortex-a53          4           8psci            F          Y                                     cpu intermediate                        i   T                      @                                 @                      !                      "                             cpu@2           (cpu           arm,cortex-a53          4           8psci            F          Y                                     cpu intermediate                        i   T                      @                                 @                      !                      "                             cpu@3           (cpu           arm,cortex-a53          4           8psci            F          Y                                     cpu intermediate                        i   T                      @                                 @                      !                      "                             cpu@100         (cpu           arm,cortex-a73          4           8psci            F           Y      #                              cpu intermediate               $        i                         @                                 @                      %                      "           &                  cpu@101         (cpu           arm,cortex-a73          4          8psci            F           Y      #                              cpu intermediate               $        i                         @                                 @                      %                      "           &                  cpu@102         (cpu           arm,cortex-a73          4          8psci            F           Y      #                              cpu intermediate               $        i                         @                                 @                      %                      "           &                  cpu@103         (cpu           arm,cortex-a73          4          8psci            F           Y      #                              cpu intermediate               $        i                         @                                 @                      %                      "           &                  idle-states         psci       cpu-sleep             arm,idle-state                   &          =           N           ^                     cluster-sleep-0           arm,idle-state                   &         =           N          ^                    cluster-sleep-1           arm,idle-state                   &         =           N          ^              #         l2-cache0             cache           o                         @                    {            !      l2-cache1             cache           o                         @                    {            %         opp-table-0           operating-points-v2                       y   opp-300000000                           	h      opp-320000000                           	      opp-340000000                C           	<      opp-360000000                u*           	Ҧ      opp-380000000                W           	      opp-400000000                ׄ           
z      opp-420000000                           
      opp-460000000                k           
L      opp-500000000                e           
}      opp-540000000                 /           
`      opp-580000000                "           
4      opp-620000000                $s                 opp-653000000                &@          YF      opp-698000000                )                opp-743000000                ,IG                opp-800000000                /                    pmu-a53           arm,cortex-a53-pmu              '                    (      pmu-a73           arm,cortex-a73-pmu              '                    )      psci              arm,psci-1.0            ?smc       fixed-factor-clock-13m            fixed-factor-clock                          *                              clk13m              ;      oscillator            fixed-clock                             clk26m              *      timer             arm,armv8-timer             '      @                                               
             soc                      +             simple-bus              efuse@8000000         %    mediatek,mt8183-efuse mediatek,efuse            4                                   +         	  disabled          interrupt-controller@c000000              arm,gic-v3                         '               P  4                                @              A             B                        	                            '   ppi-partitions     interrupt-partition-0           -                        (      interrupt-partition-1           -                        )            syscon@c530000            mediatek,mt8183-mcucfg syscon           4    S                                      interrupt-controller@c530a80          .    mediatek,mt8183-sysirq mediatek,mt6577-sysirq                                   '        4    S
       P                  cpu-debug@d410000         &    arm,coresight-cpu-debug arm,primecell           4    A                     +   .      	   apb_pclk            $         cpu-debug@d510000         &    arm,coresight-cpu-debug arm,primecell           4    Q                     +   .      	   apb_pclk            $         cpu-debug@d610000         &    arm,coresight-cpu-debug arm,primecell           4    a                     +   .      	   apb_pclk            $         cpu-debug@d710000         &    arm,coresight-cpu-debug arm,primecell           4    q                     +   .      	   apb_pclk            $         cpu-debug@d810000         &    arm,coresight-cpu-debug arm,primecell           4                         +   .      	   apb_pclk            $         cpu-debug@d910000         &    arm,coresight-cpu-debug arm,primecell           4                         +   .      	   apb_pclk            $         cpu-debug@da10000         &    arm,coresight-cpu-debug arm,primecell           4                         +   .      	   apb_pclk            $         cpu-debug@db10000         &    arm,coresight-cpu-debug arm,primecell           4                         +   .      	   apb_pclk            $         syscon@10000000            mediatek,mt8183-topckgen syscon         4                                           syscon@10001000            mediatek,mt8183-infracfg syscon         4                                6               +      syscon@10003000           mediatek,mt8183-pericfg syscon          4     0                               i      pinctrl@10005000              mediatek,mt8183-pinctrl         4     P                                                                                                                                   D  Ciocfg0 iocfg1 iocfg2 iocfg3 iocfg4 iocfg5 iocfg6 iocfg7 iocfg8 eint          M        ]           i   ,                                                        uSPI_AP_EC_CS_L SPI_AP_EC_MOSI SPI_AP_EC_CLK I2S3_DO USB_PD_INT_ODL     IT6505_HPD_L I2S3_TDM_D3 SOC_I2C6_1V8_SCL SOC_I2C6_1V8_SDA DPI_D0 DPI_D1 DPI_D2 DPI_D3 DPI_D4 DPI_D5 DPI_D6 DPI_D7 DPI_D8 DPI_D9 DPI_D10 DPI_D11 DPI_HSYNC DPI_VSYNC DPI_DE DPI_CK AP_MSDC1_CLK AP_MSDC1_DAT3 AP_MSDC1_CMD AP_MSDC1_DAT0 AP_MSDC1_DAT2 AP_MSDC1_DAT1       OTG_EN DRVBUS DISP_PWM DSI_TE LCM_RST_1V8 AP_CTS_WIFI_RTS AP_RTS_WIFI_CTS SOC_I2C5_1V8_SCL SOC_I2C5_1V8_SDA SOC_I2C3_1V8_SCL SOC_I2C3_1V8_SDA                              SOC_I2C1_1V8_SDA SOC_I2C0_1V8_SDA SOC_I2C0_1V8_SCL SOC_I2C1_1V8_SCL AP_SPI_H1_MISO AP_SPI_H1_CS_L AP_SPI_H1_MOSI AP_SPI_H1_CLK I2S5_BCK I2S5_LRCK I2S5_DO BOOTBLOCK_EN_L MT8183_KPCOL0 SPI_AP_EC_MISO UART_DBG_TX_AP_RX UART_AP_TX_DBG_RX I2S2_MCK I2S2_BCK CLK_5M_WCAM CLK_2M_UCAM I2S2_LRCK I2S2_DI SOC_I2C2_1V8_SCL SOC_I2C2_1V8_SDA SOC_I2C4_1V8_SCL SOC_I2C4_1V8_SDA  SCL8 SDA8 FCAM_PWDN_L                          I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC       AP_FLASH_WP_L EC_AP_INT_ODL IT6505_INT_ODL H1_INT_OD_L        AP_SPI_FLASH_MISO AP_SPI_FLASH_CS_L AP_SPI_FLASH_MOSI AP_SPI_FLASH_CLK DA7219_IRQ                                        ,   audiopins                  pins-bus          D    a  b  e  f    Y  Z  [                           audiotdmouton                  pins-bus                        
                    audiotdmoutoff                 pins-bus                             
                                       ec-ap-int-odl               a   pins1                                         h1-int-od-l             V   pins1                                i2c0                G   pins-bus              R  S                    i2c1                _   pins-bus              Q  T                    i2c2                S   pins-bus              g  h                  i2c3                ]   pins-bus              2  3                    i2c4                I   pins-bus              i  j                  i2c5                c   pins-bus              0  1                    i2c6                F   pins-bus                                  mmc0-pins-default               m   pins-cmd-dat          $    {    }    ~        z                                     pins-clk              |                      
      pins-rst                                             mmc0-pins-uhs               n   pins-cmd-dat          $    {    }    ~        z                                     pins-clk              |                      
      pins-ds                                 
      pins-rst                                             mmc1-pins-default               q   pins-cmd-dat                   "  !                      
                 pins-clk                                  
                    mmc1-pins-uhs               r   pins-cmd-dat                   "  !                                 
      pins-clk                                    
                  panel-pins-default     panel-reset           -                            pwm0-pin-default                \   pins1                                      pins2             +         scp             :   pins-scp-uart             n  p         spi0                U   pins-spi              U  V   W  X                  spi1                ^   pins-spi                                      spi2                `   pins-spi                                  pins-spi-mi           ^                     spi3                b   pins-spi                                      spi4                e   pins-spi                                      spi5                f   pins-spi                                      uart0-pins-default              C   pins-rx           _                        pins-tx           `         uart1-pins-default              D   pins-rx           y                        pins-tx           s      pins-rts              /      pins-cts              .                  uart1-pins-sleep                E   pins-rx           y                         pins-tx           s      pins-rts              /      pins-cts              .                  wifi-pins-pwrseq                   pins-wifi-enable                                 wifi-pins-wakeup                   pins-wifi-wakeup              q                   pp1000-mipibrdg-en                 pins1             6                   pp1800-mipibrdg-en                 pins1             $                   pp3300-panel-pins                  panel-3v3-enable              #                   ppvarp-lcd-en      pins1             B                   ppvarn-lcd-en      pins1                                anx7625-pins                J   pins1             -   I                pins2                                         touchscreen-pins                H   touch-int-odl                                      touch-rst-l                              trackpad-pins               T   trackpad-int                                          pp3300-mipibrdg-en                 pins1             %                   volume-button-pins                 voldn-btn-odl                                      volup-btn-odl                                         ts3a227e_pins               d   pins1                                         bt-pins-wakeup                 piins-bt-wakeup           *                   bt-pins-reset               v   pins-bt-reset             x                      syscon@10006000       )    mediatek,mt8183-scpsys syscon simple-mfd            4     `           power-controller          !    mediatek,mt8183-power-controller                         +                           [   power-domain@0          4                      +   /   +   7         audio audio1 audio2                   power-domain@1          4           (   +                  power-domain@2          4                        +                       :   -   power-domain@3          4                        +                       :   .   power-domain@4          4                     power-domain@5          4                     power-domain@6          4           (   +                        power-domain@7          4         X            /       /      /      /      /      /      /      /      /      /   	      5   mm mm-0 mm-1 mm-2 mm-3 mm-4 mm-5 mm-6 mm-7 mm-8 mm-9            (   +        H   0                     +                  power-domain@8          4         @            1       1   	   1      1      1      1      1         .   cam cam-0 cam-1 cam-2 cam-3 cam-4 cam-5 cam-6           (   +        H   0                  power-domain@9          4   	               "   2   	   2            isp isp-0 isp-1         (   +        H   0                  power-domain@10         4   
        H   0                  power-domain@11         4           H   0                  power-domain@12         4         @         &      #   3       3      3      3      3      3         -   vpu vpu1 vpu-0 vpu-1 vpu-2 vpu-3 vpu-4 vpu-5            (   +        H   0                     +                  power-domain@13         4                  $         vpu2            (   +                  power-domain@14         4                  %         vpu3            (   +                              watchdog@10007000             mediatek,mt8183-wdt         4     p                6               k      syscon@1000c000       "    mediatek,mt8183-apmixedsys syscon           4                                    X      pwrap@1000d000            mediatek,mt8183-pwrap           4                     Cpwrap                                    )   +         	   spi wrap       pmic              mediatek,mt6358                             U   ,         adc           mediatek,mt6358-auxadc          i         audio-codec           mediatek,mt6358-sound           {               4      regulators            mediatek,mt6358-regulator              5           5           5           5           5           5           5           5        &   5        :   5        N   5        ^   5        n   6        ~   7           8           8           8   buck_vdram1         vdram1                     L          0                     .        B                   7      buck_vcore          vcore                                j                    .        B             buck_vpa            vpa                    7          P                   B             buck_vproc11            vproc11                              j                    .        B                   &      buck_vproc12            vproc12                              j                    .        B                         buck_vgpu           vgpu                                 j                   B               Z   -        q             .      buck_vs2            vs2                    L          0                     .            8      buck_vmodem         vmodem                               j                   .        B             buck_vs1            vs1          B@         '{l          0                     .            6      ldo_vdram2          vdram2           	'         w@                   .      ldo_vsim1           vsim1            )2         )2                ldo_vibr            vibr             O         2Z           <      ldo_vrf12           vrf12            O         O           x      ldo_vio18           vio18            w@         w@          
         .            p      ldo_vusb            vusb             -         /M`                   .            j      ldo_vcamio          vcamio           w@         w@          E      ldo_vcamd           vcamd                     w@          E      ldo_vcn18           vcn18            w@         w@                ldo_vfe28           vfe28            *         *                ldo_vsram_proc11            vsram_proc11                                 j                    .      ldo_vcn28           vcn28            *         *                ldo_vsram_others            vsram_others                                 j                    .      ldo_vsram_gpu         
  vsram_gpu            P         B@          j                   Z   .        q             -      ldo_vxo22           vxo22            !         !           x         .      ldo_vefuse          vefuse                                    ldo_vaux18          vaux18           w@         w@                ldo_vmch            vmch             ,@          2Z           <      ldo_vbif28          vbif28           *         *                ldo_vsram_proc12            vsram_proc12                                 j                    .      ldo_vcama1          vcama1           w@         -          E      ldo_vemc            vemc             ,@          2Z           <            o      ldo_vio28           vio28            *         *                ldo_va12            va12             O         O                   .      ldo_vrf18           vrf18            w@         w@           x      ldo_vcn33           vcn33            2Z         5g                ldo_vcama2          vcama2           w@         -          E      ldo_vmc         vmc          w@         2Z           <      ldo_vldo28          vldo28           *         -                ldo_vaud28          vaud28           *         *                      4      ldo_vsim2           vsim2            )2         )2                   rtc           mediatek,mt6358-rtc       keys              mediatek,mt6358-keys       power              t               home               f               keyboard@10010000         .    mediatek,mt8183-keypad mediatek,mt6779-keypad           4                                           *         kpd       	  disabled          scp@10500000              mediatek,mt8183-scp          4    P             \             	  Csram cfg                                  +            main               9        okay            mediatek/mt8183/scp.img         default            :            ~   cros-ec-rpmsg             google,cros-ec-rpmsg            cros-ec-rpmsg            timer@10017000        ,    mediatek,mt8183-timer mediatek,mt6765-timer         4    p                                      ;      iommu@10205000            mediatek,mt8183-m4u         4     P                                     <   =   >   ?   @   A   B                       {      mailbox@10238000              mediatek,mt8183-gce         4    #       @                                          +            gce             z      auxadc@11001000       .    mediatek,mt8183-auxadc mediatek,mt8173-auxadc           4                         +   #         main            i           okay                W      serial@11002000       *    mediatek,mt8183-uart mediatek,mt6577-uart           4                             [               *   +         	   baud bus            okay            default            C      serial@11003000       *    mediatek,mt8183-uart mediatek,mt6577-uart           4     0                    *   +         	   baud bus            okay            default sleep              D           E        U          \      ,   y         serial@11004000       *    mediatek,mt8183-uart mediatek,mt6577-uart           4     @                       ]               *   +         	   baud bus          	  disabled          i2c@11005000              mediatek,mt8183-i2c          4     P                                    W               +   W   +   *      	   main dma                                    +            okay            default            F               i2c@11007000              mediatek,mt8183-i2c          4     p                                    Q               +   
   +   *      	   main dma                                    +            okay            default            G            touchscreen@10            elan,ekth3500           4           default            H        U   ,              %   ,               i2c@11008000              mediatek,mt8183-i2c          4                                         R               +      +   *   +   G         main dma arb                                    +            okay            default            I            anx7625@58            analogix,anx7625            4   X        default            J        1   ,   -            %   ,   I            >   K        K   L        X   M   ports                        +       port@0          4       endpoint            e   N            }         port@1          4      endpoint            e   O            R            aux-bus    panel         
    edp-panel           u   P           Q   port       endpoint            e   R            O                     i2c@11009000              mediatek,mt8183-i2c          4                                        S               +      +   *   +   I         main dma arb                                    +            okay            default            S                   a   trackpad@15           elan,ekth3000           4           default            T        U   ,                     trackpad@2c           hid-over-i2c            4   ,                    default            T        U   ,                        spi@1100a000              mediatek,mt8183-spi                      +            4                            x                  6         +            parent-clk sel-clk spi-clk          okay            default            U                       ,   V      tpm@0             google,cr50         4             B@        default            V        U   ,               thermal-sensor@1100b000                      mediatek,mt8183-thermal         4                         +   	   +   #         therm auxadc               +                   L              W           X        %   Y        1calibration-data                      svs@1100bc00              mediatek,mt8183-svs         4                                           +   	         main            %   Z   Y      (  1svs-calibration-data t-calibration-data       pwm@1100e000              mediatek,mt8183-disp-pwm            4                                       B   [           P                     +   5         main mm         okay            default            \                  pwm@11006000              mediatek,mt8183-pwm         4     `                P         0      +      +      +      +      +      +            top main pwm1 pwm2 pwm3 pwm4          i2c@1100f000              mediatek,mt8183-i2c          4                                         T               +      +   *      	   main dma                                    +            okay            default            ]               spi@11010000              mediatek,mt8183-spi                      +            4                            |                  6         +   8         parent-clk sel-clk spi-clk          okay            default            ^               flash@0           winbond,w25q64dw jedec,spi-nor          4            }x@         i2c@11011000              mediatek,mt8183-i2c          4                                       U               +   9   +   *      	   main dma                                    +            okay            default            _               spi@11012000              mediatek,mt8183-spi                      +            4                                              6         +   ;         parent-clk sel-clk spi-clk          okay            default            `               cros-ec@0             google,cros-ec-spi          4             -        U   ,              default            a            i2c-tunnel            google,cros-ec-i2c-tunnel           [                         +       sbs-battery@b             sbs,sbs-battery         4           m                       extcon0           google,extcon-usbc-cros-ec                    typec             google,cros-ec-typec                         +       connector@0           usb-c-connector         4            dual            host            sink             keyboard-controller           google,cros-ec-keyb                                     D  	
  ; < = > ? @ A	 B	 C  D  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      pwm           google,cros-ec-pwm          P         	  disabled                spi@11013000              mediatek,mt8183-spi                      +            4    0                                         6         +   <         parent-clk sel-clk spi-clk        	  disabled            default            b                  i2c@11014000              mediatek,mt8183-i2c          4    @                                                  +   H   +   *   +   G         main dma arb                                    +          	  disabled          i2c@11015000              mediatek,mt8183-i2c          4    P                                                   +   J   +   *   +   I         main dma arb                                    +          	  disabled          i2c@11016000              mediatek,mt8183-i2c          4    `                                    V               +   D   +   *   +   E         main dma arb                                    +            okay            default            c            ts3a227e@3b         default            d          ti,ts3a227e         4   ;        U   ,              okay                         i2c@11017000              mediatek,mt8183-i2c          4    p                                                  +   F   +   *   +   E         main dma arb                                    +          	  disabled          spi@11018000              mediatek,mt8183-spi                      +            4                                             6         +   K         parent-clk sel-clk spi-clk        	  disabled            default            e                  spi@11019000              mediatek,mt8183-spi                      +            4                                             6         +   L         parent-clk sel-clk spi-clk        	  disabled            default            f                  i2c@1101a000              mediatek,mt8183-i2c          4                                       X               +   b   +   *      	   main dma                                    +          	  disabled          i2c@1101b000              mediatek,mt8183-i2c          4                                        Y               +   c   +   *      	   main dma                                    +          	  disabled          usb@11201000          #    mediatek,mt8183-mtu3 mediatek,mtu3           4            .      >              	  Cmac ippc                   H           	   g      h               +   =   +   Z         sys_ck ref_ck           	   i      e                     +                    okay            	3host                     	;   j   usb@11200000          '    mediatek,mt8183-xhci mediatek,mtk-xhci          4                      Cmac                I               +   =   +   Z         sys_ck ref_ck           okay                         +            	;   j   hub@1             usb5e3,610          4               audio-controller@11220000              mediatek,mt8183-audiosys syscon         4    "                                l   mt8183-afe-pcm            mediatek,mt8183-audio                                k         	  	Iaudiosys            B   [         D      l      l      l      l      l      l      l      l      l      l      l      l   
   l   	   l      l       +   /   +   7                  0            H            L            K            O      t      u      v      w      x      y      z      {      |      }      ~         *     w   aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adc_adda6_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_i2s1_bclk_sw aud_i2s2_bclk_sw aud_i2s3_bclk_sw aud_i2s4_bclk_sw aud_tdm_clk aud_tml_clk aud_infra_clk mtkaif_26m_clk top_mux_audio top_mux_aud_intbus top_syspll_d2_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d8 top_mux_aud_eng2 top_apll2_d8 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_clk26m_clk                       mmc@11230000              mediatek,mt8183-mmc          4    #                                     M                     +      +            source hclk source_cg           okay            default state_uhs              m           n        	U                     	_         	q         	         	         	         	        	 (        	   o        	   p        	              	      U         	      mmc@11240000              mediatek,mt8183-mmc          4    $                                     N                  	   +      +   (         source hclk source_cg           okay            default state_uhs              q           r        	   s        	   t        
   u        	U                     
         
'         
4         
B                  
X         	         
e         	        	      	        	      V                     +       qca-wifi@1            qcom,ath10k         4         bluetooth@2         4             mediatek,mt7921s-bluetooth          default            v        %   ,   x            dsi-phy@11e50000              mediatek,mt8183-mipi-tx         4                         X                       
l            mipi_tx0_pll            %   w        1calibration-data            okay                |      efuse@11f10000        %    mediatek,mt8183-efuse mediatek,efuse            4                                  +      socinfo-data1@4c            4   L         socinfo-data2@60            4   `         calib@180           4                 Y      calib@190           4                 w      calib@580           4     d            Z         t-phy@11f40000        .    mediatek,mt8183-tphy mediatek,generic-tphy-v2                        +                                okay       usb-phy@0           4                   *         ref         
l           
w           okay                g      usb-phy@700         4     	             *         ref         
l           okay                h         syscon@13000000           mediatek,mt8183-mfgcfg syscon           4                                 B   [               x      gpu@13040000          '    mediatek,mt8183b-mali arm,mali-bifrost          4            @       $                                     
job mmu gpu             x            B   [      [      [           
core0 core1 core2              y        
   .      syscon@14000000           mediatek,mt8183-mmsys syscon            4                                 6           
   z          z              
   z                      /      dma-controller0@14001000              mediatek,mt8183-mdp3-rdma           4                     
   z                 
              B   [               /      /           
   {            
   z              z                   
         mdp3-rsz0@14003000            mediatek,mt8183-mdp3-rsz            4     0                
   z     0            
                  /         mdp3-rsz1@14004000            mediatek,mt8183-mdp3-rsz            4     @                
   z     @            
                  /         dma-controller@14005000           mediatek,mt8183-mdp3-wrot           4     P                
   z     P            
      !        B   [               /           
   {           
         mdp3-wdma@14006000            mediatek,mt8183-mdp3-wdma           4     `                
   z     `            
      "        B   [               /   )        
   {         ovl@14008000              mediatek,mt8183-disp-ovl            4                                       B   [               /           
   {            
   z               ovl@14009000              mediatek,mt8183-disp-ovl-2l         4                                       B   [               /           
   {           
   z               ovl@1400a000              mediatek,mt8183-disp-ovl-2l         4                                       B   [               /           
   {           
   z               rdma@1400b000             mediatek,mt8183-disp-rdma           4                                       B   [               /           
   {           
           
   z               rdma@1400c000             mediatek,mt8183-disp-rdma           4                                       B   [               /           
   {           
           
   z               color@1400e000        6    mediatek,mt8183-disp-color mediatek,mt8173-disp-color           4                                       B   [               /           
   z               ccorr@1400f000            mediatek,mt8183-disp-ccorr          4                                       B   [               /           
   z               aal@14010000              mediatek,mt8183-disp-aal            4                                       B   [               /           
   z                gamma@14011000            mediatek,mt8183-disp-gamma          4                                      B   [               /           
   z               dither@14012000           mediatek,mt8183-disp-dither         4                                       B   [               /           
   z                dsi@14014000              mediatek,mt8183-dsi         4    @                                  B   [               /      /       |         engine digital hs              /           	   |        dphy            okay                         +       port       endpoint            e   }            N            dpi@14015000              mediatek,mt8183-dpi         4    P                                  B   [               /   "   /   !   X            pixel engine pll          	  disabled       port       endpoint                mutex@14016000            mediatek,mt8183-disp-mutex          4    `                                  B   [           
              
   z     `          larb@14017000             mediatek,mt8183-smi-larb            4    p                H   0            /      /           B   [            apb smi             <      smi@14019000              mediatek,mt8183-smi-common          4                         /       /       /      /            apb smi gals0 gals1         B   [               0      mdp3-ccorr@1401c000           mediatek,mt8183-mdp3-ccorr          4                    
   z                 
      1            /   +      syscon@15020000           mediatek,mt8183-imgsys syscon           4                                    2      larb@15021000             mediatek,mt8183-smi-larb            4                    H   0            2   	   2   	   /            apb smi gals            B   [   	            A      larb@1502f000             mediatek,mt8183-smi-larb            4                    H   0            2      2      /   	         apb smi gals            B   [   	            >      syscon@16000000           mediatek,mt8183-vdecsys syscon          4                                           video-codec@16020000              mediatek,mt8183-vcodec-dec          4                                                      0            @            P            h            p            x                          (  Cmisc ld top cm ad av pp hwd hwq hwb hwg                         8  
   {       {   !   {   "   {   #   {   $   {   %   {   &           ~        *           B   [   
                         vdec          larb@16010000             mediatek,mt8183-smi-larb            4                     H   0                               apb smi         B   [   
            =      syscon@17000000           mediatek,mt8183-vencsys syscon          4                                           larb@17010000             mediatek,mt8183-smi-larb            4                     H   0                                apb smi         B   [               @      jpeg-encoder@17030000         +    mediatek,mt8183-jpgenc mediatek,mtk-jpgenc          4                                       
   {      {           B   [                           jpgenc        syscon@19000000            mediatek,mt8183-ipu_conn syscon         4                                     3      syscon@19010000           mediatek,mt8183-ipu_adl syscon          4                              syscon@19180000       !    mediatek,mt8183-ipu_core0 syscon            4                              syscon@19280000       !    mediatek,mt8183-ipu_core1 syscon            4    (                          syscon@1a000000           mediatek,mt8183-camsys syscon           4                                     1      larb@1a001000             mediatek,mt8183-smi-larb            4                     H   0            1       1       /            apb smi gals            B   [               B      larb@1a002000             mediatek,mt8183-smi-larb            4                      H   0            1   	   1   	   /            apb smi gals            B   [               ?         thermal-zones      cpu-thermal         ;   d        Q          _               o     trips      trip-point0          	                   Epassive       trip-point1          8                   Epassive                   cpu-crit             8                	   Ecritical             cooling-maps       map0                     0                               map1                     0                                     soc-thermal         Q          ;           _              o     trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                gpu-thermal         Q          ;           _              o     trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                md1-thermal         Q          ;           _              o     trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                cpu-little-thermal          Q          ;           _              o     trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                cpu-big-thermal         Q          ;           _              o     trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                tsabb-thermal           Q          ;           _              o     trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                tboard1         Q          ;            _         tboard2         Q          ;            _            chosen          serial0:115200n8          backlight_lcd0            pwm-backlight                            u   5        1   ,                                         @        okay                Q      memory@40000000         (memory          4    @                oscillator1           fixed-clock                                clk32k        regulator0            regulator-fixed         it6505_pp18            ,                        $         regulator1            regulator-fixed         lcd_pp3300           2Z         2Z         .         /      regulator3            regulator-fixed         mmc1_power          $               s      regulator4            regulator-fixed         mmc1_io         $               t      regulator5            regulator-fixed         pp1800_alw           .         /         w@         w@        $   5                  regulator6            regulator-fixed         pp3300_alw           .         /         2Z         2Z        $   5                  regulator-vsys            regulator-fixed         vsys             .         /            5      reserved-memory                      +               memory@50000000           shared-dma-pool         4    P                  A            9         mt8183-sound            H         '  default aud_tdm_out_on aud_tdm_out_off                                Z           okay            d         (    mediatek,mt8183_mt6358_ts3a227_max98357       bt-sco            linux,bt-sco          wifi-pwrseq           mmc-pwrseq-simple           default                    %   ,              {   2            u      wifi-wakeup       
    gpio-keys           default               event-wowlan            Wake on WiFi            +   ,   q                                thermal-sensor1           generic-adc-thermal                        W            sensor-channel          x              '  .  :    N   l  a    u0      7  @      {  P  (      `      a p  / $   8    L    _    s       y (   h    Z 8   N    C H   ;                  thermal-sensor2           generic-adc-thermal                        W           sensor-channel          x              '  .  :    N   l  a    u0      7  @      {  P  (      `      a p  / $   8    L    _    s       y (   h    Z 8   N    C H   ;                  pp1000-mipibrdg           regulator-fixed         pp1000_mipibrdg          B@         B@        default                              /           ,   6            $               K      pp1800-mipibrdg           regulator-fixed         pp1800_mipibrdg         default                              /           ,   $            $               L      pp3300-panel              regulator-fixed         pp3300_panel            default                              /           ,   #            $               P      pp3300-mipibrdg           regulator-fixed         pp3300_mipibrdg         default                              /           ,   %            $               M      volume-buttons        
    gpio-keys           default               button-volume-down          Volume Down            r           d        +   ,            button-volume-up          
  Volume Up              s           d        +   ,               max98357a             maxim,max98357a            ,             bt-wakeup         
    gpio-keys           default               event-wobt          Wake on BT          +   ,   *                                    	compatible interrupt-parent #address-cells #size-cells model chassis-type i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 i2c7 i2c8 i2c9 i2c10 i2c11 ovl0 ovl-2l0 ovl-2l1 rdma0 rdma1 serial0 mmc0 mmc1 opp-shared phandle opp-hz opp-microvolt required-opps clocks clock-names operating-points-v2 proc-supply cpu device_type reg enable-method capacity-dmips-mhz cpu-idle-states dynamic-power-coefficient i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells mediatek,cci entry-method local-timer-stop arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts #clock-cells clock-div clock-mult clock-output-names clock-frequency ranges status #interrupt-cells interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux drive-strength input-enable bias-pull-down bias-pull-up mediatek,pull-up-adv bias-disable mediatek,pull-down-adv output-low output-high #power-domain-cells mediatek,infracfg domain-supply mediatek,smi interrupts-extended #io-channel-cells mediatek,dmic-mode Avdd-supply vsys-ldo1-supply vsys-ldo2-supply vsys-ldo3-supply vsys-vcore-supply vsys-vdram1-supply vsys-vgpu-supply vsys-vmodem-supply vsys-vpa-supply vsys-vproc11-supply vsys-vproc12-supply vsys-vs1-supply vsys-vs2-supply vs1-ldo1-supply vs2-ldo1-supply vs2-ldo2-supply vs2-ldo3-supply vs2-ldo4-supply regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-enable-ramp-delay regulator-always-on regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread linux,keycodes wakeup-source memory-region firmware-name pinctrl-names pinctrl-0 mediatek,rpmsg-name mediatek,larbs #iommu-cells #mbox-cells pinctrl-1 reset-gpios enable-gpios vdd10-supply vdd18-supply vdd33-supply remote-endpoint power-supply backlight i2c-scl-internal-delay-ns hid-descr-addr mediatek,pad-select cs-gpios spi-max-frequency #thermal-sensor-cells resets mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names power-domains #pwm-cells google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count google,usb-port-id power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap phys mediatek,syscon-wakeup dr_mode vusb33-supply reset-names bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply assigned-clocks assigned-clock-parents non-removable mmc-pwrseq cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 keep-power-in-suspend cap-sdio-irq no-mmc #phy-cells mediatek,discth interrupt-names power-domain-names mali-supply mboxes mediatek,gce-client-reg mediatek,gce-events iommus #dma-cells mediatek,rdma-fifo-size phy-names mediatek,scp mediatek,vdecsys polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution stdout-path pwms brightness-levels num-interpolated-steps default-brightness-level gpio enable-active-high vin-supply regulator-boot-on no-map mediatek,platform pinctrl-2 mediatek,headset-codec post-power-on-delay-ms label linux,code io-channels io-channel-names temperature-lookup-table debounce-interval sdmode-gpios 