     8  $   (            	]                               (    mediatek,mt8183-pumpkin mediatek,mt8183                                  +            7Pumpkin MT8183     aliases          =/soc/i2c@11007000            B/soc/i2c@11011000            G/soc/i2c@11009000            L/soc/i2c@1100f000            Q/soc/i2c@11008000            V/soc/i2c@11016000            [/soc/i2c@11005000            `/soc/i2c@1101a000            e/soc/i2c@1101b000            j/soc/i2c@11014000            o/soc/i2c@11015000            u/soc/i2c@11017000            {/soc/ovl@14008000            /soc/ovl@14009000            /soc/ovl@1400a000            /soc/rdma@1400b000           /soc/rdma@1400c000           /soc/serial@11002000          opp-table-cluster0            operating-points-v2                          opp0-793000000               /D8@          	                  opp0-910000000               6=          
}                  opp0-1014000000              <pi          
                  opp0-1131000000              Ci                            opp0-1248000000              Jb           5                   opp0-1326000000              O	'          ~>                  opp0-1417000000              Tu@          P                  opp0-1508000000              YA           A            	      opp0-1586000000              ^p          6            
      opp0-1625000000              `ۈ@          
                  opp0-1677000000              c@          5                  opp0-1716000000              fH           f                  opp0-1781000000              j'@                            opp0-1846000000              n          B@                  opp0-1924000000              r                             opp0-1989000000              v@                               opp-table-cluster1            operating-points-v2                       $   opp1-793000000               /D8@          
`                  opp1-910000000               6=                            opp1-1014000000              <pi          q                  opp1-1131000000              Ci          X                  opp1-1248000000              Jb           5                   opp1-1326000000              O	'                            opp1-1417000000              Tu@          P                  opp1-1508000000              YA           Y            	      opp1-1586000000              ^p                      
      opp1-1625000000              `ۈ@          t                  opp1-1677000000              c@          5                  opp1-1716000000              fH           ~                  opp1-1781000000              j'@                            opp1-1846000000              n          B@                  opp1-1924000000              r                             opp1-1989000000              v@                               opp-table-cci             operating-points-v2                          opp-273000000                E@          	                  opp-338000000                %x          
}                  opp-403000000                J          
                  opp-463000000                                            opp-546000000                 L          5                   opp-624000000                %1|           ~>                  opp-689000000                )N@          P                  opp-767000000                -}          A            	      opp-845000000                2]@          6            
      opp-871000000                3g          
                  opp-923000000                7          5                  opp-962000000                9V          f                  opp-1027000000               =6                            opp-1092000000               A           B@                  opp-1144000000               D0                             opp-1196000000               GI                                cci           mediatek,mt8183-cci                               cci intermediate                            !      cpus                         +       cpu-map    cluster0       core0                    core1                    core2                    core3                       cluster1       core0                    core1                    core2                    core3                          cpu@0           cpu           arm,cortex-a53                      psci            #          6                                     cpu intermediate                        F   T        `           m   @                                 @                                             !           "                  cpu@1           cpu           arm,cortex-a53                     psci            #          6                                     cpu intermediate                        F   T        `           m   @                                 @                                             !           "                  cpu@2           cpu           arm,cortex-a53                     psci            #          6                                     cpu intermediate                        F   T        `           m   @                                 @                                             !           "                  cpu@3           cpu           arm,cortex-a53                     psci            #          6                                     cpu intermediate                        F   T        `           m   @                                 @                                             !           "                  cpu@100         cpu           arm,cortex-a73                     psci            #           6      #                              cpu intermediate                $        F           `           m   @                                 @                      %                      !           &                  cpu@101         cpu           arm,cortex-a73                    psci            #           6      #                              cpu intermediate                $        F           `           m   @                                 @                      %                      !           &                  cpu@102         cpu           arm,cortex-a73                    psci            #           6      #                              cpu intermediate                $        F           `           m   @                                 @                      %                      !           &                  cpu@103         cpu           arm,cortex-a73                    psci            #           6      #                              cpu intermediate                $        F           `           m   @                                 @                      %                      !           &                  idle-states         psci       cpu-sleep             arm,idle-state                             &           7           G                     cluster-sleep-0           arm,idle-state                            &           7          G                    cluster-sleep-1           arm,idle-state                            &           7          G              #         l2-cache0             cache           X           b           o   @                    d                   l2-cache1             cache           X           b           o   @                    d            %         opp-table-0           operating-points-v2                       _   opp-300000000                           	h      opp-320000000                           	      opp-340000000                C           	<      opp-360000000                u*           	Ҧ      opp-380000000                W           	      opp-400000000                ׄ           
z      opp-420000000                           
      opp-460000000                k           
L      opp-500000000                e           
}      opp-540000000                 /           
`      opp-580000000                "           
4      opp-620000000                $s                 opp-653000000                &@          YF      opp-698000000                )                opp-743000000                ,IG                opp-800000000                /                    pmu-a53           arm,cortex-a53-pmu              '        r            (      pmu-a73           arm,cortex-a73-pmu              '        r            )      psci              arm,psci-1.0            smc       fixed-factor-clock-13m            fixed-factor-clock          }                *                              clk13m              6      oscillator            fixed-clock         }                    clk26m              *      timer             arm,armv8-timer             '      @  r                                             
             soc                      +             simple-bus              efuse@8000000         %    mediatek,mt8183-efuse mediatek,efuse                                               +         	  disabled          interrupt-controller@c000000              arm,gic-v3                         '               P                                  @              A             B                  r      	                   '   ppi-partitions     interrupt-partition-0                                   (      interrupt-partition-1                                   )            syscon@c530000            mediatek,mt8183-mcucfg syscon               S                 }                     interrupt-controller@c530a80          .    mediatek,mt8183-sysirq mediatek,mt6577-sysirq                                   '            S
       P                  cpu-debug@d410000         &    arm,coresight-cpu-debug arm,primecell               A                     +   .      	   apb_pclk                     cpu-debug@d510000         &    arm,coresight-cpu-debug arm,primecell               Q                     +   .      	   apb_pclk                     cpu-debug@d610000         &    arm,coresight-cpu-debug arm,primecell               a                     +   .      	   apb_pclk                     cpu-debug@d710000         &    arm,coresight-cpu-debug arm,primecell               q                     +   .      	   apb_pclk                     cpu-debug@d810000         &    arm,coresight-cpu-debug arm,primecell                                    +   .      	   apb_pclk                     cpu-debug@d910000         &    arm,coresight-cpu-debug arm,primecell                                    +   .      	   apb_pclk                     cpu-debug@da10000         &    arm,coresight-cpu-debug arm,primecell                                    +   .      	   apb_pclk                     cpu-debug@db10000         &    arm,coresight-cpu-debug arm,primecell                                    +   .      	   apb_pclk                     syscon@10000000            mediatek,mt8183-topckgen syscon                               }                     syscon@10001000            mediatek,mt8183-infracfg syscon                              }                          +      syscon@10003000           mediatek,mt8183-pericfg syscon               0                }               R      pinctrl@10005000              mediatek,mt8183-pinctrl              P                                                                                                                                   D  iocfg0 iocfg1 iocfg2 iocfg3 iocfg4 iocfg5 iocfg6 iocfg7 iocfg8 eint                  &           2   ,                            r                                 ,   i2c0                E   pins_i2c            >  R  S        E            i2c1                N   pins_i2c            >  Q  T        E            i2c2                G   pins_i2c            >  g  h        E            i2c3                M   pins_i2c            >  2  3        E            i2c4                F   pins_i2c            >  i  j        E            i2c5                O   pins_i2c            >  0  1        E            i2c6                >   pins_cmd_dat            >  q  r        E            keyboard                4   pins_keyboard           >  [  \  ]         mmc0-pins-default               U   pins_cmd_dat          $  >  {    }    ~        z         Z        g           E         pins_clk            >  |        g           v   
      pins_rst            >          g           v            mmc0-pins-uhs               V   pins_cmd_dat          $  >  {    }    ~        z         Z        g           E         pins_clk            >  |        g           v   
      pins_ds         >          g           v   
      pins_rst            >          g           E            mmc1-pins-default               Y   pins_cmd_dat            >       "  !           Z        E   
      pins_clk            >           Z        v   
      pins_pmu            >                     mmc1-pins-uhs               Z   pins_cmd_dat            >       "  !          g            Z        E   
      pins_clk            >          g           v   
         Z         ite-pins                ?   pins-irq            >            Z               pins-rst            >                     dpi-func-pins               c   pins-dpi          L  >    .  /                                         dpi-idle-pins               d   pins-idle         L  >     .   /                                                             syscon@10006000       )    mediatek,mt8183-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8183-power-controller                         +                           L   power-domain@0                                +   /   +   7         audio audio1 audio2                   power-domain@1                        +                  power-domain@2                                  +                  power-domain@3                                  +                          -   power-domain@4                               power-domain@5                               power-domain@6                        +                        power-domain@7                   X            .       .      .      .      .      .      .      .      .      .   	      5   mm mm-0 mm-1 mm-2 mm-3 mm-4 mm-5 mm-6 mm-7 mm-8 mm-9               +           /                     +                  power-domain@8                   @            0       0   	   0      0      0      0      0         .   cam cam-0 cam-1 cam-2 cam-3 cam-4 cam-5 cam-6              +           /                  power-domain@9             	               "   1   	   1            isp isp-0 isp-1            +           /                  power-domain@10            
           /                  power-domain@11                       /                  power-domain@12                  @         &      #   2       2      2      2      2      2         -   vpu vpu1 vpu-0 vpu-1 vpu-2 vpu-3 vpu-4 vpu-5               +           /                     +                  power-domain@13                           $         vpu2               +                  power-domain@14                           %         vpu3               +                              watchdog@10007000             mediatek,mt8183-wdt              p                               S      syscon@1000c000       "    mediatek,mt8183-apmixedsys syscon                                }               I      pwrap@1000d000            mediatek,mt8183-pwrap                                pwrap           r                         )   +         	   spi wrap       pmic              mediatek,mt6358                                ,         adc           mediatek,mt6358-auxadc                   audio-codec           mediatek,mt6358-sound                     regulators            mediatek,mt6358-regulator      buck_vdram1          vdram1          /          G L        _  0        t                                  buck_vcore           vcore           /          G         _  j        t                                 buck_vpa             vpa         /          G 7        _  P        t                        buck_vproc11             vproc11         /          G         _  j        t                                       &      buck_vproc12             vproc12         /          G         _  j        t                                       "      buck_vgpu            vgpu            / 	h        G         _  j        t                             3                     -      buck_vs2             vs2         /          G L        _  0        t                   buck_vmodem          vmodem          /          G         _  j        t                                buck_vs1             vs1         / B@        G '{l        _  0        t                   ldo_vdram2           vdram2          / 	'        G w@        t        ldo_vsim1            vsim1           /         G /M`        t        ldo_vibr             vibr            / O        G 2Z        t   <      ldo_vrf12            vrf12           / O        G O        t   x            B      ldo_vio18            vio18           / w@        G w@        t  
                     X      ldo_vusb             vusb            / -        G /M`        t                 ldo_vcamio           vcamio          / w@        G w@        t  E      ldo_vcamd            vcamd           /         G w@        t  E      ldo_vcn18            vcn18           / w@        G w@        t              A      ldo_vfe28            vfe28           / *        G *        t        ldo_vsram_proc11             vsram_proc11            /          G         _  j        t                  ldo_vcn28            vcn28           / *        G *        t        ldo_vsram_others             vsram_others            /          G         _  j        t                  ldo_vsram_gpu         
   vsram_gpu           / P        G B@        _  j        t              -                     3      ldo_vxo22            vxo22           / !        G !        t   x               ldo_vefuse           vefuse          /         G         t        ldo_vaux18           vaux18          / w@        G w@        t        ldo_vmch             vmch            / ,@         G 2Z        t   <            [      ldo_vbif28           vbif28          / *        G *        t        ldo_vsram_proc12             vsram_proc12            /          G         _  j        t                  ldo_vcama1           vcama1          / w@        G -        t  E      ldo_vemc             vemc            / ,@         G 2Z        t   <            W      ldo_vio28            vio28           / *        G *        t        ldo_va12             va12            / O        G O        t                 ldo_vrf18            vrf18           / w@        G w@        t   x      ldo_vcn33            vcn33           / 2Z        G 5g        t              @      ldo_vcama2           vcama2          / w@        G -        t  E      ldo_vmc          vmc         / w@        G 2Z        t   <            \      ldo_vldo28           vldo28          / *        G -        t        ldo_vaud28           vaud28          / *        G *        t        ldo_vsim2            vsim2           /         G /M`        t           rtc           mediatek,mt6358-rtc       keys              mediatek,mt6358-keys       power              t               home               f               keyboard@10010000         .    mediatek,mt8183-keypad mediatek,mt6779-keypad                                r                      *         kpd         okay            default            4        %   r  s        2           B           U            g         scp@10500000              mediatek,mt8183-scp              P             \             	  sram cfg            r                      +            main               5        okay                f      timer@10017000        ,    mediatek,mt8183-timer mediatek,mt6765-timer             p                r                      6      iommu@10205000            mediatek,mt8183-m4u              P                r                     7   8   9   :   ;   <   =                       a      mailbox@10238000              mediatek,mt8183-gce             #       @         r                                 +            gce             `      auxadc@11001000       .    mediatek,mt8183-auxadc mediatek,mt8173-auxadc                                    +   #         main                       okay                H      serial@11002000       *    mediatek,mt8183-uart mediatek,mt6577-uart                                 r       [               *   +         	   baud bus            okay          serial@11003000       *    mediatek,mt8183-uart mediatek,mt6577-uart                0                r       \               *   +         	   baud bus          	  disabled          serial@11004000       *    mediatek,mt8183-uart mediatek,mt6577-uart                @                r       ]               *   +         	   baud bus          	  disabled          i2c@11005000              mediatek,mt8183-i2c               P                             r       W               +   W   +   *      	   main dma                                    +            okay            default            >            hdmitx@4c             ite,it66121            L        default            ?           ,                  ,        r                 @           A           B   ports                        +       port@0                 endpoint                          C            e         port@1                endpoint               D            k                  i2c@11007000              mediatek,mt8183-i2c               p                             r       Q               +   
   +   *      	   main dma                                    +            okay            default            E               i2c@11008000              mediatek,mt8183-i2c                                            r       R               +      +   *   +   G         main dma arb                                    +            okay            default            F               i2c@11009000              mediatek,mt8183-i2c                                           r       S               +      +   *   +   I         main dma arb                                    +            okay            default            G               spi@1100a000              mediatek,mt8183-spi                      +                                 r       x                  6         +            parent-clk sel-clk spi-clk        	  disabled          thermal-sensor@1100b000                      mediatek,mt8183-thermal                                  +   	   +   #         therm auxadc               +            r       L              H        /   I        C   J        Ocalibration-data                i      svs@1100bc00              mediatek,mt8183-svs                              r                      +   	         main            C   K   J      (  Osvs-calibration-data t-calibration-data       pwm@1100e000              mediatek,mt8183-disp-pwm                                 r                  `   L           n                     +   5         main mm       pwm@11006000              mediatek,mt8183-pwm              `                n         0      +      +      +      +      +      +            top main pwm1 pwm2 pwm3 pwm4          i2c@1100f000              mediatek,mt8183-i2c                                            r       T               +      +   *      	   main dma                                    +            okay            default            M               spi@11010000              mediatek,mt8183-spi                      +                                 r       |                  6         +   8         parent-clk sel-clk spi-clk        	  disabled          i2c@11011000              mediatek,mt8183-i2c                                          r       U               +   9   +   *      	   main dma                                    +            okay            default            N               spi@11012000              mediatek,mt8183-spi                      +                                 r                         6         +   ;         parent-clk sel-clk spi-clk        	  disabled          spi@11013000              mediatek,mt8183-spi                      +                0                r                         6         +   <         parent-clk sel-clk spi-clk        	  disabled          i2c@11014000              mediatek,mt8183-i2c              @                            r                      +   H   +   *   +   G         main dma arb                                    +          	  disabled          i2c@11015000              mediatek,mt8183-i2c              P                             r                      +   J   +   *   +   I         main dma arb                                    +          	  disabled          i2c@11016000              mediatek,mt8183-i2c              `                             r       V               +   D   +   *   +   E         main dma arb                                    +            okay            default            O               i2c@11017000              mediatek,mt8183-i2c              p                            r                      +   F   +   *   +   E         main dma arb                                    +          	  disabled          spi@11018000              mediatek,mt8183-spi                      +                                r                         6         +   K         parent-clk sel-clk spi-clk        	  disabled          spi@11019000              mediatek,mt8183-spi                      +                                r                         6         +   L         parent-clk sel-clk spi-clk        	  disabled          i2c@1101a000              mediatek,mt8183-i2c                                          r       X               +   b   +   *      	   main dma                                    +          	  disabled          i2c@1101b000              mediatek,mt8183-i2c                                           r       Y               +   c   +   *      	   main dma                                    +          	  disabled          usb@11201000          #    mediatek,mt8183-mtu3 mediatek,mtu3                       .      >              	  mac ippc            r       H           y   P      Q               +   =   +   Z         sys_ck ref_ck           ~   R      e                     +                  	  disabled       usb@11200000          '    mediatek,mt8183-xhci mediatek,mtk-xhci                                mac         r       I               +   =   +   Z         sys_ck ref_ck         	  disabled             audio-controller@11220000              mediatek,mt8183-audiosys syscon             "                 }               T   mt8183-afe-pcm            mediatek,mt8183-audio           r                     S         	  audiosys            `   L         D      T      T      T      T      T      T      T      T      T      T      T      T   
   T   	   T      T       +   /   +   7                  0            H            L            K            O      t      u      v      w      x      y      z      {      |      }      ~         *     w   aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adc_adda6_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_i2s1_bclk_sw aud_i2s2_bclk_sw aud_i2s3_bclk_sw aud_i2s4_bclk_sw aud_tdm_clk aud_tml_clk aud_infra_clk mtkaif_26m_clk top_mux_audio top_mux_aud_intbus top_syspll_d2_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d8 top_mux_aud_eng2 top_apll2_d8 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_clk26m_clk           mmc@11230000              mediatek,mt8183-mmc              #                              r       M                     +      +            source hclk source_cg           okay            default state_uhs              U           V                                                                                   (           W        #   X        0              @      U         W      mmc@11240000              mediatek,mt8183-mmc              $                              r       N                  	   +      +   (         source hclk source_cg           okay            default state_uhs              Y           Z                             e         v                                               [        #   \                           W      dsi-phy@11e50000              mediatek,mt8183-mipi-tx                                  I           }                        mipi_tx0_pll            C   ]        Ocalibration-data                b      efuse@11f10000        %    mediatek,mt8183-efuse mediatek,efuse                                              +      socinfo-data1@4c               L         socinfo-data2@60               `         calib@180                            J      calib@190                            ]      calib@580                d            K         t-phy@11f40000        .    mediatek,mt8183-tphy mediatek,generic-tphy-v2                        +                                okay       usb-phy@0                              *         ref                               okay                P      usb-phy@700              	             *         ref                    okay                Q         syscon@13000000           mediatek,mt8183-mfgcfg syscon                                 }           `   L               ^      gpu@13040000          '    mediatek,mt8183b-mali arm,mali-bifrost                      @       $  r                                   job mmu gpu             ^            `   L      L      L           core0 core1 core2               _           -      syscon@14000000           mediatek,mt8183-mmsys syscon                                  }                         `          `                 `                      .      dma-controller0@14001000              mediatek,mt8183-mdp3-rdma                                   `                 $              `   L               .      .           8   a               `              `                   ?         mdp3-rsz0@14003000            mediatek,mt8183-mdp3-rsz                 0                   `     0            $                  .         mdp3-rsz1@14004000            mediatek,mt8183-mdp3-rsz                 @                   `     @            $                  .         dma-controller@14005000           mediatek,mt8183-mdp3-wrot                P                   `     P            $      !        `   L               .           8   a           ?         mdp3-wdma@14006000            mediatek,mt8183-mdp3-wdma                `                   `     `            $      "        `   L               .   )        8   a         ovl@14008000              mediatek,mt8183-disp-ovl                                 r                  `   L               .           8   a               `               ovl@14009000              mediatek,mt8183-disp-ovl-2l                              r                  `   L               .           8   a              `               ovl@1400a000              mediatek,mt8183-disp-ovl-2l                              r                  `   L               .           8   a              `               rdma@1400b000             mediatek,mt8183-disp-rdma                                r                  `   L               .           8   a           J              `               rdma@1400c000             mediatek,mt8183-disp-rdma                                r                  `   L               .           8   a           J              `               color@1400e000        6    mediatek,mt8183-disp-color mediatek,mt8173-disp-color                                r                  `   L               .              `               ccorr@1400f000            mediatek,mt8183-disp-ccorr                               r                  `   L               .              `               aal@14010000              mediatek,mt8183-disp-aal                                 r                  `   L               .              `                gamma@14011000            mediatek,mt8183-disp-gamma                              r                  `   L               .              `               dither@14012000           mediatek,mt8183-disp-dither                              r                  `   L               .              `                dsi@14014000              mediatek,mt8183-dsi             @                r                  `   L               .      .       b         engine digital hs              .           y   b        bdphy          	  disabled       port       endpoint                dpi@14015000              mediatek,mt8183-dpi             P                r                  `   L               .   "   .   !   I            pixel engine pll            okay            default sleep              c           d   port       endpoint               e            C            mutex@14016000            mediatek,mt8183-disp-mutex              `                r                  `   L           $                 `     `          larb@14017000             mediatek,mt8183-smi-larb                p                   /            .      .           `   L            apb smi             7      smi@14019000              mediatek,mt8183-smi-common                                   .       .       .      .            apb smi gals0 gals1         `   L               /      mdp3-ccorr@1401c000           mediatek,mt8183-mdp3-ccorr                                 `                 $      1            .   +      syscon@15020000           mediatek,mt8183-imgsys syscon                                }               1      larb@15021000             mediatek,mt8183-smi-larb                                   /            1   	   1   	   .            apb smi gals            `   L   	            <      larb@1502f000             mediatek,mt8183-smi-larb                                   /            1      1      .   	         apb smi gals            `   L   	            9      syscon@16000000           mediatek,mt8183-vdecsys syscon                                }               g      video-codec@16020000              mediatek,mt8183-vcodec-dec                                                                0            @            P            h            p            x                          (  misc ld top cm ad av pp hwd hwq hwb hwg         r                8  8   a       a   !   a   "   a   #   a   $   a   %   a   &        l   f        y   g        `   L   
            g             vdec          larb@16010000             mediatek,mt8183-smi-larb                                    /            g       g            apb smi         `   L   
            8      syscon@17000000           mediatek,mt8183-vencsys syscon                                }               h      larb@17010000             mediatek,mt8183-smi-larb                                    /            h       h             apb smi         `   L               ;      jpeg-encoder@17030000         +    mediatek,mt8183-jpgenc mediatek,mtk-jpgenc                               r                  8   a      a           `   L               h            jpgenc        syscon@19000000            mediatek,mt8183-ipu_conn syscon                               }               2      syscon@19010000           mediatek,mt8183-ipu_adl syscon                               }         syscon@19180000       !    mediatek,mt8183-ipu_core0 syscon                                 }         syscon@19280000       !    mediatek,mt8183-ipu_core1 syscon                (                 }         syscon@1a000000           mediatek,mt8183-camsys syscon                                 }               0      larb@1a001000             mediatek,mt8183-smi-larb                                    /            0       0       .            apb smi gals            `   L               =      larb@1a002000             mediatek,mt8183-smi-larb                                     /            0   	   0   	   .            apb smi gals            `   L               :         thermal-zones      cpu-thermal            d                     i                 trips      trip-point0          	                  passive       trip-point1          8                  passive             j      cpu-crit             8                	  critical             cooling-maps       map0               j      0                               map1               j      0                                     soc-thermal                                 i                trips      trip-alert           L                  passive       trip-crit                            	  critical                gpu-thermal                                 i                trips      trip-alert           L                  passive       trip-crit                            	  critical                md1-thermal                                 i                trips      trip-alert           L                  passive       trip-crit                            	  critical                cpu-little-thermal                                  i                trips      trip-alert           L                  passive       trip-crit                            	  critical                cpu-big-thermal                                 i                trips      trip-alert           L                  passive       trip-crit                            	  critical                tsabb-thermal                                   i                trips      trip-alert           L                  passive       trip-crit                            	  critical                   memory@40000000         memory              @                chosen          	serial0:921600n8          reserved-memory                      +               scp-mem@50000000              shared-dma-pool             P                  	            5         leds          
    gpio-leds      led-red         	red            ,               	!off       led-green           	green              ,               	!off          thermistor            murata,ncp03wf104           	/ w@        	9 p        	D            	Q   H          connector             hdmi-connector          	hdmi            d      port       endpoint               k            D               	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 i2c7 i2c8 i2c9 i2c10 i2c11 ovl0 ovl-2l0 ovl-2l1 rdma0 rdma1 serial0 opp-shared phandle opp-hz opp-microvolt required-opps clocks clock-names operating-points-v2 cpu device_type reg enable-method capacity-dmips-mhz cpu-idle-states dynamic-power-coefficient i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells mediatek,cci proc-supply entry-method local-timer-stop arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts #clock-cells clock-div clock-mult clock-output-names clock-frequency ranges status #interrupt-cells interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux mediatek,pull-up-adv input-enable drive-strength mediatek,pull-down-adv output-high bias-pull-up #power-domain-cells mediatek,infracfg domain-supply mediatek,smi interrupts-extended #io-channel-cells mediatek,dmic-mode regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-enable-ramp-delay regulator-always-on regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread linux,keycodes wakeup-source pinctrl-names pinctrl-0 linux,keymap keypad,num-rows keypad,num-columns debounce-delay-ms mediatek,keys-per-group memory-region mediatek,larbs #iommu-cells #mbox-cells reset-gpios vcn33-supply vcn18-supply vrf12-supply bus-width remote-endpoint #thermal-sensor-cells resets mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names power-domains #pwm-cells phys mediatek,syscon-wakeup reset-names pinctrl-1 max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply assigned-clocks assigned-clock-parents non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 cap-sdio-irq no-mmc keep-power-in-suspend #phy-cells mediatek,discth interrupt-names power-domain-names mali-supply mboxes mediatek,gce-client-reg mediatek,gce-events iommus #dma-cells mediatek,rdma-fifo-size phy-names mediatek,scp mediatek,vdecsys polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution stdout-path no-map label default-state pullup-uv pullup-ohm pulldown-ohm io-channels 