  s   8  `   (              (                             $    mediatek,mt8186-evb mediatek,mt8186                                  +         !   7MediaTek MT8186 evaluation board          	   =embedded       aliases          J/soc/ovl@14005000            O/soc/ovl@14006000            W/soc/rdma@14007000           ]/soc/rdma@1401f000           c/soc/serial@11002000          cci           mediatek,mt8186-cci          k                     rcci intermediate             ~               !      opp-table-cci             operating-points-v2                          opp-500000000                e           	'                  opp-560000000                !`           
L                  opp-612000000                $za           
                  opp-682000000                (~          
                  opp-752000000                ,Ҝ           YF            	      opp-822000000                0                      
      opp-875000000                4'p                            opp-927000000                7@          5                   opp-980000000                :i           ~>                  opp-1050000000               >                            opp-1120000000               B           )$                  opp-1155000000               D                            opp-1190000000               F          
                  opp-1260000000               K           ~                  opp-1330000000               OF0          )                  opp-1400000000               SrN           R                     opp-table-cluster0            operating-points-v2                          opp-500000000                e           	'                  opp-774000000                ."M          
L                  opp-875000000                4'p          
`                  opp-975000000                :Q                            opp-1075000000               @2          q            	      opp-1175000000               F	          X            
      opp-1275000000               K          5                   opp-1375000000               Q                            opp-1500000000               Yh/                             opp-1618000000               `p          Y                  opp-1666000000               cM$                            opp-1733000000               gK{@          H                  opp-1800000000               kI           ~                  opp-1866000000               o8                            opp-1933000000               s7=@          Z                  opp-2000000000               w5           R                     opp-table-cluster1            operating-points-v2                       "   opp-774000000                ."M          
L                  opp-835000000                1          
                  opp-919000000                6          
                  opp-1002000000               ;N          YF                  opp-1085000000               @@          X            	      opp-1169000000               E@          5             
      opp-1308000000               M                             opp-1419000000               T8          Y                  opp-1530000000               [1          t                  opp-1670000000               c-          Z                  opp-1733000000               gK{@                            opp-1796000000               k           s                  opp-1860000000               nY           Լ                  opp-1923000000               r          6d                  opp-1986000000               v_          v                  opp-2050000000               z0                               cpus                         +       cpu-map    cluster0       core0                     core1                     core2                     core3                     core4                     core5                     core6                     core7                           cpu@0            cpu           arm,cortex-a55                        psci             w5          k                      rcpu intermediate             ~               T          ~        '              7           D   @        V           c           p   @                                             !                  cpu@100          cpu           arm,cortex-a55                       psci             w5          k                      rcpu intermediate             ~               T          ~        '              7           D   @        V           c           p   @                                             !                  cpu@200          cpu           arm,cortex-a55                       psci             w5          k                      rcpu intermediate             ~               T          ~        '              7           D   @        V           c           p   @                                             !                  cpu@300          cpu           arm,cortex-a55                       psci             w5          k                      rcpu intermediate             ~               T          ~        '              7           D   @        V           c           p   @                                             !                  cpu@400          cpu           arm,cortex-a55                       psci             w5          k                      rcpu intermediate             ~               T          ~        '              7           D   @        V           c           p   @                                             !                  cpu@500          cpu           arm,cortex-a55                       psci             w5          k                      rcpu intermediate             ~               T          ~        '              7           D   @        V           c           p   @                                             !                  cpu@600          cpu           arm,cortex-a76                       psci             z0         k                     rcpu intermediate             ~   "           O                   '   #   $        7           D   @        V           c           p   @                      %                      !                  cpu@700          cpu           arm,cortex-a76                       psci             z0         k                     rcpu intermediate             ~   "           O                   '   #   $        7           D   @        V           c           p   @                      %                      !                  idle-states         psci       cpu-retention-l           arm,idle-state                                2           d          @                  cpu-retention-b           arm,idle-state                                2           d          x            #      cpu-off-l             arm,idle-state                               d                     4                  cpu-off-b             arm,idle-state                               d                     l            $         l2-cache0             cache           #           9           F   @        X              &         /                   l2-cache1             cache           #           9           F   @        X              &         /            %      l3-cache              cache           #           9           F   @        X            /            &         fixed-factor-clock-13m            fixed-factor-clock          =             k   '        J           T           _clk13m              4      oscillator-26m            fixed-clock         =                     _clk26m              '      oscillator-32k            fixed-clock         =                        _clk32k        opp-table-gpu             operating-points-v2             M   opp-299000000                `          	X        r         opp-332000000                           	h        r         opp-366000000                з          	<        r         opp-400000000                ׄ           	Ҧ        r         opp-434000000                P          
z        r         opp-484000000                A           
4N        r         opp-535000000                s          
}        r         opp-586000000                "          
`        r         opp-637000000                %@          
4        r         opp-690000000                )           @        r         opp-743000000                ,IG                  r         opp-796000000                /q                   r         opp-850000000                2          5         r         opp-900000000-3              5           P        r         opp-900000000-4              5           |        r         opp-900000000-5              5                   r          opp-950000000-3              8ـ                  r         opp-950000000-4              8ـ          Y        r         opp-950000000-5              8ـ          P        r          opp-1000000000-3                 ;           ~        r         opp-1000000000-4                 ;           t        r         opp-1000000000-5                 ;           Y        r             pmu-a55           arm,cortex-a55-pmu                                  (      pmu-a76           arm,cortex-a76-pmu                                  )      psci              arm,psci-1.0             smc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3                                                                                                 	                      ppi-partitions     interrupt-partition-0                                         (      interrupt-partition-1                             )            syscon@c53a000            mediatek,mt8186-mcusys syscon                S                =                     syscon@10000000            mediatek,mt8186-topckgen syscon                                =               +      syscon@10001000       #    mediatek,mt8186-infracfg_ao syscon                                =                          ,      syscon@10003000           mediatek,mt8186-pericfg syscon                0                    H      pinctrl@10005000              mediatek,mt8186-pinctrl               P                           "             $             &             *             ,                           B  iocfg0 iocfg_lt iocfg_lm iocfg_lb iocfg_bl iocfg_rb iocfg_rt eint                                  *                                                                 *   i2c0-default-pins               9   pins-bus                         %        2           J         i2c1-default-pins               :   pins-bus                         %        2           J         i2c2-default-pins               ;   pins-bus                         %        2           J         i2c3-default-pins               <   pins-bus                         %        2           J         i2c4-default-pins               =   pins-bus                         %        2           J         i2c5-default-pins               >   pins-bus                         %        2           J         i2c6-default-pins               ?   pins-bus                        W           2           J         i2c7-default-pins               @   pins-bus                         %        2           J         i2c8-default-pins               A   pins-bus                         %        2           J         i2c9-default-pins               E   pins-bus                        W           2           J            syscon@10006000       )    mediatek,mt8186-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8186-power-controller                         +            d               7   power-domain@0                        k   +            rmfg00                        +            d      power-domain@1                      x   ,                     +            d      power-domain@2                      d          power-domain@3                      d                power-domain@17                      k   +      +         $   rsubsys-csirx-top0 subsys-csirx-top1         d          power-domain@4                       k   +      ,   =         rsys_ck ref_ck           d          power-domain@5                       k   ,   B   ,   ?         rsys_ck ref_ck           d          power-domain@18                      k   +   /   +   >         raudioadsp subsys-adsp-bus                        +            d      power-domain@19                                  +            d      power-domain@20                     x   ,        d                power-domain@16                     x   ,        d          power-domain@6                    0   k   +   *   +   +   -   
   -      -      -         M   rdisp mdp subsys-smi-infra subsys-smi-common subsys-smi-gals subsys-smi-iommu            x   ,                     +            d      power-domain@14                      k   +   )   .             rvdec0 larb          x   ,        d          power-domain@10             
      8   k   +      +      +      +       /      +   #   +   %      6   rcam0 cam1 cam2 cam3 gals subsys-cam-tm subsys-cam-top           x   ,                     +            d      power-domain@12                     d          power-domain@11                     d             power-domain@7                       k   0      +   &         rgals subsys-img-top         x   ,                     +            d      power-domain@8                      d             power-domain@9              	      (   k   +   '   1       1      1      1         P   rsubsys-ipe-top subsys-ipe-larb0 subsys-ipe-larb1 subsys-ipe-smi subsys-ipe-gals         x   ,        d          power-domain@13                      k   +   $   2            rvenc0 subsys-larb           x   ,        d          power-domain@15                      k   +   :   3      3         %   rwpe0 subsys-larb-ck subsys-larb-pclk            x   ,        d                   watchdog@10007000             mediatek,mt8186-wdt                        p                               F      syscon@1000c000       "    mediatek,mt8186-apmixedsys syscon                                 =                     pwrap@1000d000            mediatek,mt8186-pwrap syscon                                  pwrap                                  k   ,      ,          	   rspi wrap          spmi@10015000         *    mediatek,mt8186-spmi mediatek,mt8195-spmi                 P                            pmif spmimst             k   ,      ,       +   2      (   rpmif_sys_ck pmif_tmr_ck spmimst_clk_mux            +   2           +   t                                           	  disabled          timer@10017000        ,    mediatek,mt8186-timer mediatek,mt6765-timer              p                                       k   4      mailbox@1022c000              mediatek,mt8186-gce              "       @          k   ,            rgce                                              N      scp@10500000              mediatek,mt8186-scp               P             \             	  sram cfg                                      a      adsp@10680000             mediatek,mt8186-dsp       @       h                           h            h                cfg sram sec bus             k   +   /   +   >         raudiodsp adsp_bus              +   /   +   >           '   +   E        rx tx              5   6           7         	  disabled          mailbox@10686100              mediatek,mt8186-adsp-mbox                            ha                      i                   5      mailbox@10687100              mediatek,mt8186-adsp-mbox                            hq                      j                   6      spi@11000000              mediatek,mt8186-nor                                  k   +   3   ,   O   ,   c   ,   d         rspi sf axi axi_s               +   3           +   X              %             	  disabled          adc@11001000          .    mediatek,mt8186-auxadc mediatek,mt8173-auxadc                                             k   ,   "         rmain          serial@11002000       *    mediatek,mt8186-uart mediatek,mt6577-uart                                         p                k   '   ,         	   rbaud bus            okay          serial@11003000       *    mediatek,mt8186-uart mediatek,mt6577-uart                 0                       q                k   '   ,         	   rbaud bus          	  disabled          i2c@11007000              mediatek,mt8186-i2c                p                                    i                k   8       ,   '      	   rmain dma            J                        +            okay                      default            9      i2c@11008000              mediatek,mt8186-i2c                                                    j                k   8      ,   '      	   rmain dma            J                        +            okay                      &  @        default            :      i2c@11009000              mediatek,mt8186-i2c                                                   k                k   8      ,   '      	   rmain dma            J                        +            okay                      &  '        default            ;      i2c@1100f000              mediatek,mt8186-i2c                                                   l                k   8      ,   '      	   rmain dma            J                        +            okay                      default            <      i2c@11011000              mediatek,mt8186-i2c                                                 m                k   8      ,   '      	   rmain dma            J                        +            okay                      default            =      i2c@11016000              mediatek,mt8186-i2c               `                                   b                k   8      ,   '      	   rmain dma            J                        +            okay                      default            >      i2c@1100d000              mediatek,mt8186-i2c                                                   c                k   8      ,   '      	   rmain dma            J                        +            okay                      default            ?      i2c@11004000              mediatek,mt8186-i2c                @             	                      n                k   8      ,   '      	   rmain dma            J                        +            okay                      default            @      i2c@11005000              mediatek,mt8186-i2c                P             
                     o                k   8      ,   '      	   rmain dma            J                        +            okay                      default            A      spi@1100a000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                                                         k   +   K   +      ,            rparent-clk sel-clk spi-clk        	  disabled          thermal-sensor@1100b000           mediatek,mt8186-lvts                                         c                k   ,   	        @   ,            G   B   C      $  Slvts-calib-data-1 lvts-calib-data-2         d               e      svs@1100bc00              mediatek,mt8186-svs                                                      k   ,   	         rmain            G   D   B      (  Ssvs-calibration-data t-calibration-data         @   ,           zsvs_rst       pwm@1100e000          2    mediatek,mt8186-disp-pwm mediatek,mt8183-disp-pwm                                                                   k   +      ,   4         rmain mm       	  disabled          spi@11010000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                                                         k   +   K   +      ,   8         rparent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                                                         k   +   K   +      ,   ;         rparent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                 0                                       k   +   K   +      ,   <         rparent-clk sel-clk spi-clk        	  disabled          spi@11014000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                 @                       t                k   +   K   +      ,   J         rparent-clk sel-clk spi-clk        	  disabled          spi@11015000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                 P                       u                k   +   K   +      ,   K         rparent-clk sel-clk spi-clk        	  disabled          clock-controller@11017000             mediatek,mt8186-imp_iic_wrap                 p                =               8      serial@11018000       *    mediatek,mt8186-uart mediatek,mt6577-uart                                                       k   '   ,         	   rbaud bus          	  disabled          i2c@11019000              mediatek,mt8186-i2c                                                 d                k   8   	   ,   '      	   rmain dma            J                        +            okay                      default            E      audio-controller@11210000             mediatek,mt8186-sound                !                   k   ,   ,   ,   6   +      +      +   F   +            +            +      +   e   +      +   h   +   ?   +   @   +   A   +   B   +   C   +      +      +      +      +      +   ,   '     }   raud_infra_clk mtkaif_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d2_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d8 top_mux_aud_eng2 top_apll2_d8 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s4_m_sel top_tdm_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div4 top_apll12_div_tdm top_mux_audio_h top_clk26m_clk                                             x   ,           +        @   F         	  zaudiosys          	  disabled          usb@11201000          #    mediatek,mt8186-mtu3 mediatek,mtu3                        -     >              	  mac ippc          (   k   +      ,   =   ,   3   ,      ,   >      $   rsys_ck ref_ck mcu_ck dma_ck xhci_ck               /                  G              7                        +                                H            	  disabled       usb@11200000          '    mediatek,mt8186-xhci mediatek,mtk-xhci                                 mac       (   k   +      ,   =   ,   3   ,      ,   >      $   rsys_ck ref_ck mcu_ck dma_ck xhci_ck               &             	  disabled             mmc@11230000          (    mediatek,mt8186-mmc mediatek,mt8183-mmc               #                                k   +      ,      ,   U   ,            rsource hclk source_cg crypto                   d                  +                       	  disabled          mmc@11240000          (    mediatek,mt8186-mmc mediatek,mt8183-mmc               $                               k   +      ,      ,   V         rsource hclk source_cg                  e                  +              +   o      	  disabled          usb@11281000          #    mediatek,mt8186-mtu3 mediatek,mtu3                (       -    (>              	  mac ippc          $   k   ,   B   ,   ?   ,   7   '   ,   @      $   rsys_ck ref_ck mcu_ck dma_ck xhci_ck               K                  I      J              7                        +                                H  $         	  disabled       usb@11280000          '    mediatek,mt8186-xhci mediatek,mtk-xhci               (                 mac       $   k   ,   B   ,   ?   ,   7   '   ,   @      $   rsys_ck ref_ck mcu_ck dma_ck xhci_ck               D             	  disabled             t-phy@11c80000        .    mediatek,mt8186-tphy mediatek,generic-tphy-v2                        +                                okay       usb-phy@0                            k   '         rref                        I      usb-phy@700               	          k   '         rref                        J         t-phy@11ca0000        .    mediatek,mt8186-tphy mediatek,generic-tphy-v2                        +                                okay       usb-phy@0                            k   '         rref                                   G         efuse@11cb0000        %    mediatek,mt8186-efuse mediatek,efuse                                               +      lvts1-calib@1cc                           B      lvts2-calib@2f8                           C      calib@550              P   P            D      gpu-speedbin@59c                                             L      socinfo-data1@7a0                          dsi-phy@11cc0000              mediatek,mt8183-mipi-tx                                k   '        =                        _mipi_tx0_pll          	  disabled                Q      clock-controller@13000000             mediatek,mt8186-mfgsys                                 =               K      gpu@13040000          &    mediatek,mt8186-mali arm,mali-bifrost                        @          k   K          0                                                 job mmu gpu            7      7           core0 core1                    G   L      
  Sspeed-bin            ~   M           O      	  disabled                j      syscon@14000000           mediatek,mt8186-mmsys syscon                                   =                         N          N              $   N                      -      mutex@14001000            mediatek,mt8186-disp-mutex                                 k   -                  '               $   N                 <               7         smi@14002000              mediatek,mt8186-smi-common                                   k   -      -      -      -            rapb smi gals0 gals1            7               O      smi@14003000              mediatek,mt8186-smi-larb                  0                 k   -      -            rapb smi         P            a   O           7               R      smi@14004000              mediatek,mt8186-smi-larb                  @                 k   -      -            rapb smi         P           a   O           7               S      ovl@14005000          2    mediatek,mt8186-disp-ovl mediatek,mt8192-disp-ovl                 P                 k   -                 )               n   P           $   N     P               7         ovl@14006000          8    mediatek,mt8186-disp-ovl-2l mediatek,mt8192-disp-ovl-2l               `                 k   -                 *               n   P   !        $   N     `               7         rdma@14007000         4    mediatek,mt8186-disp-rdma mediatek,mt8183-disp-rdma               p                 k   -                 +               n   P   "        $   N     p               7         color@14009000        6    mediatek,mt8186-disp-color mediatek,mt8173-disp-color                                  k   -   	              -               $   N                    7         dpi@1400a000              mediatek,mt8186-dpi                                k   +   ;   -                  rpixel engine pll               +   ;           +   j              5                  7         	  disabled       port       endpoint                ccorr@1400b000        6    mediatek,mt8186-disp-ccorr mediatek,mt8192-disp-ccorr                                  k   -                 .               $   N                    7         aal@1400c000          2    mediatek,mt8186-disp-aal mediatek,mt8183-disp-aal                                  k   -                 0               $   N                    7         gamma@1400d000        6    mediatek,mt8186-disp-gamma mediatek,mt8183-disp-gamma                                  k   -                 1               $   N                    7         postmask@1400e000         <    mediatek,mt8186-disp-postmask mediatek,mt8192-disp-postmask                                k   -                 2               $   N                    7         dither@1400f000       8    mediatek,mt8186-disp-dither mediatek,mt8183-disp-dither                                k   -                 3               $   N                    7         dsi@14013000              mediatek,mt8186-dsi              0                 k   -      -      Q         rengine digital hs                 7                  7           @   -              Q        udphy          	  disabled       port       endpoint                iommu@14016000            mediatek,mt8186-iommu-mm                 `                 k   -            rbclk                  9             8     R   S   T   U   V   W   X   Y   Z   [   \   ]   ^   _           7                          P      rdma@1401f000         4    mediatek,mt8186-disp-rdma mediatek,mt8183-disp-rdma                               k   -                 4               n   P            $   N                    7         clock-controller@14020000             mediatek,mt8186-wpesys                                =               3      smi@14023000              mediatek,mt8186-smi-larb                 0                 k   3      3            rapb smi         P           a   O           7               W      clock-controller@15020000             mediatek,mt8186-imgsys1                               =               0      smi@1502e000              mediatek,mt8186-smi-larb                                  k   0      0             rapb smi         P   	        a   O           7               X      clock-controller@15820000             mediatek,mt8186-imgsys2                               =               `      smi@1582e000              mediatek,mt8186-smi-larb                                  k   0       `             rapb smi         P           a   O           7               Y      video-decoder@16000000            mediatek,mt8186-vcodec-dec                                                       +                      @                 n   P              a   video-codec@16025000              mediatek,mtk-vcodec-core                 P                      W             `  n   P      P      P      P      P      P      P      P      P      P      P      P             k   +   )   .      .       +   U      %   rvdec-sel vdec-soc-vdec vdec vdec-top               +   )           +   U           7            smi@1602e000              mediatek,mt8186-smi-larb                                  k   .       .             rapb smi         P           a   O           7               U      clock-controller@1602f000             mediatek,mt8186-vdecsys                              =               .      clock-controller@17000000             mediatek,mt8186-vencsys                                =               2      smi@17010000              mediatek,mt8186-smi-larb                                   k   2      2            rapb smi         P           a   O           7               V      video-encoder@17020000        6    mediatek,mt8186-vcodec-enc mediatek,mt8183-vcodec-enc                                                      H  n   P      P      P      P      P      P      P      P      P            k   2         	   rvenc_sel               +   $           +   U           7              a      jpeg-encoder@17030000         +    mediatek,mt8186-jpgenc mediatek,mtk-jpgenc                                                       k   2            rjpgenc           n   P      P      P      P              7         clock-controller@1a000000             mediatek,mt8186-camsys                                 =               /      smi@1a001000              mediatek,mt8186-smi-larb                                   k   /      /             rapb smi         P           a   O           7   
            Z      smi@1a002000              mediatek,mt8186-smi-larb                                    k   /      /            rapb smi         P           a   O           7   
            [      smi@1a00f000              mediatek,mt8186-smi-larb                                   k   /      b             rapb smi         P           a   O           7               \      smi@1a010000              mediatek,mt8186-smi-larb                                   k   /       c             rapb smi         P           a   O           7               ]      clock-controller@1a04f000             mediatek,mt8186-camsys_rawa                              =               b      clock-controller@1a06f000             mediatek,mt8186-camsys_rawb                              =               c      clock-controller@1b000000             mediatek,mt8186-mdpsys                                 =               d      smi@1b002000              mediatek,mt8186-smi-larb                                    k   d      d            rapb smi         P           a   O           7               T      clock-controller@1c000000             mediatek,mt8186-ipesys                                 =               1      smi@1c00f000              mediatek,mt8186-smi-larb                                   k   1      1            rapb smi         P           a   O           7   	            _      smi@1c10f000              mediatek,mt8186-smi-larb                                  k   1       1             rapb smi         P           a   O           7   	            ^         thermal-zones      cpu-little0-thermal                                 e       trips      trip-alert0          L                   Epassive             f      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               f      H                                cpu-little1-thermal                                 e      trips      trip-alert0          L                   Epassive             g      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               g      H                                cpu-little2-thermal                                 e      trips      trip-alert0          L                   Epassive             h      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               h      H                                cam-thermal                                 e      trips      trip-alert0          L                   Epassive       trip-alert1          s                   Ehot       trip-crit                              	   Ecritical                nna-thermal                                 e      trips      trip-alert0          L                   Epassive       trip-alert1          s                   Ehot       trip-crit                              	   Ecritical                adsp-thermal                                    e      trips      trip-alert0          L                   Epassive       trip-alert1          s                   Ehot       trip-crit                              	   Ecritical                gpu-thermal                                 e      trips      trip-alert0          L                   Epassive             i      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               i           j            cpu-big0-thermal                         d           e      trips      trip-alert0          L                   Epassive             k      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               k                          cpu-big1-thermal                         d           e      trips      trip-alert0          L                   Epassive             l      trip-alert1          s                   Ehot       trip-crit                              	   Ecritical             cooling-maps       map0               l                             chosen          serial0:921600n8          memory@40000000          memory               @                   	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl-2l0 rdma0 rdma1 serial0 clocks clock-names operating-points-v2 phandle opp-shared opp-hz opp-microvolt required-opps cpu device_type reg enable-method clock-frequency dynamic-power-coefficient capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells mediatek,cci entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-div clock-mult clock-output-names opp-supported-hw interrupts dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-disable drive-strength-microamp input-enable bias-pull-up #power-domain-cells mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents status #mbox-cells mbox-names mboxes power-domains #io-channel-cells pinctrl-names pinctrl-0 i2c-scl-internal-delay-ns resets nvmem-cells nvmem-cell-names #thermal-sensor-cells reset-names #pwm-cells mediatek,apmixedsys mediatek,topckgen phys wakeup-source mediatek,syscon-wakeup #phy-cells mediatek,discth bits interrupt-names power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus phy-names mediatek,larbs #iommu-cells mediatek,scp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path 