     8     (                                           5    google,spherion-rev4 google,spherion mediatek,mt8192                                     +            7Google Spherion (rev4)           =laptop     aliases          J/soc/ovl@14005000            O/soc/ovl@14006000            W/soc/ovl@14014000            _/soc/rdma@14007000           e/soc/rdma@14015000           k/soc/i2c@11f00000            p/soc/i2c@11d20000            u/soc/i2c@11d21000            z/soc/i2c@11cb0000            /soc/i2c@11d00000            /soc/mmc@11f60000            /soc/mmc@11f70000            /soc/serial@11002000          fixed-factor-clock-13m            fixed-factor-clock                                                            clk13m              &      oscillator0           fixed-clock                                clk26m                    oscillator1           fixed-clock                                   clk32k        cpus                         +       cpu@0            cpu           arm,cortex-a55                        psci             ec3@                                 %   @        7           D           Q   @        c           p                                                   
      cpu@100          cpu           arm,cortex-a55                       psci             ec3@                                 %   @        7           D           Q   @        c           p                                                         cpu@200          cpu           arm,cortex-a55                       psci             ec3@                                 %   @        7           D           Q   @        c           p                                                         cpu@300          cpu           arm,cortex-a55                       psci             ec3@                                 %   @        7           D           Q   @        c           p                                                         cpu@400          cpu           arm,cortex-a76                       psci             ځf                                 %   @        7           D           Q   @        c           p   	                                                      cpu@500          cpu           arm,cortex-a76                       psci             ځf                                 %   @        7           D           Q   @        c           p   	                                                      cpu@600          cpu           arm,cortex-a76                       psci             ځf                                 %   @        7           D           Q   @        c           p   	                                                      cpu@700          cpu           arm,cortex-a76                       psci             ځf                                 %   @        7           D           Q   @        c           p   	                                                      cpu-map    cluster0       core0              
      core1                    core2                    core3                    core4                    core5                    core6                    core7                          l2-cache0             cache                                 '   @        9           p                              l2-cache1             cache                                 '   @        9           p                        	      l3-cache              cache                                  '   @        9                              idle-states         psci       cpu-retention-l           arm,idle-state                             
   7                   +                    cpu-retention-b           arm,idle-state                             
   #                   +                    cpu-off-l             arm,idle-state                            
   <                   +  \                  cpu-off-b             arm,idle-state                            
   (                   +                          pmu-a55           arm,cortex-a55-pmu                      <                  pmu-a76           arm,cortex-a76-pmu                      <                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  <                                             
                 ]@      opp-table-0           operating-points-v2          G            \   opp-358000000           R    V        Y 	@*      opp-399000000           R    A        Y 	p      opp-440000000           R    9         Y 	      opp-482000000           R            Y 	Ҧ      opp-523000000           R    ,X        Y 
z      opp-564000000           R    !         Y 
4N      opp-605000000           R    $@        Y 
e"      opp-647000000           R    &o        Y 
      opp-688000000           R    )         Y 
      opp-724000000           R    +']         Y       opp-748000000           R    ,         Y @      opp-772000000           R    .         Y q      opp-795000000           R    /b        Y       opp-819000000           R    0        Y X      opp-843000000           R    2?(        Y ,      opp-866000000           R    3        Y 5          soc                      +             simple-bus          g                                k   performance-controller@11bc10             mediatek,cpufreq-hw                            0               r                     interrupt-controller@c000000              arm,gic-v3                                                                                           <      	                               ppi-partitions     interrupt-partition-0              
                           interrupt-partition-1                                               syscon@10000000            mediatek,mt8192-topckgen syscon                                                      syscon@10001000            mediatek,mt8192-infracfg syscon                                                                syscon@10003000           mediatek,mt8192-pericfg syscon                0                                3      pinctrl@10005000              mediatek,mt8192-pinctrl               P                                                                                                                                                ]  iocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint             	                   %                               <                              	  1I2S_DP_LRCK IS_DP_BCLK I2S_DP_MCLK I2S_DP_DATAOUT SAR0_INT_ODL EC_AP_INT_ODL EDPBRDG_INT_ODL DPBRDG_INT_ODL DPBRDG_PWREN DPBRDG_RST_ODL I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAIN AP_FLASH_WP_L TRACKPAD_INT_ODL EC_AP_HPD_OD SD_CD_ODL HP_INT_ODL_ALC EN_PP1000_DPBRDG AP_GPIO20 TOUCH_INT_L_1V8 UART_BT_WAKE_ODL AP_GPIO23 AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK EN_PP3300_DPBRDG_DX AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO I2S_HP_DATAOUT AP_GPIO30 I2S_SPKR_MCLK I2S_SPKR_BCLK I2S_SPKR_LRCK I2S_SPKR_DATAIN I2S_SPKR_DATAOUT AP_SPI_H1_TPM_CLK AP_SPI_H1_TPM_CS_L AP_SPI_H1_TPM_MISO AP_SPI_H1_TPM_MOSI BL_PWM EDPBRDG_PWREN EDPBRDG_RST_ODL EN_PP3300_HUB HUB_RST_L       SD_CLK SD_CMD SD_DATA3 SD_DATA0 SD_DATA2 SD_DATA1       PCIE_WAKE_ODL PCIE_RST_L PCIE_CLKREQ_ODL                        SPMI_SCL SPMI_SDA AP_GOOD UART_DBG_TX_AP_RX UART_AP_TX_DBG_RX UART_AP_TX_BT_RX UART_BT_TX_AP_RX MIPI_DPI_D0_R MIPI_DPI_D1_R MIPI_DPI_D2_R MIPI_DPI_D3_R MIPI_DPI_D4_R MIPI_DPI_D5_R MIPI_DPI_D6_R MIPI_DPI_D7_R MIPI_DPI_D8_R MIPI_DPI_D9_R MIPI_DPI_D10_R   MIPI_DPI_DE_R MIPI_DPI_D11_R MIPI_DPI_VSYNC_R MIPI_DPI_CLK_R MIPI_DPI_HSYNC_R PCM_BT_DATAIN PCM_BT_SYNC PCM_BT_DATAOUT PCM_BT_CLK AP_I2C_AUDIO_SCL AP_I2C_AUDIO_SDA SCP_I2C_SCL SCP_I2C_SDA AP_I2C_WLAN_SCL AP_I2C_WLAN_SDA AP_I2C_DPBRDG_SCL AP_I2C_DPBRDG_SDA EN_PP1800_DPBRDG_DX EN_PP3300_EDP_DX EN_PP1800_EDPBRDG_DX EN_PP1000_EDPBRDG SCP_JTAG0_TDO SCP_JTAG0_TDI SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TRSTN EN_PP3000_VMC_PMU EN_PP3300_DISPLAY_DX TOUCH_RST_L_1V8 TOUCH_REPORT_DISABLE   AP_I2C_TRACKPAD_SCL_1V8 AP_I2C_TRACKPAD_SDA_1V8 EN_PP3300_WLAN BT_KILL_L WIFI_KILL_L SET_VMC_VOLT_AT_1V8 EN_SPK AP_WARM_RST_REQ   EN_PP3000_SD_S3 AP_EDP_BKLTEN    AP_SPI_EC_CLK AP_SPI_EC_CS_L AP_SPI_EC_MISO AP_SPI_EC_MOSI AP_I2C_EDPBRDG_SCL AP_I2C_EDPBRDG_SDA MT6315_PROC_INT MT6315_GPU_INT UART_SERVO_TX_SCP_RX UART_SCP_TX_SERVO_RX BT_RTS_AP_CTS AP_RTS_BT_CTS UART_AP_WAKE_BT_ODL WLAN_ALERT_ODL EC_IN_RW_ODL H1_AP_INT_ODL            MSDC0_CMD MSDC0_DAT0 MSDC0_DAT2 MSDC0_DAT4 MSDC0_DAT6 MSDC0_DAT1 MSDC0_DAT5 MSDC0_DAT7 MSDC0_DSL MSDC0_CLK MSDC0_DAT3 MSDC0_RST_L SCP_VREQ_VAO AUD_DAT_MOSI2 AUD_NLE_MOSI1 AUD_NLE_MOSI0 AUD_DAT_MISO2 AP_I2C_SAR_SDA AP_I2C_SAR_SCL AP_I2C_PWR_SCL AP_I2C_PWR_SDA AP_I2C_TS_SCL_1V8 AP_I2C_TS_SDA_1V8 SRCLKENA0 SRCLKENA1 AP_EC_WATCHDOG_L PWRAP_SPI0_MI PWRAP_SPI0_CSN PWRAP_SPI0_MO PWRAP_SPI0_CK AP_RTC_CLK32K AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1                anx7625-default-pins                ?   pins-out            A  )   *          H      pins-in         A            S         `         aud-clk-mosi-off-pins                  pins-mosi-off           A               aud-clk-mosi-on-pins                   pins-mosi-on            A            m   
         aud-dat-miso-ch34-off-pins                 pins-miso-off           A            aud-dat-miso-ch34-on-pins                  pins-miso-on            A           aud-dat-miso-off-pins                  pins-miso-off           A               aud-dat-miso-on-pins                   pins-miso-on            A            m   
         aud-dat-miso2-off-pins                 pins-miso-off           A            aud-dat-miso2-on-pins                  pins-miso-on            A           aud-dat-mosi-ch34-off-pins                 pins-mosi-off           A            aud-dat-mosi-ch34-on-pins                  pins-mosi-on            A           aud-dat-mosi-off-pins                  pins-mosi-off           A               aud-dat-mosi-on-pins                   pins-mosi-on            A            m   
         aud-gpio-i2s3-off-pins                 pins-i2s3-off           A      !   #          aud-gpio-i2s3-on-pins                  pins-i2s3-on            A     !  #         aud-gpio-i2s8-off-pins                 pins-i2s8-off           A  
                   aud-gpio-i2s8-on-pins                  pins-i2s8-on            A  
               aud-gpio-i2s9-off-pins                 pins-i2s9-off           A            aud-gpio-i2s9-on-pins                  pins-i2s9-on            A           aud-gpio-tdm-off-pins                  pins-tdm-off            A                      aud-gpio-tdm-on-pins                   pins-tdm-on         A                  aud-nle-mosi-off-pins                  pins-nle-mosi-off           A               aud-nle-mosi-on-pins                   pins-nle-mosi-on            A             cr50-irq-default-pins               -   pins-gsc-ap-int-odl         A            S         cros-ec-irq-default-pins                +   pins-ec-ap-int-odl          A            S         `         i2c0-default-pins               Q   pins-bus            A            `           |           i2c1-default-pins               J   pins-bus            A  v  w        `           |           i2c2-default-pins               L   pins-bus            A            `            i2c3-default-pins               >   pins-bus            A                     |           i2c7-default-pins               H   pins-bus            A  |  }                 |           mmc0-default-pins               T   pins-cmd-dat          $  A                           S        m           `   e      pins-clk            A          m              f      pins-rst            A          m              e         mmc0-uhs-pins               U   pins-cmd-dat          $  A                           S        m   
        `   e      pins-clk            A          m   
           f      pins-rst            A          m              e      pins-ds         A          m   
           f         mmc1-default-pins               X   pins-cmd-dat            A  6  8  7  5  4         S        m           `   e      pins-clk            A  3        m              f      pins-insert         A            S         `         mmc1-uhs-pins               Y   pins-cmd-dat            A  6  8  7  5  4         S        m           `   e      pins-clk            A  3         S        m              f         nor-flash-default-pins              <   pins-cs-io1         A             S         `        m   
      pins-io0            A           `        m   
      pins-clk            A           S         `        m   
         pcie-default-pins               :   pins-pcie-wake          A  ?         `      pins-pcie-pereset           A  @      pins-pcie-clkreq            A  A         `      pins-wifi-kill          A                     pp1000-dpbrdg-en-pins               ~   pins-en         A            H         pp1000-mipibrdg-en-pins                pins-en         A            H         pp1800-dpbrdg-en-pins                  pins-en         A  ~          H         pp1800-mipibrd-en-pins                 pins-en         A            H         pp3300-dpbrdg-en-pins                  pins-en         A            H         pp3300-mipibrdg-en-pins                pins-en         A            H         pp3300-wlan-pins                   pins-pcie-en-pp3300-wlan            A                     pwm0-default-pins               )   pins-pwm            A  (      pins-inhibit            A                     rt1015p-default-pins                   pins            A            H         scp-pins                /   pins-vreq-vao           A           spi1-default-pins               *   pins-cs-mosi-clk            A                     pins-miso           A                    spi5-default-pins               ,   pins-bus            A  &  %   '  $                  trackpad-default-pins               M   pins-int-n          A            S        `   g         touchscreen-default-pins                R   pins-irq            A            S         `      pins-reset          A                  pins-report-sw          A            H         vow-clk-miso-off-pins                  pins-miso-off           A            vow-clk-miso-on-pins                   pins-miso-on            A           vow-dat-miso-off-pins                  pins-miso-off           A            vow-dat-miso-on-pins                   pins-miso-on            A              syscon@10006000       )    mediatek,mt8192-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8192-power-controller                         +                           7   power-domain@0                                    :      /        audio audio1 audio2                              power-domain@1                                     conn                                 power-domain@2                                           mfg alt                      +                             power-domain@3                                              +                             power-domain@4                                power-domain@5                                power-domain@6                                power-domain@7                                power-domain@8                                      power-domain@9              	      (                                       !  disp disp-0 disp-1 disp-2 disp-3                                    +                  power-domain@10             
      (                                          ipe ipe-0 ipe-1 ipe-2 ipe-3                              power-domain@11                                                 isp isp-0 isp-1                              power-domain@12                                                 isp2 isp2-0 isp2-1                               power-domain@13                                        
  mdp mdp-0                                power-domain@14                            3              venc venc-0                              power-domain@15                             4                              vdec vdec-0 vdec-1 vdec-2                                   +                  power-domain@16                         !      !      !            vdec2-0 vdec2-1 vdec2-2                      power-domain@17                   (         
   "       "      "      "           cam cam-0 cam-1 cam-2 cam-3                                 +                  power-domain@18                         #            cam_rawa-0                    power-domain@19                         $            cam_rawb-0                    power-domain@20                         %            cam_rawc-0                                watchdog@10007000             mediatek,mt8192-wdt               p                               6      syscon@1000c000       "    mediatek,mt8192-apmixedsys syscon                                                 2      timer@10017000        ,    mediatek,mt8192-timer mediatek,mt6765-timer              p                <                          &      pwrap@10026000            mediatek,mt6873-pwrap                `                pwrap           <                                          	  spi wrap                                   pmic              mediatek,mt6359                             #            adc           mediatek,mt6359-auxadc          7         mt6359codec         I           \           p         regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !                           buck_vgpu11         vgpu11                    7                                                      buck_vmodem         vmodem                              *                 buck_vpu            vpu                   7                                             buck_vcore          vcore                                                                   buck_vs2            vs2          5          j                                        buck_vpa            vpa                    7          ,      buck_vproc2         vproc2                    7          L                                   buck_vproc1         vproc1                    7          L                                   buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                                     ldo_vaud18          vaud18           w@         w@                 ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z      ldo_vrf12           vrf12                                     ldo_vusb            vusb             -         -                         ldo_vsram_proc2         vsram_proc2                              L                          ldo_vio18           vio18                                                    K      ldo_vcamio          vcamio                          ldo_vcn18           vcn18            w@         w@                 ldo_vfe28           vfe28            *         *           x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@                          ldo_vsram_others            vsram_others             q         5                                          7  '                  ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !               ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *                 ldo_vio28           vio28            *         2Z               ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z            V      ldo_vcn33_2_bt          vcn33_2_bt           *         5g      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                         ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                                 *                 ldo_vufs            vufs                                           W      ldo_vm18            vm18                                     ldo_vbbck           vbbck                     O      ldo_vsram_proc1         vsram_proc1                              L                          ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt6873-spmi                  p                            pmif spmimst                                8      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux                                                  +       pmic@6            mediatek,mt6315-regulator                      regulators     vbuck1          Vbcpu                     7                                            vbuck3          Vlcpu                     7                                                  pmic@7            mediatek,mt6315-regulator                      regulators     vbuck1          Vgpu                      5                                                  7  '                           mailbox@10228000              mediatek,mt8192-gce              "       @         <                      T                          gce             ]      clock-controller@10720000             mediatek,mt8192-scp_adsp                 r                             `fail          serial@11002000       *    mediatek,mt8192-uart mediatek,mt6577-uart                                  <       m                               	  baud bus            `okay          serial@11003000       *    mediatek,mt8192-uart mediatek,mt6577-uart                 0                <       n                               	  baud bus          	  `disabled          clock-controller@11007000             mediatek,mt8192-imp_iic_wrap_c                p                          spi@1100a000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                  <                             M                    parent-clk sel-clk spi-clk        	  `disabled          thermal-sensor@1100b000           mediatek,mt8192-lvts-ap                               <                             	        g               n   '        zlvts-calib-data-1                          {      svs@1100bc00              mediatek,mt8192-svs                               <                             	        main            n   (   '      (  zsvs-calibration-data t-calibration-data         g              svs_rst       pwm@1100e000              mediatek,mt8183-disp-pwm                                  <                                        !      8        main mm         `okay            default            )            |      spi@11010000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                  <                             M            <        parent-clk sel-clk spi-clk          `okay                        default            *   ec@0              google,cros-ec-spi                       #                  -        default            +                              +       pwm           google,cros-ec-pwm                     `okay                      i2c-tunnel            google,cros-ec-i2c-tunnel                                    +       sbs-battery@b             sbs,sbs-battery                                *            regulator@0           google,cros-ec-regulator                          w@         2Z            [      regulator@1           google,cros-ec-regulator                         2Z         2Z            Z      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector                      ?left            Edual            Phost            Zsource        connector@1           usb-c-connector                     ?right           Edual            Phost            Zsource           keyboard-controller           google,cros-ec-keyb         i           y                 D     t x c  	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (                 	  	                 spi@11012000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                  <                             M            >        parent-clk sel-clk spi-clk        	  `disabled          spi@11013000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                 0                <                             M            ?        parent-clk sel-clk spi-clk        	  `disabled          spi@11018000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 <                             M            L        parent-clk sel-clk spi-clk        	  `disabled          spi@11019000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 <                             M            M        parent-clk sel-clk spi-clk          `okay                  %                       default            ,   tpm@0             google,cr50                      #                  B@        default            -         spi@1101d000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 <                             M            m        parent-clk sel-clk spi-clk        	  `disabled          spi@1101e000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 <                             M            n        parent-clk sel-clk spi-clk        	  `disabled          scp@10500000              mediatek,mt8192-scp       0       P             r             p                 sram cfg l1tcm          <                                    main            `okay            mediatek/mt8192/scp.img            .        default            /            q   cros-ec-rpmsg             google,cros-ec-rpmsg            cros-ec-rpmsg            usb@11200000          '    mediatek,mt8192-xhci mediatek,mtk-xhci                               >              	  mac ippc            #          a               host               0      1                 "      #              ]      ]                7   2               R      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck                     3      f        `okay            -   4        ;   5      syscon@11210000           mediatek,mt8192-audsys syscon                !                                  8   mt8192-afe-pcm            mediatek,mt8192-audio           <                      g   6         	  audiosys            G   2                   [           m   7               8       8      8      8      8      8      8      8      8      8      8   	   8   
   8      8      8      8      8      8      8      8         /      :                  H      /      e      0      i      +      g      ,      k      ;      <      =      >      ?      @      A      B      C      D                                                                        7        u  aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adda6_adc_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_tdm_clk aud_tml_clk aud_nle aud_dac_hires_clk aud_adc_hires_clk aud_adc_hires_tml aud_adda6_adc_hires_clk aud_3rd_dac_clk aud_3rd_dac_predis_clk aud_3rd_dac_tml aud_3rd_dac_hires_clk aud_infra_clk aud_infra_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d4_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d4 top_mux_aud_eng2 top_apll2_d4 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_i2s6_m_sel top_i2s7_m_sel top_i2s8_m_sel top_i2s9_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_apll12_div5 top_apll12_div6 top_apll12_div7 top_apll12_div8 top_apll12_div9 top_mux_audio_h top_clk26m_clk                         pcie@11230000             mediatek,mt8192-pcie             pci              #                	  pcie-mac                         +         0         +      '      *      j      ^      \      /  pl_250m tl_26m tl_96m tl_32k peri_26m top_133m                )              Q        <                      {             8  k                                                                                      `                    9                      9                     9                     9           default            :   interrupt-controller                                                 9      pcie@0,0             pci                                                 {                           +            k   wifi@0,0          (                                                 ;            spi@11234000              mediatek,mt8192-nor              #@                <                            :      w      ]        spi sf axi                :              b                     +            `okay            default            <   flash@0            winbond,w25q64jwm jedec,spi-nor                      u                                thermal-sensor@11278000           mediatek,mt8192-lvts-mcu                 '                <                             	        g              n   '        zlvts-calib-data-1                          r      efuse@11c10000        %    mediatek,mt8192-efuse mediatek,efuse                                               +      socinfo-data1@44                D         socinfo-data2@50                P         data1@1c0                 X            '      calib@580                 h            (         i2c@11cb0000              mediatek,mt8192-i2c                            !s                <       s                   =          x      	  main dma                                     +            `okay                      default            >   anx7625@58            analogix,anx7625                X        default            ?              )                  *               @           A           B   ports                        +       port@0                  endpoint               C            a         port@1                 endpoint               D            F            aux-bus    panel         
    edp-panel           "   B        /   E   port       endpoint               F            D                     clock-controller@11cb1000             mediatek,mt8192-imp_iic_wrap_e                                               =      i2c@11d00000              mediatek,mt8192-i2c                            !v               <       w                   G          x      	  main dma                                     +            `okay                      default            H      i2c@11d01000              mediatek,mt8192-i2c                           !w              <       x                   G         x      	  main dma                                     +          	  `disabled          i2c@11d02000              mediatek,mt8192-i2c                            !y               <       y                   G         x      	  main dma                                     +          	  `disabled          clock-controller@11d03000             mediatek,mt8192-imp_iic_wrap_s               0                                G      i2c@11d20000              mediatek,mt8192-i2c                            !q                <       q                   I          x      	  main dma                                     +            `okay                      default            J   audio-codec@1a                      #                 9           H           Y   K        e   K        r   K           4          realtek,rt5682s                      i2c@11d21000              mediatek,mt8192-i2c                           !q              <       r                   I         x      	  main dma                                     +            `okay                        18        default            L   trackpad@15           elan,ekth3000                       #                 default            M           N                  i2c@11d22000              mediatek,mt8192-i2c                            !s              <       t                   I         x      	  main dma                                     +          	  `disabled          clock-controller@11d23000              mediatek,mt8192-imp_iic_wrap_ws              0                                I      i2c@11e00000              mediatek,mt8192-i2c                            !u                <       u                   O          x      	  main dma                                     +          	  `disabled          clock-controller@11e01000             mediatek,mt8192-imp_iic_wrap_w                                               O      t-phy@11e40000        .    mediatek,mt8192-tphy mediatek,generic-tphy-v2                        +           k                usb-phy@0                                       ref                        0      usb-phy@700               	                     ref                        1         dsi-phy@11e50000              mediatek,mt8183-mipi-tx                                   2   
                                  mipi_tx0_pll            `okay                `      i2c@11f00000              mediatek,mt8192-i2c                            !p               <       p                   P          x      	  main dma                                     +            `okay                      default            Q   touchscreen@10                      #                 default            R          elan,ekth3500            i2c@11f01000              mediatek,mt8192-i2c                           !u               <       v                   P         x      	  main dma                                     +          	  `disabled          clock-controller@11f02000             mediatek,mt8192-imp_iic_wrap_n                                                P      clock-controller@11f10000             mediatek,mt8192-msdc_top                                                  S      mmc@11f60000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                             <       c             8            S   	   S      S      S      S      S         3  source hclk source_cg sys_cg pclk_cg axi_cg ahb_cg          `okay            default state_uhs              T           U                               V           W                                    		         	         	'        	A (         	P         	X         	^      mmc@11f70000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                             <       g             8            S   
   S      S      S      S      S         3  source hclk source_cg sys_cg pclk_cg axi_cg ahb_cg          `okay            default state_uhs              X           Y                            	l                    Z           [         	u         	         	         	P         	      gpu@13000000          )    mediatek,mt8192-mali arm,mali-valhall-jm                          @       0  <      m             l             k               job mmu gpu             2         (  m   7      7      7      7      7           	core0 core1 core2 core3 core4           	   \        `okay            	         clock-controller@13fbf000             mediatek,mt8192-mfgcfg                                         syscon@14000000           mediatek,mt8192-mmsys syscon                                                          	   ]          ]              	   ]                            mutex@14001000            mediatek,mt8192-disp-mutex                                <                                      	   ]                 	            m   7   	      smi@14002000              mediatek,mt8192-smi-common                                                                   apb smi gals0 gals1         m   7   	            ^      larb@14003000             mediatek,mt8192-smi-larb                  0                
            
   ^                       apb smi         m   7   	            b      larb@14004000             mediatek,mt8192-smi-larb                  @                
           
   ^                       apb smi         m   7   	            c      ovl@14005000              mediatek,mt8192-disp-ovl                  P                <                                     
,   _      _           m   7   	        	   ]     P          ovl@14006000              mediatek,mt8192-disp-ovl-2l               `                <                      m   7   	                       
,   _   "   _            	   ]     `          rdma@14007000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma               p                <                                     
,   _           
3           m   7   	        	   ]     p          color@14009000        6    mediatek,mt8192-disp-color mediatek,mt8173-disp-color                                 <                     m   7   	                       	   ]               ccorr@1400a000            mediatek,mt8192-disp-ccorr                                <                     m   7   	               	        	   ]               aal@1400b000          2    mediatek,mt8192-disp-aal mediatek,mt8183-disp-aal                                 <                     m   7   	                       	   ]               gamma@1400c000        6    mediatek,mt8192-disp-gamma mediatek,mt8183-disp-gamma                                 <                     m   7   	                       	   ]               postmask@1400d000             mediatek,mt8192-disp-postmask                                 <                     m   7   	                       	   ]               dither@1400e000       8    mediatek,mt8192-disp-dither mediatek,mt8183-disp-dither                               <                     m   7   	               
        	   ]               dsi@14010000              mediatek,mt8183-dsi                               <      	                                `        engine digital hs              `        
Kdphy            m   7   	        g              `okay       port       endpoint               a            C            ovl@14014000              mediatek,mt8192-disp-ovl-2l              @                <                     m   7   	                       
,   _   #   _   !        	   ]     @          rdma@14015000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma              P                <                     m   7   	                       
,   _   %        
3           	   ]     P          dpi@14016000              mediatek,mt8192-dpi              `                <                            !         2           pixel engine pll          	  `disabled          m4u@1401d000              mediatek,mt8192-m4u                            <  
U   b   c   d   e   f   g   h   i   j   k   l   m   n   o   p        <                                    bclk            m   7   	        
d               _      clock-controller@15020000             mediatek,mt8192-imgsys                                                      larb@1502e000             mediatek,mt8192-smi-larb                                 
   	        
   ^                               apb smi         m   7               h      clock-controller@15820000             mediatek,mt8192-imgsys2                                                     larb@1582e000             mediatek,mt8192-smi-larb                                 
           
   ^                               apb smi         m   7               i      video-codec@16000000              mediatek,mt8192-vcodec-dec                                 
q   q        
,   _                        +           k                    `    video-codec@10000             mediatek,mtk-vcodec-lat                                <                   @  
,   _      _      _      _      _      _      _      _         (         4                            F        sel soc-vdec soc-lat vdec top                 4              F        m   7         video-codec@25000             mediatek,mtk-vcodec-core                  P                <                   X  
,   _      _      _      _      _      _      _      _      _      _      _         (         4   !      !      !          F        sel soc-vdec soc-lat vdec top                 4              F        m   7            larb@1600d000             mediatek,mt8192-smi-larb                                  
           
   ^                                 apb smi         m   7               f      clock-controller@1600f000             mediatek,mt8192-vdecsys_soc                                                      larb@1602e000             mediatek,mt8192-smi-larb                                 
           
   ^            !       !            apb smi         m   7               e      clock-controller@1602f000             mediatek,mt8192-vdecsys                                              !      clock-controller@17000000             mediatek,mt8192-vencsys                                                      larb@17010000             mediatek,mt8192-smi-larb                                  
           
   ^                              apb smi         m   7               g      vcodec@17020000           mediatek,mt8192-vcodec-enc                               X  
,   _      _      _      _      _      _      _      _      _      _      _           <      5               
q   q        m   7                        	  venc_sel                  3              W      clock-controller@1a000000             mediatek,mt8192-camsys                                                 "      larb@1a001000             mediatek,mt8192-smi-larb                                  
           
   ^            "      "            apb smi         m   7               j      larb@1a002000             mediatek,mt8192-smi-larb                                   
           
   ^            "      "           apb smi         m   7               k      larb@1a00f000             mediatek,mt8192-smi-larb                                  
           
   ^            #      #            apb smi         m   7               l      larb@1a010000             mediatek,mt8192-smi-larb                                  
           
   ^            $      $            apb smi         m   7               m      larb@1a011000             mediatek,mt8192-smi-larb                                 
           
   ^            %       %           apb smi         m   7               n      clock-controller@1a04f000             mediatek,mt8192-camsys_rawa                                              #      clock-controller@1a06f000             mediatek,mt8192-camsys_rawb                                              $      clock-controller@1a08f000             mediatek,mt8192-camsys_rawc                                              %      clock-controller@1b000000             mediatek,mt8192-ipesys                                                       larb@1b00f000             mediatek,mt8192-smi-larb                                  
           
   ^                             apb smi         m   7   
            p      larb@1b10f000             mediatek,mt8192-smi-larb                                 
           
   ^                              apb smi         m   7   
            o      clock-controller@1f000000             mediatek,mt8192-mdpsys                                                       larb@1f002000             mediatek,mt8192-smi-larb                                   
           
   ^                             apb smi         m   7               d         thermal-zones      cpu0-thermal            
~          
           
   r      trips      trip-alert          
 L        
           Epassive             s      trip-crit           
         
        	   Ecritical             cooling-maps       map0            
   s      0  
   
                     cpu1-thermal            
~          
           
   r      trips      trip-alert          
 L        
           Epassive             t      trip-crit           
         
        	   Ecritical             cooling-maps       map0            
   t      0  
   
                     cpu2-thermal            
~          
           
   r      trips      trip-alert          
 L        
           Epassive             u      trip-crit           
         
        	   Ecritical             cooling-maps       map0            
   u      0  
   
                     cpu3-thermal            
~          
           
   r      trips      trip-alert          
 L        
           Epassive             v      trip-crit           
         
        	   Ecritical             cooling-maps       map0            
   v      0  
   
                     cpu4-thermal            
~          
           
   r       trips      trip-alert          
 L        
           Epassive             w      trip-crit           
         
        	   Ecritical             cooling-maps       map0            
   w      0  
                        cpu5-thermal            
~          
           
   r      trips      trip-alert          
 L        
           Epassive             x      trip-crit           
         
        	   Ecritical             cooling-maps       map0            
   x      0  
                        cpu6-thermal            
~          
           
   r      trips      trip-alert          
 L        
           Epassive             y      trip-crit           
         
        	   Ecritical             cooling-maps       map0            
   y      0  
                        cpu7-thermal            
~          
           
   r      trips      trip-alert          
 L        
           Epassive             z      trip-crit           
         
        	   Ecritical             cooling-maps       map0            
   z      0  
                        vpu0-thermal            
~          
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  ppvar_sys                     `            }      reserved-memory                      +            k   scp@50000000              shared-dma-pool              P                              .      wifi@c0000000             restricted-dma-pool                                    ;         audio-codec           realtek,rt1015p         default                                      H                      sound                     aud_clk_mosi_off aud_clk_mosi_on aud_dat_mosi_off aud_dat_mosi_on aud_dat_miso_off aud_dat_miso_on vow_dat_miso_off vow_dat_miso_on vow_clk_miso_off vow_clk_miso_on aud_nle_mosi_off aud_nle_mosi_on aud_dat_miso2_off aud_dat_miso2_on aud_gpio_i2s3_off aud_gpio_i2s3_on aud_gpio_i2s8_off aud_gpio_i2s8_on aud_gpio_i2s9_off aud_gpio_i2s9_on aud_dat_mosi_ch34_off aud_dat_mosi_ch34_on aud_dat_miso_ch34_off aud_dat_miso_ch34_on aud_gpio_tdm_off aud_gpio_tdm_on                                                                                                                                                           &           1           <           G           R           ]           h           s           ~                                                     '    mediatek,mt8192_mt6359_rt1015p_rt5682s     speaker-codecs                   headset-codec                           pwmleds       	    pwm-leds       led         kbd_backlight                       
                             	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl-2l0 ovl-2l2 rdma0 rdma4 i2c0 i2c1 i2c2 i2c3 i2c7 mmc0 mmc1 serial0 #clock-cells clocks clock-div clock-mult clock-output-names phandle clock-frequency device_type reg enable-method cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains capacity-dmips-mhz #cooling-cells cpu cache-level cache-unified entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts opp-shared opp-hz opp-microvolt dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux output-low input-enable bias-pull-up drive-strength drive-strength-microamp bias-disable bias-pull-down output-high #power-domain-cells clock-names mediatek,infracfg domain-supply assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread #mbox-cells status resets nvmem-cells nvmem-cell-names #thermal-sensor-cells reset-names #pwm-cells pinctrl-names pinctrl-0 mediatek,pad-select spi-max-frequency wakeup-source google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count label power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap cs-gpios firmware-name memory-region mediatek,rpmsg-name interrupt-names phys mediatek,syscon-wakeup vusb33-supply vbus-supply mediatek,apmixedsys mediatek,topckgen power-domains bus-range interrupt-map-mask interrupt-map num-lanes spi-rx-bus-width spi-tx-bus-width enable-gpios reset-gpios vdd10-supply vdd18-supply vdd33-supply remote-endpoint power-supply backlight realtek,jd-src #sound-dai-cells AVDD-supply DBVDD-supply LDO1-IN-supply MICVDD-supply clock-stretch-ns vcc-supply #phy-cells pinctrl-1 vmmc-supply vqmmc-supply cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset mmc-hs400-enhanced-strobe hs400-ds-delay no-sdio no-sd non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc power-domain-names operating-points-v2 mali-supply mboxes mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus mediatek,rdma-fifo-size phy-names mediatek,larbs #iommu-cells mediatek,scp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path pwms brightness-levels num-interpolated-steps default-brightness-level num-channels wakeup-delay-ms enable-active-high regulator-boot-on gpio vin-supply off-on-delay-us no-map sdb-gpios mediatek,platform pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 pinctrl-8 pinctrl-9 pinctrl-10 pinctrl-11 pinctrl-12 pinctrl-13 pinctrl-14 pinctrl-15 pinctrl-16 pinctrl-17 pinctrl-18 pinctrl-19 pinctrl-20 pinctrl-21 pinctrl-22 pinctrl-23 pinctrl-24 pinctrl-25 sound-dai function color max-brightness 