     8     (            9  x                             $    mediatek,mt8192-evb mediatek,mt8192                                  +         !   7MediaTek MT8192 evaluation board       aliases          =/soc/ovl@14005000            B/soc/ovl@14006000            J/soc/ovl@14014000            R/soc/rdma@14007000           X/soc/rdma@14015000           ^/soc/serial@11002000          fixed-factor-clock-13m            fixed-factor-clock           f             s            z                        clk13m              $      oscillator0           fixed-clock          f                      clk26m                    oscillator1           fixed-clock          f                         clk32k        cpus                         +       cpu@0            cpu           arm,cortex-a55                        psci             ec3@                                       @                              !   @        3           @           Q               e          x               
      cpu@100          cpu           arm,cortex-a55                       psci             ec3@                                       @                              !   @        3           @           Q               e          x                     cpu@200          cpu           arm,cortex-a55                       psci             ec3@                                       @                              !   @        3           @           Q               e          x                     cpu@300          cpu           arm,cortex-a55                       psci             ec3@                                       @                              !   @        3           @           Q               e          x                     cpu@400          cpu           arm,cortex-a76                       psci             f                                       @                              !   @        3           @   	        Q              e           x                     cpu@500          cpu           arm,cortex-a76                       psci             f                                       @                              !   @        3           @   	        Q              e           x                     cpu@600          cpu           arm,cortex-a76                       psci             f                                       @                              !   @        3           @   	        Q              e           x                     cpu@700          cpu           arm,cortex-a76                       psci             f                                       @                              !   @        3           @   	        Q              e           x                     cpu-map    cluster0       core0              
      core1                    core2                    core3                    core4                    core5                    core6                    core7                          l2-cache0             cache                                      @        	           @                              l2-cache1             cache                                      @        	           @                        	      l3-cache              cache                                       @        	                              idle-states         psci       cpu-retention-l           arm,idle-state                                7                                       cpu-retention-b           arm,idle-state                                #                                       cpu-off-l             arm,idle-state                               <                     \                  cpu-off-b             arm,idle-state                               (                                             pmu-a55           arm,cortex-a55-pmu                                        pmu-a76           arm,cortex-a76-pmu                                        psci              arm,psci-1.0             smc       timer             arm,armv8-timer                   @                                               
                 ]@      opp-table-0           operating-points-v2                      5   opp-358000000           "    V        ) 	@*      opp-399000000           "    A        ) 	p      opp-440000000           "    9         ) 	      opp-482000000           "            ) 	Ҧ      opp-523000000           "    ,X        ) 
z      opp-564000000           "    !         ) 
4N      opp-605000000           "    $@        ) 
e"      opp-647000000           "    &o        ) 
      opp-688000000           "    )         ) 
      opp-724000000           "    +']         )       opp-748000000           "    ,         ) @      opp-772000000           "    .         ) q      opp-795000000           "    /b        )       opp-819000000           "    0        ) X      opp-843000000           "    2?(        ) ,      opp-866000000           "    3        ) 5          soc                      +             simple-bus          7                                ;   performance-controller@11bc10             mediatek,cpufreq-hw                            0               B                     interrupt-controller@c000000              arm,gic-v3          \           m                                                                            	                      ppi-partitions     interrupt-partition-0              
                           interrupt-partition-1                                               syscon@10000000            mediatek,mt8192-topckgen syscon                                 f                     syscon@10001000            mediatek,mt8192-infracfg syscon                                f                                syscon@10003000           mediatek,mt8192-pericfg syscon                0                 f               *      pinctrl@10005000              mediatek,mt8192-pinctrl               P                                                                                                                                                ]  iocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint                                                                                     \                     syscon@10006000       )    mediatek,mt8192-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8192-power-controller                         +                           ,   power-domain@0                        s            :      /        audio audio1 audio2                              power-domain@1                       s              conn                                 power-domain@2                       s                    mfg alt                      +                  power-domain@3                                              +                  power-domain@4                                power-domain@5                                power-domain@6                                power-domain@7                                power-domain@8                                      power-domain@9              	      (   s                                    !  disp disp-0 disp-1 disp-2 disp-3                                    +                  power-domain@10             
      (   s                                       ipe ipe-0 ipe-1 ipe-2 ipe-3                              power-domain@11                      s                           isp isp-0 isp-1                              power-domain@12                      s                           isp2 isp2-0 isp2-1                               power-domain@13                      s                  
  mdp mdp-0                                power-domain@14                      s      3              venc venc-0                              power-domain@15                       s      4                           vdec vdec-0 vdec-1 vdec-2                                   +                  power-domain@16                      s                           vdec2-0 vdec2-1 vdec2-2                      power-domain@17                   (   s      
                                     cam cam-0 cam-1 cam-2 cam-3                                 +                  power-domain@18                      s   !            cam_rawa-0                    power-domain@19                      s   "            cam_rawb-0                    power-domain@20                      s   #            cam_rawc-0                                watchdog@10007000             mediatek,mt8192-wdt               p                               +      syscon@1000c000       "    mediatek,mt8192-apmixedsys syscon                                  f               )      timer@10017000        ,    mediatek,mt8192-timer mediatek,mt6765-timer              p                                       s   $      pwrap@10026000            mediatek,mt6873-pwrap                `                pwrap                                  s                   	  spi wrap                          #         pmic              mediatek,mt6359                  \      adc           mediatek,mt6359-auxadc          :         mt6359codec       regulators            mediatek,mt6359-regulator      buck_vs1            Lvs1         [ 5         s !                           buck_vgpu11         Lvgpu11          [         s 7                                             buck_vmodem         Lvmodem          [         s           *                 buck_vpu            Lvpu         [         s 7                                             buck_vcore          Lvcore           [         s                                               buck_vs2            Lvs2         [ 5         s j                            buck_vpa            Lvpa         [          s 7          ,      buck_vproc2         Lvproc2          [         s 7          L                                   buck_vproc1         Lvproc1          [         s 7          L                                   buck_vcore_sshub            Lvcore_sshub         [         s 7      buck_vgpu11_sshub           Lvgpu11_sshub            [         s 7      ldo_vaud18          Lvaud18          [ w@        s w@                 ldo_vsim1           Lvsim1           [         s /M`      ldo_vibr            Lvibr            [ O        s 2Z      ldo_vrf12           Lvrf12           [         s        ldo_vusb            Lvusb            [ -        s -                         ldo_vsram_proc2         Lvsram_proc2         [          s           L                          ldo_vio18           Lvio18           [         s                          ldo_vcamio          Lvcamio          [         s       ldo_vcn18           Lvcn18           [ w@        s w@                 ldo_vfe28           Lvfe28           [ *        s *           x      ldo_vcn13           Lvcn13           [         s        ldo_vcn33_1_bt          Lvcn33_1_bt          [ *        s 5g      ldo_vcn33_1_wifi            Lvcn33_1_wifi            [ *        s 5g      ldo_vaux18          Lvaux18          [ w@        s w@                          ldo_vsram_others            Lvsram_others            [          s                            ldo_vefuse          Lvefuse          [         s       ldo_vxo22           Lvxo22           [ w@        s !               ldo_vrfck           Lvrfck           [ `        s       ldo_vrfck_1         Lvrfck           [         s j       ldo_vbif28          Lvbif28          [ *        s *                 ldo_vio28           Lvio28           [ *        s 2Z               ldo_vemc            Lvemc            [ ,@         s 2Z      ldo_vemc_1          Lvemc            [ &%        s 2Z      ldo_vcn33_2_bt          Lvcn33_2_bt          [ *        s 5g      ldo_vcn33_2_wifi            Lvcn33_2_wifi            [ *        s 5g      ldo_va12            Lva12            [ O        s                 ldo_va09            Lva09            [ 5         s O      ldo_vrf18           Lvrf18           [         s P      ldo_vsram_md          	  Lvsram_md            [          s           *                 ldo_vufs            Lvufs            [         s       ldo_vm18            Lvm18            [         s                ldo_vbbck           Lvbbck           [         s O      ldo_vsram_proc1         Lvsram_proc1         [          s           L                          ldo_vsim2           Lvsim2           [         s /M`      ldo_vsram_others_sshub          Lvsram_others_sshub          [          s          rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt6873-spmi                  p                            pmif spmimst             s                   8      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux                       #            mailbox@10228000              mediatek,mt8192-gce              "       @                                           s              gce             6      clock-controller@10720000             mediatek,mt8192-scp_adsp                 r                  f           fail          serial@11002000       *    mediatek,mt8192-uart mediatek,mt6577-uart                                         m                s               	  baud bus            okay          serial@11003000       *    mediatek,mt8192-uart mediatek,mt6577-uart                 0                       n                s               	  baud bus          	  disabled          clock-controller@11007000             mediatek,mt8192-imp_iic_wrap_c                p                 f         spi@1100a000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                         s      M                    parent-clk sel-clk spi-clk        	  disabled          thermal-sensor@1100b000           mediatek,mt8192-lvts-ap                                                      s      	                          %        lvts-calib-data-1                          S      svs@1100bc00              mediatek,mt8192-svs                                                      s      	        main               &   %      (  svs-calibration-data t-calibration-data                       5svs_rst       pwm@1100e000              mediatek,mt8183-disp-pwm                                                        A            s      !      8        main mm       	  disabled          spi@11010000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                         s      M            <        parent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                         s      M            >        parent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                 0                                       s      M            ?        parent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            L        parent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            M        parent-clk sel-clk spi-clk        	  disabled          spi@1101d000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            m        parent-clk sel-clk spi-clk        	  disabled          spi@1101e000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            n        parent-clk sel-clk spi-clk        	  disabled          scp@10500000              mediatek,mt8192-scp       0       P             r             p                 sram cfg l1tcm                                s              main          	  disabled                I      usb@11200000          '    mediatek,mt8192-xhci mediatek,mtk-xhci                               >              	  mac ippc            L          a               `host            p   '      (                 "      #        #      ]      ]          s      7   )               R      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck          u           *      f      	  disabled          syscon@11210000           mediatek,mt8192-audsys syscon                !                   f               -   mt8192-afe-pcm            mediatek,mt8192-audio                                    +         	  5audiosys               )                                 ,            s   -       -      -      -      -      -      -      -      -      -      -   	   -   
   -      -      -      -      -      -      -      -         /      :                  H      /      e      0      i      +      g      ,      k      ;      <      =      >      ?      @      A      B      C      D                                                                        7        u  aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adda6_adc_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_tdm_clk aud_tml_clk aud_nle aud_dac_hires_clk aud_adc_hires_clk aud_adc_hires_tml aud_adda6_adc_hires_clk aud_3rd_dac_clk aud_3rd_dac_predis_clk aud_3rd_dac_tml aud_3rd_dac_hires_clk aud_infra_clk aud_infra_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d4_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d4 top_mux_aud_eng2 top_apll2_d4 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_i2s6_m_sel top_i2s7_m_sel top_i2s8_m_sel top_i2s9_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_apll12_div5 top_apll12_div6 top_apll12_div7 top_apll12_div8 top_apll12_div9 top_mux_audio_h top_clk26m_clk             pcie@11230000             mediatek,mt8192-pcie             pci              #                	  pcie-mac                         +         0   s      +      '      *      j      ^      \      /  pl_250m tl_26m tl_96m tl_32k peri_26m top_133m                )        #      Q                                           8  ;                                                      \                                `                    .                      .                     .                     .      interrupt-controller                                  \               .         spi@11234000              mediatek,mt8192-nor              #@                                      s      :      w      ]        spi sf axi                :        #                        +          	  disabled          thermal-sensor@11278000           mediatek,mt8192-lvts-mcu                 '                                       s      	                         %        lvts-calib-data-1                          J      efuse@11c10000        %    mediatek,mt8192-efuse mediatek,efuse                                               +      socinfo-data1@44                D         socinfo-data2@50                P         data1@1c0                 X            %      calib@580                 h            &         i2c@11cb0000              mediatek,mt8192-i2c                            !s                       s                s   /          x      	  main dma             z                        +          	  disabled          clock-controller@11cb1000             mediatek,mt8192-imp_iic_wrap_e                                f               /      i2c@11d00000              mediatek,mt8192-i2c                            !v                      w                s   0          x      	  main dma             z                        +          	  disabled          i2c@11d01000              mediatek,mt8192-i2c                           !w                     x                s   0         x      	  main dma             z                        +          	  disabled          i2c@11d02000              mediatek,mt8192-i2c                            !y                      y                s   0         x      	  main dma             z                        +          	  disabled          clock-controller@11d03000             mediatek,mt8192-imp_iic_wrap_s               0                 f               0      i2c@11d20000              mediatek,mt8192-i2c                            !q                       q                s   1          x      	  main dma             z                        +          	  disabled          i2c@11d21000              mediatek,mt8192-i2c                           !q                     r                s   1         x      	  main dma             z                        +          	  disabled          i2c@11d22000              mediatek,mt8192-i2c                            !s                     t                s   1         x      	  main dma             z                        +          	  disabled          clock-controller@11d23000              mediatek,mt8192-imp_iic_wrap_ws              0                 f               1      i2c@11e00000              mediatek,mt8192-i2c                            !u                       u                s   2          x      	  main dma             z                        +          	  disabled          clock-controller@11e01000             mediatek,mt8192-imp_iic_wrap_w                                f               2      t-phy@11e40000        .    mediatek,mt8192-tphy mediatek,generic-tphy-v2                        +           ;                usb-phy@0                            s           ref                        '      usb-phy@700               	          s           ref                        (         dsi-phy@11e50000              mediatek,mt8183-mipi-tx                                s   )   
         f                         mipi_tx0_pll          	  disabled                9      i2c@11f00000              mediatek,mt8192-i2c                            !p                      p                s   3          x      	  main dma             z                        +          	  disabled          i2c@11f01000              mediatek,mt8192-i2c                           !u                      v                s   3         x      	  main dma             z                        +          	  disabled          clock-controller@11f02000             mediatek,mt8192-imp_iic_wrap_n                                 f               3      clock-controller@11f10000             mediatek,mt8192-msdc_top                                   f               4      mmc@11f60000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                                    c             8   s         4   	   4      4      4      4      4         3  source hclk source_cg sys_cg pclk_cg axi_cg ahb_cg        	  disabled          mmc@11f70000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                                    g             8   s         4   
   4      4      4      4      4         3  source hclk source_cg sys_cg pclk_cg axi_cg ahb_cg        	  disabled          gpu@13000000          )    mediatek,mt8192-mali arm,mali-valhall-jm                          @       0        m             l             k               `job mmu gpu          s   )         (     ,      ,      ,      ,      ,           core0 core1 core2 core3 core4              5      	  disabled          clock-controller@13fbf000             mediatek,mt8192-mfgcfg                                f         syscon@14000000           mediatek,mt8192-mmsys syscon                                    f                      +   6          6              2   6                            mutex@14001000            mediatek,mt8192-disp-mutex                                                       s               2   6                 J               ,   	      smi@14002000              mediatek,mt8192-smi-common                                   s                                apb smi gals0 gals1            ,   	            7      larb@14003000             mediatek,mt8192-smi-larb                  0                ^            o   7         s              apb smi            ,   	            :      larb@14004000             mediatek,mt8192-smi-larb                  @                ^           o   7         s              apb smi            ,   	            ;      ovl@14005000              mediatek,mt8192-disp-ovl                  P                                       s              |   8      8              ,   	        2   6     P          ovl@14006000              mediatek,mt8192-disp-ovl-2l               `                                         ,   	         s              |   8   "   8            2   6     `          rdma@14007000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma               p                                       s              |   8                         ,   	        2   6     p          color@14009000        6    mediatek,mt8192-disp-color mediatek,mt8173-disp-color                                                         ,   	         s              2   6               ccorr@1400a000            mediatek,mt8192-disp-ccorr                                                        ,   	         s      	        2   6               aal@1400b000          2    mediatek,mt8192-disp-aal mediatek,mt8183-disp-aal                                                         ,   	         s              2   6               gamma@1400c000        6    mediatek,mt8192-disp-gamma mediatek,mt8183-disp-gamma                                                         ,   	         s              2   6               postmask@1400d000             mediatek,mt8192-disp-postmask                                                         ,   	         s              2   6               dither@1400e000       8    mediatek,mt8192-disp-dither mediatek,mt8183-disp-dither                                                       ,   	         s      
        2   6               dsi@14010000              mediatek,mt8183-dsi                                     	                s                9        engine digital hs           p   9        dphy               ,   	                    	  disabled       port       endpoint                ovl@14014000              mediatek,mt8192-disp-ovl-2l              @                                        ,   	         s              |   8   #   8   !        2   6     @          rdma@14015000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma              P                                        ,   	         s              |   8   %                   2   6     P          dpi@14016000              mediatek,mt8192-dpi              `                                      s      !         )           pixel engine pll          	  disabled          m4u@1401d000              mediatek,mt8192-m4u                            <     :   ;   <   =   >   ?   @   A   B   C   D   E   F   G   H                              s              bclk               ,   	                       8      clock-controller@15020000             mediatek,mt8192-imgsys                                 f                     larb@1502e000             mediatek,mt8192-smi-larb                                 ^   	        o   7         s                      apb smi            ,               @      clock-controller@15820000             mediatek,mt8192-imgsys2                                f                     larb@1582e000             mediatek,mt8192-smi-larb                                 ^           o   7         s                      apb smi            ,               A      video-codec@16000000              mediatek,mt8192-vcodec-dec                                    I        |   8                        +           ;                    `    video-codec@10000             mediatek,mtk-vcodec-lat                                                   @  |   8      8      8      8      8      8      8      8         (   s      4                         F        sel soc-vdec soc-lat vdec top                 4        #      F           ,         video-codec@25000             mediatek,mtk-vcodec-core                  P                                   X  |   8      8      8      8      8      8      8      8      8      8      8         (   s      4                         F        sel soc-vdec soc-lat vdec top                 4        #      F           ,            larb@1600d000             mediatek,mt8192-smi-larb                                  ^           o   7         s                      apb smi            ,               >      clock-controller@1600f000             mediatek,mt8192-vdecsys_soc                                f                     larb@1602e000             mediatek,mt8192-smi-larb                                 ^           o   7         s                      apb smi            ,               =      clock-controller@1602f000             mediatek,mt8192-vdecsys                               f                     clock-controller@17000000             mediatek,mt8192-vencsys                                 f                     larb@17010000             mediatek,mt8192-smi-larb                                  ^           o   7         s                     apb smi            ,               ?      vcodec@17020000           mediatek,mt8192-vcodec-enc                               X  |   8      8      8      8      8      8      8      8      8      8      8                 5                  I           ,            s            	  venc_sel                  3        #      W      clock-controller@1a000000             mediatek,mt8192-camsys                                  f                      larb@1a001000             mediatek,mt8192-smi-larb                                  ^           o   7         s                       apb smi            ,               B      larb@1a002000             mediatek,mt8192-smi-larb                                   ^           o   7         s                      apb smi            ,               C      larb@1a00f000             mediatek,mt8192-smi-larb                                  ^           o   7         s   !      !            apb smi            ,               D      larb@1a010000             mediatek,mt8192-smi-larb                                  ^           o   7         s   "      "            apb smi            ,               E      larb@1a011000             mediatek,mt8192-smi-larb                                 ^           o   7         s   #       #           apb smi            ,               F      clock-controller@1a04f000             mediatek,mt8192-camsys_rawa                               f               !      clock-controller@1a06f000             mediatek,mt8192-camsys_rawb                               f               "      clock-controller@1a08f000             mediatek,mt8192-camsys_rawc                               f               #      clock-controller@1b000000             mediatek,mt8192-ipesys                                  f                     larb@1b00f000             mediatek,mt8192-smi-larb                                  ^           o   7         s                    apb smi            ,   
            H      larb@1b10f000             mediatek,mt8192-smi-larb                                 ^           o   7         s                     apb smi            ,   
            G      clock-controller@1f000000             mediatek,mt8192-mdpsys                                  f                     larb@1f002000             mediatek,mt8192-smi-larb                                   ^           o   7         s                    apb smi            ,               <         thermal-zones      cpu0-thermal                                    J      trips      trip-alert           L                   passive             K      trip-crit                            	   critical             cooling-maps       map0               K      0     
                     cpu1-thermal                                    J      trips      trip-alert           L                   passive             L      trip-crit                            	   critical             cooling-maps       map0               L      0     
                     cpu2-thermal                                    J      trips      trip-alert           L                   passive             M      trip-crit                            	   critical             cooling-maps       map0               M      0     
                     cpu3-thermal                                    J      trips      trip-alert           L                   passive             N      trip-crit                            	   critical             cooling-maps       map0               N      0     
                     cpu4-thermal                                    J       trips      trip-alert           L                   passive             O      trip-crit                            	   critical             cooling-maps       map0               O      0                          cpu5-thermal                                    J      trips      trip-alert           L                   passive             P      trip-crit                            	   critical             cooling-maps       map0               P      0                          cpu6-thermal                                    J      trips      trip-alert           L                   passive             Q      trip-crit                            	   critical             cooling-maps       map0               Q      0                          cpu7-thermal                                    J      trips      trip-alert           L                   passive             R      trip-crit                            	   critical             cooling-maps       map0               R      0                          vpu0-thermal                                    S      trips      trip-alert           L                   passive       trip-crit                            	   critical                vpu1-thermal                                    S   	   trips      trip-alert           L                   passive       trip-crit                            	   critical                gpu-thermal                                 S   
   trips      trip-alert           L                   passive       trip-crit                            	   critical                gpu1-thermal                                    S      trips      trip-alert           L                   passive       trip-crit                            	   critical                infra-thermal                                   S      trips      trip-alert           L                   passive       trip-crit                            	   critical                cam-thermal                                 S      trips      trip-alert           L                   passive       trip-crit                            	   critical                md0-thermal                                 S      trips      trip-alert           L                   passive       trip-crit                            	   critical                md1-thermal                                 S      trips      trip-alert           L                   passive       trip-crit                            	   critical                md2-thermal                                 S      trips      trip-alert           L                   passive       trip-crit                            	   critical                   chosen          -serial0:921600n8          memory@40000000          memory               @                   	compatible interrupt-parent #address-cells #size-cells model ovl0 ovl-2l0 ovl-2l2 rdma0 rdma4 serial0 #clock-cells clocks clock-div clock-mult clock-output-names phandle clock-frequency device_type reg enable-method cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains capacity-dmips-mhz #cooling-cells cpu cache-level cache-unified entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts opp-shared opp-hz opp-microvolt dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges #power-domain-cells clock-names mediatek,infracfg assigned-clocks assigned-clock-parents #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #mbox-cells status resets nvmem-cells nvmem-cell-names #thermal-sensor-cells reset-names #pwm-cells interrupts-extended interrupt-names phys wakeup-source mediatek,syscon-wakeup mediatek,apmixedsys mediatek,topckgen power-domains bus-range interrupt-map-mask interrupt-map #phy-cells power-domain-names operating-points-v2 mboxes mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus mediatek,rdma-fifo-size phy-names mediatek,larbs #iommu-cells mediatek,scp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path 