 t?   8 e   (             e                             D    google,tomato-rev4 google,tomato-rev3 google,tomato mediatek,mt8195                                  +            7Acer Tomato (rev3 - 4) board       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/i2c@11e00000            /soc/i2c@11e01000            /soc/i2c@11e02000            /soc/i2c@11e03000            /soc/i2c@11e04000           /soc/i2c@11d00000           /soc/i2c@11d02000           /soc/mmc@11230000           /soc/mmc@11240000           /soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55          *            .psci            <               Pec3@        `  4        s                            @                                 @                                                             cpu@100         cpu           arm,cortex-a55          *           .psci            <               Pec3@        `  4        s                            @                                 @                                                             cpu@200         cpu           arm,cortex-a55          *           .psci            <               Pec3@        `  4        s                            @                                 @                                                             cpu@300         cpu           arm,cortex-a55          *           .psci            <               Pec3@        `  4        s                            @                                 @                                                             cpu@400         cpu           arm,cortex-a78          *           .psci            <              Pf        `           s                            @                                 @                      	                      
                 cpu@500         cpu           arm,cortex-a78          *           .psci            <              Pf        `           s                            @                                 @                      	                      
                 cpu@600         cpu           arm,cortex-a78          *           .psci            <              Pf        `           s                            @                                 @                      	                      
                 cpu@700         cpu           arm,cortex-a78          *           .psci            <              Pf        `           s                            @                                 @                      	                      
                 cpu-map    cluster0       core0                    core1                    core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                     6        G   2        X   _        h  D                 cpu-retention-b           arm,idle-state                     6        G   -        X           h                   cpu-off-l             arm,idle-state                    6        G   7        X           h  H                 cpu-off-b             arm,idle-state                    6        G   2        X           h                      l2-cache0             cache           y                         @                                                l2-cache1             cache           y                         @                                          	      l3-cache              cache           y                          @                                        dsu-pmu           arm,dsu-pmu                                                                fail          dmic-codec            dmic-codec                        2      mt8195-sound                       okay                     }  DL10_FE DPTX_BE ETDM1_IN_BE ETDM2_IN_BE ETDM1_OUT_BE ETDM2_OUT_BE UL_SRC1_BE AFE_SOF_DL2 AFE_SOF_DL3 AFE_SOF_UL4 AFE_SOF_UL5            default                  ?  Headphone HPOL Headphone HPOR IN1P Headset Mic Ext Spk Speaker        %    mediatek,mt8195_mt6359_rt1019_rt5682             7m8195_r1019_5682s      mm-dai-link         ETDM1_IN_BE         )cpu       hs-playback-dai-link            ETDM1_OUT_BE            )cpu    codec           ?                hs-capture-dai-link         ETDM2_IN_BE         )cpu    codec           ?                spk-playback-dai-link           ETDM2_OUT_BE            )cpu    codec           ?            displayport-dai-link            DPTX_BE    codec           ?               fixed-factor-clock-13m            fixed-factor-clock          I            V           ]           g           rclk13m             2      oscillator-26m            fixed-clock         I            P        rclk26m                   oscillator-32k            fixed-clock         I            P           rclk32k        performance-controller@11bc10             mediatek,cpufreq-hw          *                 0                                   opp-table-gpu             operating-points-v2                     |   opp-390000000               >         	h      opp-410000000               p         	      opp-431000000                        	      opp-473000000               1h@         	<      opp-515000000               F         	<      opp-556000000               !#          	Ҧ      opp-598000000               #         	      opp-640000000               &%          	      opp-670000000               'c         
      opp-700000000               )'          
L      opp-730000000               +         
}      opp-760000000               -L          
`      opp-790000000               /q         
4      opp-820000000               05                opp-850000000               2         @      opp-880000000               4s          q         pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0            5smc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3                                                      *                                          	                              ppi-partitions     interrupt-partition-0           .                             interrupt-partition-1           .                                   syscon@10000000            mediatek,mt8195-topckgen syscon         *                      I              !      syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          *                     I           7              "      syscon@10003000           mediatek,mt8195-pericfg syscon          *     0                I              H      pinctrl@10005000              mediatek,mt8195-pinctrl         *     P                                                                                                         B  Diocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            N        ^           j                                                                 v        default                 >  I2S_SPKR_MCLK I2S_SPKR_DATAIN I2S_SPKR_LRCK I2S_SPKR_BCLK EC_AP_INT_ODL AP_FLASH_WP_L TCHPAD_INT_ODL EDP_HPD_1V8 AP_I2C_CAM_SDA AP_I2C_CAM_SCL AP_I2C_TCHPAD_SDA_1V8 AP_I2C_TCHPAD_SCL_1V8 AP_I2C_AUD_SDA AP_I2C_AUD_SCL AP_I2C_TPM_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 EC_AP_HPD_OD  PCIE_NVME_RST_L PCIE_NVME_CLKREQ_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL PCIE_WAKE_1V8_ODL CLK_24M_CAM0 CAM1_SEN_EN AP_I2C_PWR_SCL_1V8 AP_I2C_PWR_SDA_1V8 AP_I2C_MISC_SCL AP_I2C_MISC_SDA EN_PP5000_HDMI_X AP_HDMITX_HTPLG  AP_HDMITX_SCL_1V8 AP_HDMITX_SDA_1V8 AP_RTC_CLK32K AP_EC_WATCHDOG_L SRCLKENA0 SRCLKENA1 PWRAP_SPI0_CS_L PWRAP_SPI0_CK PWRAP_SPI0_MOSI PWRAP_SPI0_MISO SPMI_SCL SPMI_SDA    I2S_HP_DATAIN I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAOUT SD_CD_ODL EN_PP3300_DISP_X TCHSCR_RST_1V8_L TCHSCR_REPORT_DISABLE EN_PP3300_WLAN_X BT_KILL_1V8_L I2S_SPKR_DATAOUT WIFI_KILL_1V8_L BEEP_ON SCP_I2C_SENSOR_SCL_1V8 SCP_I2C_SENSOR_SDA_1V8     AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MISO2 SCP_VREQ_VAO AP_SPI_GSC_TPM_CLK AP_SPI_GSC_TPM_MOSI AP_SPI_GSC_TPM_CS_L AP_SPI_GSC_TPM_MISO EN_PP1000_CAM_X AP_EDP_BKLTEN  USB3_HUB_RST_L  WLAN_ALERT_ODL EC_IN_RW_ODL GSC_AP_INT_ODL HP_INT_ODL CAM0_RST_L CAM1_RST_L TCHSCR_INT_1V8_L CAM1_DET_L RST_ALC1011_L   BL_PWM_1V8 UART_AP_TX_DBG_RX UART_DBG_TX_AP_RX EN_SPKR AP_EC_WARM_RST_REQ UART_SCP_TX_DBGCON_RX UART_DBGCON_TX_SCP_RX   KPCOL0  MT6315_GPU_INT MT6315_PROC_BC_INT SD_CMD SD_CLK SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RSTB EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL   MT6360_INT_ODL SCP_JTAG0_TRSTN AP_SPI_EC_CS_L AP_SPI_EC_CLK AP_SPI_EC_MOSI AP_SPI_EC_MISO SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TDO SCP_JTAG0_TDI AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO                 audio-default-pins                pins-cmd-dat          D    E  F  G  H  I  J  K           <  1  2  3  4  5      pins-hp-jack-int-odl              Y                     e         cr50-irq-default-pins              k   pins-gsc-ap-int-odl           X                   cros-ec-irq-default-pins               >   pins-ec-ap-int-odl                        e                  edptx-default-pins                pins-cmd-dat                                disp-pwm0-default-pins             B   pins-disp-pwm             R   a         dptx-default-pins                 pins-cmd-dat                                i2c0-default-pins              b   pins-bus                	                            i2c1-default-pins              c   pins-bus              
                               i2c2-default-pins              f   pins-bus                                            i2c3-default-pins              j   pins-bus                                             i2c4-default-pins              l   pins-bus                                              i2c5-default-pins              ^   pins-bus                                            i2c7-default-pins              _   pins-bus                                  mmc0-default-pins              K   pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-clk              z                      f      pins-rst              x                      e         mmc0-uhs-pins              L   pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-clk              z                      f      pins-ds                                 f      pins-rst              x                      e         mmc1-detect-pins               P   pins-insert           6                   mmc1-default-pins              O   pins-cmd-dat              n  p  q  r  s                               e      pins-clk              o                      f         nor-default-pins               \   pins-ck-io                                          pins-cs                                        pcie0-default-pins     pins-bus                                    pcie1-default-pins             [   pins-bus                                    panel-pwr-default-pins                pins-vreg-en              7          pio-default-pins                  pins-wifi-enable              :                           pins-low-power-pd         ,          .   /   0   A   B   C   D                               pins-low-power-pupd       <    M   N   O   P   S   U   Z   [   ]   ^   _   `   h   i   k                     e      pins-low-power-hdmi-disable                  !                         pins-low-power-hdmi-rsel-disable              "   #                   $      pins-low-power-pcie0-disable                                                rt1019p-default-pins                  pins-amp-sdb              d                   scp-default-pins               4   pins-vreq             L                           spi0-default-pins              =   pins-cs-mosi-clk                                 pins-miso                               subpmic-default-pins               `   pins-subpmic-int-n                                        trackpad-default-pins              d   pins-int-n                                        touchscreen-default-pins               m   pins-int-n            \                     e      pins-rst              8                pins-report-sw            9                      syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            *     `           power-controller          !    mediatek,mt8195-power-controller                         +            %              6   power-domain@8          *                        +            %           9      power-domain@9          *   	        V          !           Gmfg alt         S   "                     +            %           9   #   power-domain@10         *   
        %          power-domain@11         *           %          power-domain@12         *           %          power-domain@13         *           %          power-domain@14         *           %                power-domain@15         *           V   !      !      !      !   	   !   @   !   A   !   K   !      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $           Gvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           S   "                     +            %      power-domain@16         *         8  V   !      %   $   %   %   %   &   %   '   %   (   %   )      D  Gvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         S   "                     +            %      power-domain@17         *           V   !      &      &           Gvppsys1 vppsys1-0 vppsys1-1         S   "        %          power-domain@22         *            V   '      '      '      '         $  Gwepsys-0 wepsys-1 wepsys-2 wepsys-3         S   "        %          power-domain@23         *           V   (            Gvdec0-0         S   "                     +            %       power-domain@24         *           V   )            Gvdec1-0         S   "        %          power-domain@25         *           V   *            Gvdec2-0         S   "        %             power-domain@26         *           V   +            Gvenc0-larb          S   "                     +            %       power-domain@27         *           V   ,            Gvenc1-larb          S   "        %             power-domain@18         *            V   !      -       -      -         &  Gvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           S   "                     +            %      power-domain@19         *           S   "        %          power-domain@20         *           S   "        %          power-domain@21         *           V   !   Q        Ghdmi_tx         %             power-domain@28         *           V   .       .   
        Gimg-0 img-1         S   "                     +            %      power-domain@29         *           %          power-domain@30         *           V   !      .      /           Gipe ipe-0 ipe-1         S   "        %             power-domain@31         *         (  V   0       0      0      0      0           Gcam-0 cam-1 cam-2 cam-3 cam-4           S   "                     +            %      power-domain@32         *            %          power-domain@33         *   !        %          power-domain@34         *   "        %                   power-domain@0          *            S   "        %          power-domain@1          *           S   "        %          power-domain@2          *           %          power-domain@3          *           %          power-domain@4          *           V   !   5   !   7        Gcsi_rx_top csi_rx_top1          %          power-domain@5          *           V   1           Gether           %          power-domain@6          *           V   !   X   !   n        Gadsp adsp1                       +            S   "        %      power-domain@7          *            V   !   g   !   "   !   n   "   2        Gaudio audio1 audio2 audio3          S   "        %                   watchdog@10007000             mediatek,mt8195-wdt         *     p                7              ;      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           *                     I                     timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         *    p                      	               V   2      pwrap@10024000            mediatek,mt8195-pwrap syscon            *    @                Dpwrap                                 V   "      "          	  Gspi wrap            e   !   $        u   !      pmic              mediatek,mt6359                                         adc           mediatek,mt6359-auxadc                   mt6359codec                             regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5           !                     4      buck_vgpu11         vgpu11                     7        H                     ]                   4      buck_vmodem         vmodem                             H  *                 buck_vpu            vpu                    7        H                     ]                   4      buck_vcore          vcore                               H                     ]                   4                 buck_vs2            vs2          5           j                      4      buck_vpa            vpa                     7          ,      buck_vproc2         vproc2                     7        H  L                   ]                buck_vproc1         vproc1                     7        H  L                   ]                buck_vcore_sshub            vcore_sshub                    7      buck_vgpu11_sshub           vgpu11_sshub             dp          dp         4      ldo_vaud18          vaud18           w@          w@                 ldo_vsim1           vsim1                      /M`      ldo_vibr            vibr             O          2Z      ldo_vrf12           vrf12                                4      ldo_vusb            vusb             -          -                   4           I      ldo_vsram_proc2         vsram_proc2                             H  L                    4      ldo_vio18           vio18                                         4           g      ldo_vcamio          vcamio                           ldo_vcn18           vcn18            w@          w@                 ldo_vfe28           vfe28            *          *           x      ldo_vcn13           vcn13                             ldo_vcn33_1_bt          vcn33_1_bt           *          5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *          5g      ldo_vaux18          vaux18           w@          w@                    4      ldo_vsram_others            vsram_others             q          q        H                        #      ldo_vefuse          vefuse                           ldo_vxo22           vxo22            w@          !         4      ldo_vrfck           vrfck            `                ldo_vrfck_1         vrfck                      j       ldo_vbif28          vbif28           *          *                 ldo_vio28           vio28            *          2Z         4      ldo_vemc            vemc             ,@           2Z      ldo_vemc_1          vemc             &%          2Z           M      ldo_vcn33_2_bt          vcn33_2_bt           *          5g      ldo_vcn33_2_wifi            vcn33_2_wifi             *          5g      ldo_va12            va12             O                    4      ldo_va09            va09             5           O      ldo_vrf18           vrf18                      P      ldo_vsram_md          	  vsram_md                                H  *                 ldo_vufs            vufs                                4           N      ldo_vm18            vm18                                4      ldo_vbbck           vbbck                      O      ldo_vsram_proc1         vsram_proc1                             H  L                    4      ldo_vsim2           vsim2                      /M`      ldo_vsram_others_sshub          vsram_others_sshub                               rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             *    p                            Dpmif spmimst            V   "      "       !   E      (  Gpmif_sys_ck pmif_tmr_ck spmimst_clk_mux         e   !   $        u   !                        +       mt6315@6              mediatek,mt6315-regulator           *          regulators     vbuck1          Vbcpu                      7                   H  j        ]                   4           
            mt6315@7              mediatek,mt6315-regulator           *          regulators     vbuck1          Vgpu                       7                   H  j        ]                                    infra-iommu@10315000              mediatek,mt8195-iommu-infra         *    1P       P       P                                                                           u              V      mailbox@10320000              mediatek,mt8195-gce         *    2        @                                          V   "                    mailbox@10330000              mediatek,mt8195-gce         *    3        @                                          V   "              }      scp@10500000              mediatek,mt8195-scp       0  *    P             r             p                 Dsram cfg l1tcm                               okay            mediatek/mt8195/scp.img            3        default            4           ~   cros-ec-rpmsg             google,cros-ec-rpmsg            cros-ec-rpmsg            clock-controller@10720000             mediatek,mt8195-scp_adsp            *    r                 I              5      dsp@10803000              mediatek,mt8195-dsp          *    0                           	  Dcfg sram          ,  V   !   X      !   n   !      5       !   #      K  Gadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             6           rx tx              7   8        okay               9   :                 mailbox@10816000              mediatek,mt8195-adsp-mbox                       *    `                                        7      mailbox@10817000              mediatek,mt8195-adsp-mbox                       *    p                                        8      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           *                        !           6                 6                  ;         	  audiosys            V                    !      !      !      !      !      !   g   !   "   !   #   !   n   !   e   !   a   !   b   !   c   !   d   "   2   5            Gclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          okay                       #               <                 serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                                           V      "         	  Gbaud bus            okay          serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                                           V      "         	  Gbaud bus          	  disabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                                           V      "         	  Gbaud bus          	  disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                                          V      "         	  Gbaud bus          	  disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                                          V      "         	  Gbaud bus          	  disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                                          V      "         	  Gbaud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           *                      V   "           Gmain                       okay                     syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           *     0                I              1      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *                                           V   !      !      "           Gparent-clk sel-clk spi-clk          okay            default            =        D       ec@0                         +              google,cros-ec-spi          *                             default            >        X -         j   i2c-tunnel            google,cros-ec-i2c-tunnel           x                         +       sbs-battery@b             sbs,sbs-battery         *                                  regulator@0           google,cros-ec-regulator            *            mt_pmic_vmc_ldo          O          6           R      regulator@1           google,cros-ec-regulator            *           mt_pmic_vmch_ldo             )2          6           Q      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector         *            dual            host            source        connector@1           usb-c-connector         *           dual            host            source           keyboard-controller           google,cros-ec-keyb                                     D     t x c  	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      4  !               	  	                        thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         *                                           V   "              "            6   ?   @      $  Blvts-calib-data-1 lvts-calib-data-2         S                    svs@1100bc00              mediatek,mt8195-svs         *                                           V   "           Gmain            6   A   ?      (  Bsvs-calibration-data t-calibration-data            "           svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           *                                              6           i           V   !   *   "   0        Gmain mm         okay            default            B                 pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           *                                          i           V   !   +   "   N        Gmain mm       	  disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *                                           V   !      !      "   3        Gparent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *                                           V   !      !      "   4        Gparent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *    0                                      V   !      !      "   5        Gparent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *                                          V   !      !      "   <        Gparent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *                                          V   !      !      "   =        Gparent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave           *                                          V   "   R        Gspi         e   !           u   !         	  disabled          spi@1101e000              mediatek,mt8195-spi-slave           *                                          V   "   S        Gspi         e   !           u   !         	  disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           *           @                              tmacirq        .  Gaxi apb mac_main ptp_ref rmii_internal mac_cg         0  V   1       1      !   R   !   S   !   T   1           e   !   R   !   S   !   T        u   !      !      !              6              "           C           D           E                                        	  disabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config                                 	                                    C      rx-queues-config            	            	.           D   queue0           	?        	R          queue1           	?        	R          queue2           	?        	R          queue3           	?        	R             tx-queues-config            	j            	           E   queue0          	            	?        	          queue1          	            	?        	         queue2          	            	?        	         queue3          	            	?        	               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           *            -     >              	  Dmac ippc                                 ?                      +                                 V   "   /   !      "   B        Gsys_ck ref_ck mcu_ck            	   F      G            j        	   H      g        okay            	host            	   I   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          *                       Dmac                               e   !   ,   !   -        u   !      !         $  V   "   /   !                "   B      $  Gsys_ck ref_ck mcu_ck dma_ck xhci_ck         okay            	           	   J         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          *    #                                                    V   !      "      "           Gsource hclk source_cg           okay            	            
         
        
% L        \          
4         
C         
R         
Z         
`        default state_uhs              K        
n   L        
x   M        
   N      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          *    $                                                    V   !      "      "   $        Gsource hclk source_cg           e   !           u   !           okay            	            
        
      6           \          
         
R        default state_uhs              O   P        
n   O         
         
        
x   Q        
   R      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          *    %                                                    V   !       "      "   I        Gsource hclk source_cg           e   !            u   !         	  disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            *    '                                      V   "              "           6   ?   @      $  Blvts-calib-data-1 lvts-calib-data-2         S                    usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           *    )             )>              	  Dmac ippc                                 	   S           e   !   .   !   /        u   !      !         $  V   1      !                1         $  Gsys_ck ref_ck mcu_ck dma_ck xhci_ck         	   H      h         j        okay            	           	   I        	   J        
         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           *    *       -    *>              	  Dmac ippc                        *        ?                      +                                e   !   0        u   !           V   1      !      1           Gsys_ck ref_ck mcu_ck            	   T            j        	   H      i        okay            	host            	   I   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          *                       Dmac                              e   !   1        u   !           V   1           Gsys_ck          okay            	   J         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           *    +       -    +>              	  Dmac ippc                        +        ?                      +                                e   !   2        u   !           V   1      !      1   	        Gsys_ck ref_ck mcu_ck            	   U            j        	   H      j        okay            	host            	   I   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          *                       Dmac                              e   !   3        u   !           V   1   	        Gsys_ck          okay             
        	   J         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           *    /        @       	  Dpcie-mac                                 
             8                                                              
       V                        0  V   "   V   "   #   "   &   "   +   "   K   1         /  Gpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          e   !   G        u   !           	   W      	  pcie-phy               6                                             `  3                  X                      X                     X                     X         	  disabled       interrupt-controller                                                X         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           *    /       @       	  Dpcie-mac                                 
             8         $       $                  $       $                 
       V                        (  V   "   W      "   X      "   Q   1         /  Gpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          e   !   H        u   !           	   Y         	  pcie-phy               6                                            `  3                  Z                      Z                     Z                     Z           okay            default            [   interrupt-controller                                                Z         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         *    2                      9               V   !   o   1      1           Gspi sf axi                       +            okay            default            \   flash@0           jedec,spi-nor           *            Xu         A           R            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            *                                  +      usb3-tx-imp@184,1           *             c                  s      usb3-rx-imp@184,2           *             c                 r      usb3-intr@185           *             c                 q      usb3-tx-imp@186,1           *             c                  p      usb3-rx-imp@186,2           *             c                 o      usb3-intr@187           *             c                 n      usb2-intr-p0@188,1          *             c             usb2-intr-p1@188,2          *             c            usb2-intr-p2@189,1          *             c            usb2-intr-p3@189,2          *             c            pciephy-rx-ln1@190,1            *             c                  z      pciephy-tx-ln1-nmos@190,2           *             c                 y      pciephy-tx-ln1-pmos@191,1           *             c                  x      pciephy-rx-ln0@191,2            *             c                 w      pciephy-tx-ln0-nmos@192,1           *             c                  v      pciephy-tx-ln0-pmos@192,2           *             c                 u      pciephy-glb-intr@193            *             c                  t      dp-data@1ac         *                      lvts1-calib@1bc         *                ?      lvts2-calib@1d0         *     8           @      svs-calib@580           *     d           A      socinfo-data1@7a0           *              t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0           *               V   !           Gref         h              T         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0           *               V   !           Gref         h              U         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         *                     V           rmipi_tx0_pll            I            h          	  disabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         *                     V           rmipi_tx1_pll            I            h          	  disabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *                 "                                     ]           V   ]       "   ;      	  Gmain dma                         +            okay            P         default            ^      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *                "                                      ]           V   ]      "   ;      	  Gmain dma                         +          	  disabled          i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *                 "                                     ]           V   ]      "   ;      	  Gmain dma                         +            okay            P         default            _   pmic@34                      mediatek,mt6360         *   4                                  tIRQB            default            `         j         clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          *    0                I              ]      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *                 "                                      ]           V   a       "   ;      	  Gmain dma                         +            okay            P         default            b      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *                "                                      ]           V   a      "   ;      	  Gmain dma                         +            okay            P         s  0        default            c   trackpad@15           elan,ekth3000           *                            default            d           e         j         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *                 "                                     ]           V   a      "   ;      	  Gmain dma                         +            okay            P         default            f   codec@1a            *                 Y                                    g           h           i          realtek,rt5682s                                i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    0            "                                     ]           V   a      "   ;      	  Gmain dma                         +            okay            P         default            j   tpm@50            google,cr50         *   P              X           default            k         i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    @            "                                      ]           V   a      "   ;      	  Gmain dma                         +            okay            P         default            l   touchscreen@10            hid-over-i2c            *                            \           default            m           
           e        okay             clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          *    P                I              a      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                   6           okay       usb-phy@0           *               V   !              Gref da_ref          h              S      usb-phy@700         *              V          !           Gref da_ref          6   n   o   p        Bintr rx_imp tx_imp          h              Y         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0           *               V   !              Gref da_ref          h              F      usb-phy@700         *              V          !           Gref da_ref          6   q   r   s        Bintr rx_imp tx_imp          h              G         phy@11e80000              mediatek,mt8195-pcie-phy            *                     Dsif         6   t   u   v   w   x   y   z      G  Bglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             6           h          	  disabled               W      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           *                     V            
  Gunipro mp           h          	  disabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           *             @         V   {          0                                                 tjob mmu gpu         %   |      (     6   
   6      6      6      6           9core0 core1 core2 core3 core4           okay            L         clock-controller@13fbf000             mediatek,mt8195-mfgcfg          *                    I              {      syscon@14000000           mediatek,mt8195-vppsys0 syscon          *                      I           X   }                      $      dma-controller@14001000           mediatek,mt8195-mdp3-rdma           *                     X   }                  p                 ~           6                         V   $         <     }         }         }         }         }                       display@14002000              mediatek,mt8195-mdp3-fg         *                      X   }                   V   $          display@14003000              mediatek,mt8195-mdp3-stitch         *     0                X   }      0            V   $         display@14004000              mediatek,mt8195-mdp3-hdr            *     @                X   }      @            V   $   "      display@14005000              mediatek,mt8195-mdp3-aal            *     P                      F               X   }      P            V   $   
           6         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           *     `                X   }      `            p    %        V   $         display@14007000              mediatek,mt8195-mdp3-tdshp          *     p                X   }      p            V   $   #      display@14008000              mediatek,mt8195-mdp3-color          *                           I               X   }                  V   $   $           6         display@14009000              mediatek,mt8195-mdp3-ovl            *                           J               X   }                  V   $   %           6                       display@1400a000              mediatek,mt8195-mdp3-padding            *                     X   }                  V   $              6         display@1400b000              mediatek,mt8195-mdp3-tcc            *                     X   }                  V   $         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         *                     X   }                  p    +        V   $                            6                    mutex@1400f000            mediatek,mt8195-vpp-mutex           *                           P               X   }                  V   $              6         smi@14010000              mediatek,mt8195-smi-sub-common          *                     V   $      $      $           Gapb smi gals0                         6                    smi@14011000              mediatek,mt8195-smi-sub-common          *                    V   $      $      $           Gapb smi gals0                         6                    smi@14012000              mediatek,mt8195-smi-common-vpp          *                      V   $      $      $      $           Gapb smi gals0 gals1            6                    larb@14013000             mediatek,mt8195-smi-larb            *    0                                      V   $      $           Gapb smi            6                    iommu@14018000            mediatek,mt8195-iommu-vpp           *                  8                                                          R               V   $           Gbclk            u              6                    clock-controller@14e00000             mediatek,mt8195-wpesys          *                     I              '      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         *                     I         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         *    0                I         larb@14e04000             mediatek,mt8195-smi-larb            *    @                                      V   '      '           Gapb smi            6                    larb@14e05000             mediatek,mt8195-smi-larb            *    P                                      V   '      '      $           Gapb smi gals               6                    syscon@14f00000           mediatek,mt8195-vppsys1 syscon          *                     I           X   }   	                  &      mutex@14f01000            mediatek,mt8195-vpp-mutex           *                          {               X   }   	              V   &   '           6         larb@14f02000             mediatek,mt8195-smi-larb            *                                           V   &      &      $           Gapb smi gals               6                    larb@14f03000             mediatek,mt8195-smi-larb            *    0                                      V   &      &      $           Gapb smi gals               6                    display@14f06000              mediatek,mt8195-mdp3-split          *    `                X   }   	  `            V   &      &   +   &   ,           6         display@14f07000              mediatek,mt8195-mdp3-tcc            *    p                X   }   	  p            V   &         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           *                    X   }   	              p            V   &                            6                    dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           *                    X   }   	              p            V   &   
                         6                    dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           *                    X   }   	              p            V   &                            6                    display@14f0b000              mediatek,mt8195-mdp3-fg         *                    X   }   	              V   &   	      display@14f0c000              mediatek,mt8195-mdp3-fg         *                    X   }   	              V   &         display@14f0d000              mediatek,mt8195-mdp3-fg         *                    X   }   	              V   &         display@14f0e000              mediatek,mt8195-mdp3-hdr            *                    X   }   	              V   &         display@14f0f000              mediatek,mt8195-mdp3-hdr            *                    X   }   	              V   &         display@14f10000              mediatek,mt8195-mdp3-hdr            *                     X   }   
               V   &          display@14f11000              mediatek,mt8195-mdp3-aal            *                          i               X   }   
              V   &              6         display@14f12000              mediatek,mt8195-mdp3-aal            *                           j               X   }   
               V   &              6         display@14f13000              mediatek,mt8195-mdp3-aal            *    0                      k               X   }   
  0            V   &   !           6         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           *    @                X   }   
  @            p            V   &         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           *    P                X   }   
  P            p            V   &   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           *    `                X   }   
  `            p            V   &   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          *    p                X   }   
  p            V   &         display@14f18000              mediatek,mt8195-mdp3-tdshp          *                    X   }   
              V   &   (      display@14f19000              mediatek,mt8195-mdp3-tdshp          *                    X   }   
              V   &   )      display@14f1a000              mediatek,mt8195-mdp3-merge          *                    X   }   
              V   &              6         display@14f1b000              mediatek,mt8195-mdp3-merge          *                    X   }   
              V   &              6         display@14f1c000              mediatek,mt8195-mdp3-color          *                          t               X   }   
              V   &              6         display@14f1d000              mediatek,mt8195-mdp3-color          *                    X   }   
                    u               V   &              6         display@14f1e000              mediatek,mt8195-mdp3-color          *                          v               X   }   
              V   &              6         display@14f1f000              mediatek,mt8195-mdp3-ovl            *                          w               X   }   
              V   &               6                       display@14f20000              mediatek,mt8195-mdp3-padding            *                     X   }                  V   &              6         display@14f21000              mediatek,mt8195-mdp3-padding            *                    X   }                 V   &              6         display@14f22000              mediatek,mt8195-mdp3-padding            *                     X   }                  V   &              6         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         *    0                X   }     0            p            V   &                            6                    dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         *    @                X   }     @            p            V   &                            6                    dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         *    P                X   }     P            p            V   &                            6                    clock-controller@15000000             mediatek,mt8195-imgsys          *                      I              .      larb@15001000             mediatek,mt8195-smi-larb            *                        	                   V   .       .       .   
        Gapb smi gals               6                    smi@15002000              mediatek,mt8195-smi-sub-common          *                      V   .      .      $           Gapb smi gals0                         6                    smi@15003000              mediatek,mt8195-smi-sub-common          *     0                V   .       .       .   
        Gapb smi gals0                         6                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         *                     I                    larb@15120000             mediatek,mt8195-smi-larb            *                        
                   V   .                  Gapb smi            6                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          *                     I         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         *    "                 I                    larb@15230000             mediatek,mt8195-smi-larb            *    #                                       V   .                  Gapb smi            6                    clock-controller@15330000             mediatek,mt8195-ipesys          *    3                 I              /      larb@15340000             mediatek,mt8195-smi-larb            *    4                                       V   /      /           Gapb smi            6                    clock-controller@16000000             mediatek,mt8195-camsys          *                      I              0      larb@16001000             mediatek,mt8195-smi-larb            *                                           V   0       0       0           Gapb smi gals               6                    larb@16002000             mediatek,mt8195-smi-larb            *                                            V   0      0           Gapb smi            6                    smi@16004000              mediatek,mt8195-smi-sub-common          *     @                V   0       0       0           Gapb smi gals0                         6                    smi@16005000              mediatek,mt8195-smi-sub-common          *     P                V   0      0      $           Gapb smi gals0                         6                    larb@16012000             mediatek,mt8195-smi-larb            *                                           V                      Gapb smi            6                     larb@16013000             mediatek,mt8195-smi-larb            *    0                                      V                      Gapb smi            6                     larb@16014000             mediatek,mt8195-smi-larb            *    @                                      V                      Gapb smi            6   !                 larb@16015000             mediatek,mt8195-smi-larb            *    P                                      V                      Gapb smi            6   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa         *                    I                    clock-controller@1606f000             mediatek,mt8195-camsys_yuva         *                    I                    clock-controller@1608f000             mediatek,mt8195-camsys_rawb         *                    I                    clock-controller@160af000             mediatek,mt8195-camsys_yuvb         *    
                I                    clock-controller@16140000             mediatek,mt8195-camsys_mraw         *                     I                    larb@16141000             mediatek,mt8195-smi-larb            *                                          V   0              0           Gapb smi gals               6   "                 larb@16142000             mediatek,mt8195-smi-larb            *                                           V                      Gapb smi            6   "                 clock-controller@17200000             mediatek,mt8195-ccusys          *                      I                    larb@17201000             mediatek,mt8195-smi-larb            *                                           V                      Gapb smi            6                    video-codec@18000000              mediatek,mt8195-vcodec-dec             ~                                  +            *                   @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         *                                          V   !   A   (      (      !           Gsel vdec lat top            e   !   A        u   !              6         video-codec@10000             mediatek,mtk-vcodec-lat         *                                         0                                          V   !   A   (      (      !           Gsel vdec lat top            e   !   A        u   !              6         video-codec@25000             mediatek,mtk-vcodec-core            *     P                                   P                                                             V   !   A   )      )      !           Gsel vdec lat top            e   !   A        u   !              6            larb@1800d000             mediatek,mt8195-smi-larb            *                                           V   (       (            Gapb smi            6                    larb@1800e000             mediatek,mt8195-smi-larb            *                                           V   $      (            Gapb smi            6                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         *                     I              (      larb@1802e000             mediatek,mt8195-smi-larb            *                                          V   )       )            Gapb smi            6                    clock-controller@1802f000             mediatek,mt8195-vdecsys         *                    I              )      larb@1803e000             mediatek,mt8195-smi-larb            *                                          V   $      *            Gapb smi            6                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           *                    I              *      clock-controller@190f3000             mediatek,mt8195-apusys_pll          *    0                I         clock-controller@1a000000             mediatek,mt8195-vencsys         *                      I              +      larb@1a010000             mediatek,mt8195-smi-larb            *                                           V   +      +           Gapb smi            6                    video-codec@1a020000              mediatek,mt8195-vcodec-enc          *                   H       `     a     b     c     d     v     w     x     y              U                  ~        V   +         	  Gvenc_sel            e   !   @        u   !              6                        +         jpgdec-master             mediatek,mt8195-jpgdec             6         0       m     n     r     s     t     u                     +               jpgdec@1a040000           mediatek,mt8195-jpgdec-hw           *                   0       m     n     r     s     t     u              W               V   +           Gjpgdec             6         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw           *                   0       m     n     r     s     t     u              X               V   +           Gjpgdec             6         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw           *                   0                                              \               V   ,           Gjpgdec             6            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           *                      I              ,      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            *                                      I           X                       %      jpgenc-master             mediatek,mt8195-jpgenc             6                                                     +               jpgenc@1a030000           mediatek,mt8195-jpgenc-hw           *                           g     h     i     l              V               V   +           Gjpgenc             6         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw           *                                                        [               V   ,           Gjpgenc             6            larb@1b010000             mediatek,mt8195-smi-larb            *                                           V   ,      ,      $            Gapb smi gals               6                    ovl@1c000000              mediatek,mt8195-disp-ovl            *                            |                  6           V   %                          X                   rdma@1c002000             mediatek,mt8195-disp-rdma           *                            ~                  6           V   %                          X                   color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           *     0                                        6           V   %           X        0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           *     @                                        6           V   %           X        @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           *     P                                        6           V   %           X        P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           *     `                                        6           V   %           X        `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         *     p                                        6           V   %   	        X        p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         *                                             6           V   %      %   *           Gengine digital hs           	           dphy          	  disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            *                                             6           V   %           X                  dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         *                                             6           V   %      %   +           Gengine digital hs           	           dphy          	  disabled          merge@1c014000            mediatek,mt8195-disp-merge          *    @                                        6           V   %           X        @          dp-intf@1c015000              mediatek,mt8195-dp-intf         *    P                                     V   %   ,   %                  Gpixel engine pll            okay       port       endpoint                                      mutex@1c016000            mediatek,mt8195-disp-mutex          *    `                                        6           V   %           X        `            p  U      larb@1c018000             mediatek,mt8195-smi-larb            *                                           V   %   (   %   (   $           Gapb smi gals               6                    larb@1c019000             mediatek,mt8195-smi-larb            *                                          V   %   (   $       $           Gapb smi gals               6                    syscon@1c100000           mediatek,mt8195-vdosys1 syscon          *                                      X                     I           7              -      smi@1c01b000              mediatek,mt8195-smi-common-vdo          *                     V   %   %   %   &   %   )   %   $        Gapb smi gals0 gals1            6                    iommu@1c01f000            mediatek,mt8195-iommu-vdo           *                  8                                                                         u           V   %   '        Gbclk               6                    mutex@1c101000            mediatek,mt8195-disp-mutex          *                                            6           V   -           X                    p        larb@1c102000             mediatek,mt8195-smi-larb            *                                           V   -       -       -           Gapb smi gals               6                    larb@1c103000             mediatek,mt8195-smi-larb            *    0                                      V   -      -      $            Gapb smi gals               6                    dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           *    @                                     V   -              6                 @        X        @                     dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           *    P                                     V   -              6                 `        X        P                     dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           *    `                                     V   -              6                 A        X        `                     dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           *    p                                     V   -              6                 a        X        p                     dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           *                                         V   -              6                 B        X                             dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           *                                         V   -              6                 b        X                             dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           *                                         V   -              6                 C        X                             dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           *                                         V   -              6                 c        X                             vpp-merge@1c10c000            mediatek,mt8195-disp-merge          *                                         V   -   	   -           Gmerge merge_async              6           X                                -         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          *                                         V   -   
   -           Gmerge merge_async              6           X                                -         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          *                                         V   -      -           Gmerge merge_async              6           X                                -         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          *                                         V   -      -           Gmerge merge_async              6           X                                -         vpp-merge@1c110000            mediatek,mt8195-disp-merge          *                                          V   -      -           Gmerge merge_async              6           X                                 -         dp-intf@1c113000              mediatek,mt8195-dp-intf         *    0                                        6           V   -   /   -                  Gpixel engine pll            okay       port       endpoint                                      hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  *    @            P            p                                                              4  Dmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  X        @            P            p                                                          h  V   -   %   -       -   #   -   !   -   $   -   "   -   1   -   &   -   '   -   (   -   )   -   *   !           Gmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             6                 d      e                           (     -   3   -   4   -   5   -   6   -   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx          *    P                 6           Bdp_calibration_data            6                                          okay            default               ports                        +       port@0          *       endpoint                                   port@1          *      endpoint                                                           aux-bus    panel         
    edp-panel           '           4      port       endpoint                                            dp-tx@1c600000            mediatek,mt8195-dp-tx           *    `                 6           Bdp_calibration_data            6                                          okay                        default                          ports                        +       port@0          *       endpoint                                   port@1          *      endpoint                                           thermal-zones      cpu0-thermal            >          L           b         trips      trip-alert          r L        ~          %passive                  trip-crit           r         ~        	  %critical             cooling-maps       map0                     0                          cpu1-thermal            >          L           b         trips      trip-alert          r L        ~          %passive                  trip-crit           r         ~        	  %critical             cooling-maps       map0                     0                          cpu2-thermal            >          L           b         trips      trip-alert          r L        ~          %passive                  trip-crit           r         ~        	  %critical             cooling-maps       map0                     0                          cpu3-thermal            >          L           b         trips      trip-alert          r L        ~          %passive                  trip-crit           r         ~        	  %critical             cooling-maps       map0                     0                          cpu4-thermal            >          L           b          trips      trip-alert          r L        ~          %passive                  trip-crit           r         ~        	  %critical             cooling-maps       map0                     0                          cpu5-thermal            >          L           b         trips      trip-alert          r L        ~          %passive                  trip-crit           r         ~        	  %critical             cooling-maps       map0                     0                          cpu6-thermal            >          L           b         trips      trip-alert          r L        ~          %passive                  trip-crit           r         ~        	  %critical             cooling-maps       map0                     0                          cpu7-thermal            >          L           b         trips      trip-alert          r L        ~          %passive                  trip-crit           r         ~        	  %critical             cooling-maps       map0                     0                          vpu0-thermal            >          L           b         trips      trip-alert          r L        ~          %passive       trip-crit           r         ~        	  %critical                vpu1-thermal            >          L           b      	   trips      trip-alert          r L        ~          %passive       trip-crit           r         ~        	  %critical                gpu-thermal         >          L           b      
   trips      trip-alert          r L        ~          %passive       trip-crit           r         ~        	  %critical                gpu1-thermal            >          L           b         trips      trip-alert          r L        ~          %passive       trip-crit           r         ~        	  %critical                vdec-thermal            >          L           b         trips      trip-alert          r L        ~          %passive       trip-crit           r         ~        	  %critical                img-thermal         >          L           b         trips      trip-alert          r L        ~          %passive       trip-crit           r         ~        	  %critical                infra-thermal           >          L           b         trips      trip-alert          r L        ~          %passive       trip-crit           r         ~        	  %critical                cam0-thermal            >          L           b         trips      trip-alert          r L        ~          %passive       trip-crit           r         ~        	  %critical                cam1-thermal            >          L           b         trips      trip-alert          r L        ~          %passive       trip-crit           r         ~        	  %critical                soc-area-thermal            >          L           b      trips      trip-crit           r H         ~        	  %critical                pmic-area-thermal           >          L            b      trips      trip-crit           r H         ~        	  %critical                   backlight-lcd0            pwm-backlight                           @              R                                       '                    chosen          serial0:115200n8          memory@40000000         memory          *    @                regulator-pp3300-disp-x           regulator-fixed         pp3300_disp_x            2Z          2Z          	                       7            default                       h                 regulator-pp3300-ldo-z5           regulator-fixed         pp3300_ldo_z5            4                   2Z          2Z                      i      regulator-pp3300-s3           regulator-fixed       
  pp3300_s3            4                   2Z          2Z           h           e      regulator-pp3300-z2           regulator-fixed       
  pp3300_z2            4                   2Z          2Z                      h      regulator-pp4200-z2           regulator-fixed       
  pp4200_z2            4                   @@          @@                 regulator-pp5000-s5           regulator-fixed       
  pp5000_s5            4                   LK@          LK@                 regulator-ppvar-sys           regulator-fixed       
  ppvar_sys            4                           thermal-sensor-t1             generic-adc-thermal         S            2               >sensor-channel          O  x        ~    %  '    :  [  N     a    u0        @  ]      P        `  G     p    $    8    L    _   } s   k    \ (   O    D 8   ;    3 H   ,                 thermal-sensor-t2             generic-adc-thermal         S            2              >sensor-channel          O  x        ~    %  '    :  [  N     a    u0        @  ]      P        `  G     p    $    8    L    _   } s   k    \ (   O    D 8   ;    3 H   ,                 regulator-5v0-usb-vbus            regulator-fixed       	  usb-vbus             LK@          LK@                  4           J      reserved-memory                      +               memory@50000000           shared-dma-pool         *    P                  h           3      memory@60000000           shared-dma-pool         *    `                   h           :      memory@60d80000           shared-dma-pool         *    `                  h           <      memory@60e80000           shared-dma-pool         *    `       (           h           9         rt1019p           realtek,rt1019p         ort1019p                     default                    u      d                        	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c7 mmc0 mmc1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform mediatek,adsp mediatek,dai-link pinctrl-names pinctrl-0 audio-routing link-name mediatek,clk-provider sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit gpio-line-names pinmux input-enable bias-pull-up bias-disable drive-strength-microamp drive-strength bias-pull-down output-high output-low #power-domain-cells domain-supply clock-names mediatek,infracfg assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells firmware-name memory-region mediatek,rpmsg-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names mediatek,etdm-in2-cowork-source mediatek,etdm-out2-cowork-source mediatek,pad-select spi-max-frequency wakeup-source google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode vusb33-supply rx-fifo-depth vbus-supply bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable pinctrl-1 vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 mediatek,u3p-dis-msk usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells i2c-scl-internal-delay-ns vcc-supply #sound-dai-cells realtek,jd-src AVDD-supply MICVDD-supply VBAT-supply realtek,amic-delay-ms hid-descr-addr post-power-on-delay-ms vdd-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes power-supply backlight polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device brightness-levels default-brightness-level enable-gpios num-interpolated-steps pwms stdout-path enable-active-high gpio vin-supply regulator-boot-on io-channels io-channel-names temperature-lookup-table no-map label sdb-gpios 