 C   8 9x   (            
 9@                             %    mediatek,mt8195-demo mediatek,mt8195                                     +            7MediaTek MT8195 demo board     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/serial@11001100          cpus                         +       cpu@0            cpu           arm,cortex-a55                       psci                           #ec3@        3  4        F              V           c   @        u                         @                                            	      cpu@100          cpu           arm,cortex-a55                      psci                           #ec3@        3  4        F              V           c   @        u                         @                                            
      cpu@200          cpu           arm,cortex-a55                      psci                           #ec3@        3  4        F              V           c   @        u                         @                                                  cpu@300          cpu           arm,cortex-a55                      psci                           #ec3@        3  4        F              V           c   @        u                         @                                                  cpu@400          cpu           arm,cortex-a78                      psci                          #f        3           F              V           c   @        u                         @                                                  cpu@500          cpu           arm,cortex-a78                      psci                          #f        3           F              V           c   @        u                         @                                                  cpu@600          cpu           arm,cortex-a78                      psci                          #f        3           F              V           c   @        u                         @                                                  cpu@700          cpu           arm,cortex-a78                      psci                          #f        3           F              V           c   @        u                         @                                                  cpu-map    cluster0       core0              	      core1              
      core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                                2            _        0  D                 cpu-retention-b           arm,idle-state                                -                    0                   cpu-off-l             arm,idle-state                               7                    0  H                 cpu-off-b             arm,idle-state                               2                    0                      l2-cache0             cache           A           X           e   @        w                       M                 l2-cache1             cache           A           X           e   @        w                       M                 l3-cache              cache           A           X            e   @        w            M                    dsu-pmu           arm,dsu-pmu         [                       f   	   
                          kfail          dmic-codec            dmic-codec          r              2      mt8195-sound                     	  kdisabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             (      oscillator-26m            fixed-clock                     #        clk26m                   oscillator-32k            fixed-clock                     #           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw                            0                                   opp-table-gpu             operating-points-v2                     `   opp-390000000               >        	 	h      opp-410000000               p        	 	      opp-431000000                       	 	      opp-473000000               1h@        	 	<      opp-515000000               F        	 	<      opp-556000000               !#         	 	Ҧ      opp-598000000               #        	 	      opp-640000000               &%         	 	      opp-670000000               'c        	 
      opp-700000000               )'         	 
L      opp-730000000               +        	 
}      opp-760000000               -L         	 
`      opp-790000000               /q        	 
4      opp-820000000               05         	       opp-850000000               2        	 @      opp-880000000               4s         	 q         pmu-a55           arm,cortex-a55-pmu                      [                  pmu-a78           arm,cortex-a78-pmu                      [                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  [                                             
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3          )           :                        Q                                              [      	                     ppi-partitions     interrupt-partition-0           f   	   
                       interrupt-partition-1           f                                   syscon@10000000            mediatek,mt8195-topckgen syscon                                                    syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                                           o                    syscon@10003000           mediatek,mt8195-pericfg syscon                0                              ;      pinctrl@10005000              mediatek,mt8195-pinctrl               P                                                                                                         B  |iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                                                      Q        [                      )                 eth-default-pins               7   pins-txd              M  N  O  P                 pins-cc           U  X  W  V                 pins-rxd              Q  R  S  T      pins-mdio             Y  Z               pins-power            [   \                   eth-sleep-pins             8   pins-txd              M   N   O   P       pins-cc           U   X   W   V       pins-rxd              Q   R   S   T       pins-mdio             Y   Z                            gpio-keys-pins                pins              j                   i2c6-pins              O   pins                                  mmc0-default-pins              >   pins-clk              z                      f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-rst              x                      e         mmc0-uhs-pins              ?   pins-clk              z                      f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-ds                                 f      pins-rst              x                      e         mmc1-default-pins              B   pins-clk              o                      f      pins-cmd-dat              n  p  q  r  s                               e      pins-insert                              mmc1-uhs-pins              C   pins-clk              o                      f      pins-cmd-dat              n  p  q  r  s                               e         uart0-pins             .   pins              b  c         uart1-pins             /   pins              f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8195-power-controller                         +                          *   power-domain@8                                   +                  power-domain@9              	                            (mfg alt         4                        +                  power-domain@10             
                  power-domain@11                               power-domain@12                               power-domain@13                               power-domain@14                                     power-domain@15                                             	      @      A      K                                                                                                                                (vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           4                        +                  power-domain@16                   8              $      %      &      '      (      )      D  (vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         4                        +                  power-domain@17                                               (vppsys1 vppsys1-0 vppsys1-1         4                     power-domain@22                                                    $  (wepsys-0 wepsys-1 wepsys-2 wepsys-3         4                     power-domain@23                                    (vdec0-0         4                        +                   power-domain@24                                    (vdec1-0         4                     power-domain@25                                     (vdec2-0         4                        power-domain@26                        !            (venc0-larb          4                        +                   power-domain@27                        "            (venc1-larb          4                        power-domain@18                               #       #      #         &  (vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           4                        +                  power-domain@19                     4                     power-domain@20                     4                     power-domain@21                           Q        (hdmi_tx                      power-domain@28                        $       $   
        (img-0 img-1         4                        +                  power-domain@29                               power-domain@30                              $      %           (ipe ipe-0 ipe-1         4                        power-domain@31                   (     &       &      &      &      &           (cam-0 cam-1 cam-2 cam-3 cam-4           4                        +                  power-domain@32                                power-domain@33             !                  power-domain@34             "                           power-domain@0                       4                     power-domain@1                      4                     power-domain@2                                power-domain@3                                power-domain@4                            5      7        (csi_rx_top csi_rx_top1                    power-domain@5                         '           (ether                     power-domain@6                            X      n        (adsp adsp1                       +            4                 power-domain@7                             g      "      n      2        (audio audio1 audio2 audio3          4                              watchdog@10007000             mediatek,mt8195-wdt          F              p                o              -      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                                                     timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer              p                [      	                  (      pwrap@10024000            mediatek,mt8195-pwrap syscon                 @                |pwrap           [                                         	  (spi wrap            ^      $        n         pmic              mediatek,mt6359          Q        )                       adc           mediatek,mt6359-auxadc                   mt6359codec       regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !                           buck_vgpu11         vgpu11                    7                             /                         buck_vmodem         vmodem                              *                 buck_vpu            vpu                   7                             /                         buck_vcore          vcore                                                   /                         buck_vs2            vs2          5          j                            buck_vpa            vpa                    7          ,      buck_vproc2         vproc2                    7          L                   /                         buck_vproc1         vproc1                    7          L                   /                         buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@                 ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z      ldo_vrf12           vrf12                                     ldo_vusb            vusb             -         -                              <      ldo_vsram_proc2         vsram_proc2                              L                          ldo_vio18           vio18                                              ldo_vcamio          vcamio                          ldo_vcn18           vcn18            w@         w@                 ldo_vfe28           vfe28            *         *           x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@                          ldo_vsram_others            vsram_others                                                           ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !               ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *                 ldo_vio28           vio28            *         2Z               ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z           @      ldo_vcn33_2_bt          vcn33_2_bt           *         5g      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                         ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                                 *                          ldo_vufs            vufs                                 A      ldo_vm18            vm18                                     ldo_vbbck           vbbck                     O               ldo_vsram_proc1         vsram_proc1                              L                          ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi                  p                            |pmif spmimst                               E      (  (pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         ^      $        n            infra-iommu@10315000              mediatek,mt8195-iommu-infra              1P       P       P  [                                                                         G              J      mailbox@10320000              mediatek,mt8195-gce              2        @         [                      T                                  mailbox@10330000              mediatek,mt8195-gce              3        @         [                      T                            a      scp@10500000              mediatek,mt8195-scp       0       P             r             p                 |sram cfg l1tcm          [                   	  kdisabled               b      clock-controller@10720000             mediatek,mt8195-scp_adsp                 r                               )      dsp@10803000              mediatek,mt8195-dsp               0                           	  |cfg sram          ,        X         n         )          #      K  (adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          `   *           nrx tx           y   +   ,      	  kdisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           T                 `                [                        +      mailbox@10817000              mediatek,mt8195-adsp-mbox           T                 p                [                        ,      mt8195-afe-pcm@10890000           mediatek,mt8195-audio                                            `   *           [      6                  -         	  audiosys                                                               g      "      #      n      e      a      b      c      d      2   )            (clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  kdisabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                     	  (baud bus            kokay            default            .      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                     	  (baud bus            kokay            default            /      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                     	  (baud bus          	  kdisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                    	  (baud bus          	  kdisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                    	  (baud bus          	  kdisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                    	  (baud bus          	  kdisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                                (main                     	  kdisabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                 0                              '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  [                                                (parent-clk sel-clk spi-clk        	  kdisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap                               [                                                      0   1      $  lvts-calib-data-1 lvts-calib-data-2                             svs@1100bc00              mediatek,mt8195-svs                               [                                    (main               2   0      (  svs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                 [                      `   *                            *      0        (main mm       	  kdisabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                 [                                      +      N        (main mm       	  kdisabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  [                                        3        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  [                                        4        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                 0                [                                        5        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 [                                        <        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 [                                        =        (parent-clk sel-clk spi-clk        	  kdisabled          spi@1101d000              mediatek,mt8195-spi-slave                                [                            R        (spi         ^              n            	  kdisabled          spi@1101e000              mediatek,mt8195-spi-slave                                [                            S        (spi         ^              n            	  kdisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                       @         [                     macirq        .  (axi apb mac_main ptp_ref rmii_internal mac_cg         0     '       '         R      S      T   '           ^      R      S      T        n                          `   *                         3        ,   4        ?   5        R           ]           h            kokay          	  urgmii-id            ~   6              ]                  ' 8        default sleep              7           8   mdio              snps,dwmac-mdio                      +       ethernet-phy@1                         6         stmmac-axi-config                                                                     3      rx-queues-config                                   4   queue0           	                  queue1           	                  queue2           	                  queue3           	                     tx-queues-config            4            J           5   queue0          \            	        h          queue1          \            	        h         queue2          \            	        h         queue3          \            	        h               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                        -     >              	  |mac ippc                                 ?                      +           [                            /            B        (sys_ck ref_ck mcu_ck            v   9      :            {           ;      g        kokay               <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                  |mac         [                      ^      ,      -        n                  $        /                     B      $  (sys_ck ref_ck mcu_ck dma_ck xhci_ck         kokay               =         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc               #                              [                                                (source hclk source_cg           kokay            default state_uhs              >           ?                                                                                  ! L        0   @        <   A         I      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc               $                              [                                        $        (source hclk source_cg           ^              n              kokay            default state_uhs              B           C        W                                      `         q         ~        0   D        <   E      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc               %                              [                                         I        (source hclk source_cg           ^               n            	  kdisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                 '                [                                                     0   1      $  lvts-calib-data-1 lvts-calib-data-2                             usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci                )             )>              	  |mac ippc            [                     v   F      G           ^      .      /        n                  $     '                     '         $  (sys_ck ref_ck mcu_ck dma_ck xhci_ck            ;      h         {        kokay               <      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3                *       -    *>              	  |mac ippc                        *        ?                      +           [                     ^      0        n                 '            '           (sys_ck ref_ck mcu_ck            v   H            {           ;      i        kokay               <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                  |mac         [                     ^      1        n                 '           (sys_ck          kokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3                +       -    +>              	  |mac ippc                        +        ?                      +           [                     ^      2        n                 '            '   	        (sys_ck ref_ck mcu_ck            v   I            {           ;      j        kokay               <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                  |mac         [                     ^      3        n                 '   	        (sys_ck          kokay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +                /        @       	  |pcie-mac            [                                  8                                                                     J                        0        V      #      &      +      K   '         /  (pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ^      G        n              v   K      	  pcie-phy            `   *            )                                `                    L                      L                     L                     L         	  kdisabled       interrupt-controller             Q                     )              L         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +                /       @       	  |pcie-mac            [                                  8         $       $                  $       $                        J                        (        W         X         Q   '         /  (pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ^      H        n              v   G         	  pcie-phy            `   *           )                                `                    M                      M                     M                     M         	  kdisabled       interrupt-controller             Q                     )              M         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor              2                [      9                     o   '      '           (spi sf axi                       +          	  kdisabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                                               +      usb3-tx-imp@184,1                                           W      usb3-rx-imp@184,2                                          V      usb3-intr@185                                          U      usb3-tx-imp@186,1                                           T      usb3-rx-imp@186,2                                          S      usb3-intr@187                                          R      usb2-intr-p0@188,1                                     usb2-intr-p1@188,2                                    usb2-intr-p2@189,1                                    usb2-intr-p3@189,2                                    pciephy-rx-ln1@190,1                                            ^      pciephy-tx-ln1-nmos@190,2                                          ]      pciephy-tx-ln1-pmos@191,1                                           \      pciephy-rx-ln0@191,2                                           [      pciephy-tx-ln0-nmos@192,1                                           Z      pciephy-tx-ln0-pmos@192,2                                          Y      pciephy-glb-intr@193                                            X      dp-data@1ac                                lvts1-calib@1bc                          0      lvts2-calib@1d0               8           1      svs-calib@580                 d           2      socinfo-data1@7a0                          t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                kokay       usb-phy@0                                         (ref                       H         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                kokay       usb-phy@0                                         (ref                       I         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                          mipi_tx0_pll                                  	  kdisabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                          mipi_tx1_pll                                  	  kdisabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "               [                                    N          ;      	  (main dma                         +          	  kdisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                [                                    N         ;      	  (main dma                         +            kokay            #            O        default    pmic@34           mediatek,mt6360             4         Q        )                 e           IRQB       charger           mediatek,mt6360-chg          @   usb-otg-vbus-regulator          usb-otg-vbus             C(         X           =         regulator             mediatek,mt6360-regulator           	   P   buck1           mt6360,buck1                               /                         buck2           mt6360,buck2                               /                              P      ldo1            mt6360,ldo1          O         6        /             ldo2            mt6360,ldo2          O         6        /             ldo3            mt6360,ldo3          O         6        /                  E      ldo5            mt6360,ldo5          )2         6        /                  D      ldo6            mt6360,ldo6                              /             ldo7            mt6360,ldo7                              /                               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "               [                                    N         ;      	  (main dma                         +          	  kdisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s               0                              N      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "                [                                    Q          ;      	  (main dma                         +          	  kdisabled          i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                [                                    Q         ;      	  (main dma                         +          	  kdisabled          i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "               [                                    Q         ;      	  (main dma                         +          	  kdisabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c               0            "               [                                    Q         ;      	  (main dma                         +          	  kdisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c               @            "                [                                    Q         ;      	  (main dma                         +          	  kdisabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w               P                              Q      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                `   *           kokay       usb-phy@0                                            (ref da_ref                        F      usb-phy@700                                            (ref da_ref             R   S   T        intr rx_imp tx_imp                        G         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                kokay       usb-phy@0                                            (ref da_ref                        9      usb-phy@700                                            (ref da_ref             U   V   W        intr rx_imp tx_imp                        :         phy@11e80000              mediatek,mt8195-pcie-phy                                  |sif            X   Y   Z   [   \   ]   ^      G  glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          `   *                     	  kdisabled               K      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy                                             
  (unipro mp                     	  kdisabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                         @            _          0  [                                               job mmu gpu         	   `      (  `   *   
   *      *      *      *           	'core0 core1 core2 core3 core4         	  kdisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg                                             _      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                            	:   a                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                 	:   a                  	R              	f   b        `   *           	s   c                       <  y   a         a         a         a         a              	z         display@14002000              mediatek,mt8195-mdp3-fg                                	:   a                                display@14003000              mediatek,mt8195-mdp3-stitch               0                	:   a      0                        display@14004000              mediatek,mt8195-mdp3-hdr                  @                	:   a      @                  "      display@14005000              mediatek,mt8195-mdp3-aal                  P                [      F               	:   a      P                  
        `   *         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                 `                	:   a      `            	R    %                    display@14007000              mediatek,mt8195-mdp3-tdshp                p                	:   a      p                  #      display@14008000              mediatek,mt8195-mdp3-color                                [      I               	:   a                        $        `   *         display@14009000              mediatek,mt8195-mdp3-ovl                                  [      J               	:   a                        %        `   *           	s   c         display@1400a000              mediatek,mt8195-mdp3-padding                                  	:   a                                `   *         display@1400b000              mediatek,mt8195-mdp3-tcc                                  	:   a                              dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot                               	:   a                  	R    +                      	s   c           `   *           	z         mutex@1400f000            mediatek,mt8195-vpp-mutex                                 [      P               	:   a                                `   *         smi@14010000              mediatek,mt8195-smi-sub-common                                                          (apb smi gals0           	   d        `   *              e      smi@14011000              mediatek,mt8195-smi-sub-common                                                         (apb smi gals0           	   d        `   *                    smi@14012000              mediatek,mt8195-smi-common-vpp                                                                 (apb smi gals0 gals1         `   *              d      larb@14013000             mediatek,mt8195-smi-larb                 0                	           	   e                            (apb smi         `   *              h      iommu@14018000            mediatek,mt8195-iommu-vpp                              8  	   f   g   h   i   j   k   l   m   n   o   p   q   r   s        [      R                             (bclk            G           `   *              c      clock-controller@14e00000             mediatek,mt8195-wpesys                                                    clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0                                        clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1              0                         larb@14e04000             mediatek,mt8195-smi-larb                 @                	           	   t                            (apb smi         `   *                    larb@14e05000             mediatek,mt8195-smi-larb                 P                	           	   d                                  (apb smi gals            `   *              j      syscon@14f00000           mediatek,mt8195-vppsys1 syscon                                           	:   a   	                        mutex@14f01000            mediatek,mt8195-vpp-mutex                                [      {               	:   a   	                    '        `   *         larb@14f02000             mediatek,mt8195-smi-larb                                  	           	   t                                  (apb smi gals            `   *                    larb@14f03000             mediatek,mt8195-smi-larb                 0                	           	   e                                  (apb smi gals            `   *              i      display@14f06000              mediatek,mt8195-mdp3-split               `                	:   a   	  `                        +      ,        `   *         display@14f07000              mediatek,mt8195-mdp3-tcc                 p                	:   a   	  p                        dma-controller@14f08000           mediatek,mt8195-mdp3-rdma                                	:   a   	              	R                          	s   u           `   *           	z         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma                                	:   a   	              	R                  
        	s   u           `   *           	z         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma                                	:   a   	              	R                          	s   c           `   *           	z         display@14f0b000              mediatek,mt8195-mdp3-fg                              	:   a   	                    	      display@14f0c000              mediatek,mt8195-mdp3-fg                              	:   a   	                          display@14f0d000              mediatek,mt8195-mdp3-fg                              	:   a   	                          display@14f0e000              mediatek,mt8195-mdp3-hdr                                 	:   a   	                          display@14f0f000              mediatek,mt8195-mdp3-hdr                                 	:   a   	                          display@14f10000              mediatek,mt8195-mdp3-hdr                                  	:   a   
                            display@14f11000              mediatek,mt8195-mdp3-aal                                 [      i               	:   a   
                            `   *         display@14f12000              mediatek,mt8195-mdp3-aal                                  [      j               	:   a   
                             `   *         display@14f13000              mediatek,mt8195-mdp3-aal                 0                [      k               	:   a   
  0                  !        `   *         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                @                	:   a   
  @            	R                        display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                P                	:   a   
  P            	R                  $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                	:   a   
  `            	R                  %      display@14f17000              mediatek,mt8195-mdp3-tdshp               p                	:   a   
  p                        display@14f18000              mediatek,mt8195-mdp3-tdshp                               	:   a   
                    (      display@14f19000              mediatek,mt8195-mdp3-tdshp                               	:   a   
                    )      display@14f1a000              mediatek,mt8195-mdp3-merge                               	:   a   
                            `   *         display@14f1b000              mediatek,mt8195-mdp3-merge                               	:   a   
                            `   *         display@14f1c000              mediatek,mt8195-mdp3-color                               [      t               	:   a   
                            `   *         display@14f1d000              mediatek,mt8195-mdp3-color                               	:   a   
              [      u                             `   *         display@14f1e000              mediatek,mt8195-mdp3-color                               [      v               	:   a   
                            `   *         display@14f1f000              mediatek,mt8195-mdp3-ovl                                 [      w               	:   a   
                             `   *           	s   u         display@14f20000              mediatek,mt8195-mdp3-padding                                  	:   a                                `   *         display@14f21000              mediatek,mt8195-mdp3-padding                                 	:   a                               `   *         display@14f22000              mediatek,mt8195-mdp3-padding                                  	:   a                                `   *         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              0                	:   a     0            	R                          	s   u           `   *           	z         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              @                	:   a     @            	R                          	s   u           `   *           	z         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              P                	:   a     P            	R                          	s   c           `   *           	z         clock-controller@15000000             mediatek,mt8195-imgsys                                               $      larb@15001000             mediatek,mt8195-smi-larb                                  	   	        	   v           $       $       $   
        (apb smi gals            `   *                    smi@15002000              mediatek,mt8195-smi-sub-common                                    $      $                 (apb smi gals0           	   d        `   *              y      smi@15003000              mediatek,mt8195-smi-sub-common                0                   $       $       $   
        (apb smi gals0           	   t        `   *              v      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                                             w      larb@15120000             mediatek,mt8195-smi-larb                                  	   
        	   v           $      w            (apb smi         `   *                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                                         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe              "                               x      larb@15230000             mediatek,mt8195-smi-larb                 #                 	           	   v           $      x            (apb smi         `   *                    clock-controller@15330000             mediatek,mt8195-ipesys               3                               %      larb@15340000             mediatek,mt8195-smi-larb                 4                 	           	   y           %      %           (apb smi         `   *              k      clock-controller@16000000             mediatek,mt8195-camsys                                               &      larb@16001000             mediatek,mt8195-smi-larb                                  	           	   z           &       &       &           (apb smi gals            `   *                    larb@16002000             mediatek,mt8195-smi-larb                                   	           	   {           &      &           (apb smi         `   *              l      smi@16004000              mediatek,mt8195-smi-sub-common                @                   &       &       &           (apb smi gals0           	   t        `   *              z      smi@16005000              mediatek,mt8195-smi-sub-common                P                   &      &                 (apb smi gals0           	   d        `   *              {      larb@16012000             mediatek,mt8195-smi-larb                                  	           	   {           |       |            (apb smi         `   *               m      larb@16013000             mediatek,mt8195-smi-larb                 0                	           	   z           }       }            (apb smi         `   *                     larb@16014000             mediatek,mt8195-smi-larb                 @                	           	   {           ~       ~            (apb smi         `   *   !           s      larb@16015000             mediatek,mt8195-smi-larb                 P                	           	   z                              (apb smi         `   *   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa                                            |      clock-controller@1606f000             mediatek,mt8195-camsys_yuva                                            }      clock-controller@1608f000             mediatek,mt8195-camsys_rawb                                            ~      clock-controller@160af000             mediatek,mt8195-camsys_yuvb              
                                    clock-controller@16140000             mediatek,mt8195-camsys_mraw                                                   larb@16141000             mediatek,mt8195-smi-larb                                 	           	   z           &              &           (apb smi gals            `   *   "                 larb@16142000             mediatek,mt8195-smi-larb                                  	           	   {                              (apb smi         `   *   "           r      clock-controller@17200000             mediatek,mt8195-ccusys                                                     larb@17201000             mediatek,mt8195-smi-larb                                  	           	   {                              (apb smi         `   *              n      video-codec@18000000              mediatek,mt8195-vcodec-dec          	f   b        	s   u                       +                                @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                 	s   c     c                 A                          (sel vdec lat top            ^      A        n              `   *         video-codec@10000             mediatek,mtk-vcodec-lat                                [                   0  	s   u      u     u     u     u     u                 A                          (sel vdec lat top            ^      A        n              `   *         video-codec@25000             mediatek,mtk-vcodec-core                  P                [                   P  	s   u     u     u     u     u     u     u     u     u     u                 A                          (sel vdec lat top            ^      A        n              `   *            larb@1800d000             mediatek,mt8195-smi-larb                                  	           	   t                              (apb smi         `   *                    larb@1800e000             mediatek,mt8195-smi-larb                                  	           	                                (apb smi         `   *              q      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc                                                   larb@1802e000             mediatek,mt8195-smi-larb                                 	           	   t                              (apb smi         `   *                    clock-controller@1802f000             mediatek,mt8195-vdecsys                                                  larb@1803e000             mediatek,mt8195-smi-larb                                 	           	                                 (apb smi         `   *              p      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1                                                     clock-controller@190f3000             mediatek,mt8195-apusys_pll               0                         clock-controller@1a000000             mediatek,mt8195-vencsys                                              !      larb@1a010000             mediatek,mt8195-smi-larb                                  	           	   t           !      !           (apb smi         `   *                    video-codec@1a020000              mediatek,mt8195-vcodec-enc                              H  	s   u  `   u  a   u  b   u  c   u  d   u  v   u  w   u  x   u  y        [      U               	f   b           !         	  (venc_sel            ^      @        n              `   *                        +         jpgdec-master             mediatek,mt8195-jpgdec          `   *         0  	s   u  m   u  n   u  r   u  s   u  t   u  u                     +               jpgdec@1a040000           mediatek,mt8195-jpgdec-hw                               0  	s   u  m   u  n   u  r   u  s   u  t   u  u        [      W                  !           (jpgdec          `   *         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw                               0  	s   u  m   u  n   u  r   u  s   u  t   u  u        [      X                  !           (jpgdec          `   *         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw                               0  	s   c     c     c     c     c     c          [      \                  "           (jpgdec          `   *            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                                "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                 y                             	:                             jpgenc-master             mediatek,mt8195-jpgenc          `   *            	s   c     c     c     c                       +               jpgenc@1a030000           mediatek,mt8195-jpgenc-hw                                  	s   u  g   u  h   u  i   u  l        [      V                  !           (jpgenc          `   *         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw                                  	s   c     c     c     c          [      [                  "           (jpgenc          `   *            larb@1b010000             mediatek,mt8195-smi-larb                                  	           	   d           "      "                  (apb smi gals            `   *              o      ovl@1c000000              mediatek,mt8195-disp-ovl                                   [      |               `   *                          	s   u           	:                   rdma@1c002000             mediatek,mt8195-disp-rdma                                  [      ~               `   *                         	s   u            	:                   color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                 0                [                     `   *                         	:        0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                 @                [                     `   *                         	:        @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                 P                [                     `   *                         	:        P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                 `                [                     `   *                         	:        `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither               p                [                     `   *                 	        	:        p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                               [                     `   *                       *           (engine digital hs           v           dphy          	  kdisabled          dsc@1c009000              mediatek,mt8195-disp-dsc                                  [                     `   *                         	:                  dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                               [                     `   *                       +           (engine digital hs           v           dphy          	  kdisabled          merge@1c014000            mediatek,mt8195-disp-merge               @                [                     `   *                         	:        @          dp-intf@1c015000              mediatek,mt8195-dp-intf              P                [                           ,                    (pixel engine pll          	  kdisabled          mutex@1c016000            mediatek,mt8195-disp-mutex               `                [                     `   *                         	:        `            	R  U      larb@1c018000             mediatek,mt8195-smi-larb                                 	            	   t              (      (              (apb smi gals            `   *                    larb@1c019000             mediatek,mt8195-smi-larb                                 	           	   d              (                     (apb smi gals            `   *              f      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                                y                 	:                                o              #      smi@1c01b000              mediatek,mt8195-smi-common-vdo                                      %      &      )      $        (apb smi gals0 gals1         `   *              t      iommu@1c01f000            mediatek,mt8195-iommu-vdo                              8  	                                                  [                     G                 '        (bclk            `   *              u      mutex@1c101000            mediatek,mt8195-disp-mutex                               [                     `   *              #           	:                    	R        larb@1c102000             mediatek,mt8195-smi-larb                                  	           	   t           #       #       #           (apb smi gals            `   *                    larb@1c103000             mediatek,mt8195-smi-larb                 0                	           	   d           #      #                  (apb smi gals            `   *              g      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma                @                [                        #           `   *           	s   u   @        	:        @            	z         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma                P                [                        #           `   *           	s   c   `        	:        P            	z         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma                `                [                        #           `   *           	s   u   A        	:        `            	z         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma                p                [                        #           `   *           	s   c   a        	:        p            	z         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma                                [                        #           `   *           	s   u   B        	:                    	z         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma                                [                        #           `   *           	s   c   b        	:                    	z         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                                [                        #           `   *           	s   u   C        	:                    	z         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma                                [                        #           `   *           	s   c   c        	:                    	z         vpp-merge@1c10c000            mediatek,mt8195-disp-merge                               [                        #   	   #           (merge merge_async           `   *           	:                     	           #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge                               [                        #   
   #           (merge merge_async           `   *           	:                     	           #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge                               [                        #      #           (merge merge_async           `   *           	:                     	           #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge                               [                        #      #           (merge merge_async           `   *           	:                     	           #         vpp-merge@1c110000            mediatek,mt8195-disp-merge                                [                        #      #           (merge merge_async           `   *           	:                      	           #         dp-intf@1c113000              mediatek,mt8195-dp-intf              0                [                     `   *              #   /   #                 (pixel engine pll          	  kdisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p       @            P            p                                                              4  |mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  	:        @            P            p                                                          h     #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *              (mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          `   *           	s   c   d   c   e        [                   (     #   3   #   4   #   5   #   6   #   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx               P                            dp_calibration_data         `   *           [                     	        	  kdisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx                `                            dp_calibration_data         `   *           [                     	        	  kdisabled             thermal-zones      cpu0-thermal            	          	           
         trips      trip-alert          
" L        
.           passive                  trip-crit           
"         
.        	   critical             cooling-maps       map0            
9         0  
>   	   
                  cpu1-thermal            	          	           
         trips      trip-alert          
" L        
.           passive                  trip-crit           
"         
.        	   critical             cooling-maps       map0            
9         0  
>   	   
                  cpu2-thermal            	          	           
         trips      trip-alert          
" L        
.           passive                  trip-crit           
"         
.        	   critical             cooling-maps       map0            
9         0  
>   	   
                  cpu3-thermal            	          	           
         trips      trip-alert          
" L        
.           passive                  trip-crit           
"         
.        	   critical             cooling-maps       map0            
9         0  
>   	   
                  cpu4-thermal            	          	           
          trips      trip-alert          
" L        
.           passive                  trip-crit           
"         
.        	   critical             cooling-maps       map0            
9         0  
>                        cpu5-thermal            	          	           
         trips      trip-alert          
" L        
.           passive                  trip-crit           
"         
.        	   critical             cooling-maps       map0            
9         0  
>                        cpu6-thermal            	          	           
         trips      trip-alert          
" L        
.           passive                  trip-crit           
"         
.        	   critical             cooling-maps       map0            
9         0  
>                        cpu7-thermal            	          	           
         trips      trip-alert          
" L        
.           passive                  trip-crit           
"         
.        	   critical             cooling-maps       map0            
9         0  
>                        vpu0-thermal            	          	           
         trips      trip-alert          
" L        
.           passive       trip-crit           
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.        	   critical                vpu1-thermal            	          	           
      	   trips      trip-alert          
" L        
.           passive       trip-crit           
"         
.        	   critical                gpu-thermal         	          	           
      
   trips      trip-alert          
" L        
.           passive       trip-crit           
"         
.        	   critical                gpu1-thermal            	          	           
         trips      trip-alert          
" L        
.           passive       trip-crit           
"         
.        	   critical                vdec-thermal            	          	           
         trips      trip-alert          
" L        
.           passive       trip-crit           
"         
.        	   critical                img-thermal         	          	           
         trips      trip-alert          
" L        
.           passive       trip-crit           
"         
.        	   critical                infra-thermal           	          	           
         trips      trip-alert          
" L        
.           passive       trip-crit           
"         
.        	   critical                cam0-thermal            	          	           
         trips      trip-alert          
" L        
.           passive       trip-crit           
"         
.        	   critical                cam1-thermal            	          	           
         trips      trip-alert          
" L        
.           passive       trip-crit           
"         
.        	   critical                   chosen          
Mserial0:921600n8          firmware       optee             linaro,optee-tz         smc          gpio-keys         
    gpio-keys           default               key-0           Z      j         
  
Yvolume_up           
_   s         {        
j            memory@40000000          memory               @                reserved-memory                      +               optee@43200000           
|             C                memory@50000000           shared-dma-pool              P                  
|      memory@53000000           shared-dma-pool              S       @        memory@54600000          
|             T`                memory@60000000           shared-dma-pool              `                  
|      memory@62000000           shared-dma-pool              b       @              	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us pinctrl-1 snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup vusb33-supply vbus-supply bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval no-map 