 TR   8 HX   (             H                              4    mediatek,mt8395-evk mediatek,mt8395 mediatek,mt8195                                  +         "   7MediaTek Genio 1200 EVK-P1V2-EMMC      aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/serial@11001100             /soc/ethernet@11021000        cpus                         +       cpu@0            cpu           arm,cortex-a55                      psci                           -ec3@        =  4        P              `           m   @                                 @                                            	      cpu@100          cpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `           m   @                                 @                                            
      cpu@200          cpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `           m   @                                 @                                                  cpu@300          cpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `           m   @                                 @                                                  cpu@400          cpu           arm,cortex-a78                     psci                          -f        =           P              `           m   @                                 @                                                  cpu@500          cpu           arm,cortex-a78                     psci                          -f        =           P              `           m   @                                 @                                                  cpu@600          cpu           arm,cortex-a78                     psci                          -f        =           P              `           m   @                                 @                                                  cpu@700          cpu           arm,cortex-a78                     psci                          -f        =           P              `           m   @                                 @                                                  cpu-map    cluster0       core0              	      core1              
      core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                                2        *   _        :  D                 cpu-retention-b           arm,idle-state                                -        *           :                   cpu-off-l             arm,idle-state                               7        *           :  H                 cpu-off-b             arm,idle-state                               2        *           :                      l2-cache0             cache           K           b           o   @                               W                 l2-cache1             cache           K           b           o   @                               W                 l3-cache              cache           K           b            o   @                    W                    dsu-pmu           arm,dsu-pmu         e                       p   	   
                          ufail          dmic-codec            dmic-codec          |                    mt8195-sound                     	  udisabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             )      oscillator-26m            fixed-clock                     -        clk26m                   oscillator-32k            fixed-clock                     -           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw                           0                                   opp-table-gpu             operating-points-v2                     o   opp-390000000               >         	h      opp-410000000               p         	      opp-431000000                        	      opp-473000000               1h@         	<      opp-515000000               F         	<      opp-556000000               !#          	Ҧ      opp-598000000               #         	      opp-640000000               &%          	      opp-670000000               'c         
      opp-700000000               )'          
L      opp-730000000               +         
}      opp-760000000               -L          
`      opp-790000000               /q         
4      opp-820000000               05                opp-850000000               2         @      opp-880000000               4s          q         pmu-a55           arm,cortex-a55-pmu                      e                  pmu-a78           arm,cortex-a78-pmu                      e                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  e                                             
             soc                      +             simple-bus           !        (                          interrupt-controller@c000000              arm,gic-v3          3           D                        [                                             e      	                     ppi-partitions     interrupt-partition-0           p   	   
                       interrupt-partition-1           p                                   syscon@10000000            mediatek,mt8195-topckgen syscon                                                   syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                                          y                    syscon@10003000           mediatek,mt8195-pericfg syscon               0                              B      pinctrl@10005000              mediatek,mt8195-pinctrl              P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                                                      [        e                      3                 audio-default-pins     pins-cmd-dat          4    =  >  A  B  C  D  E  F  G  H  I  J  K         disp-pwm1-default-pins     pins1             h         edp-panel-12v-en-pins                 pins1             `                   edp-panel-3v3-en-pins                 pins1                                eth-default-pins               >   pins-cc           U  V  W  X                 pins-mdio             Y  Z               pins-power            [   \                pins-rxd              Q  R  S  T      pins-txd              M  N  O  P                    eth-sleep-pins             ?   pins-cc           U   V   W   X       pins-mdio             Y   Z                         pins-rxd              Q   R   S   T       pins-txd              M   N   O   P          gpio-keys-pins     pins              j                            i2c0-pins              \   pins                	                              i2c1-pins              ]   pins              
                                i2c2-pins              `   pins                                               i2c6-pins              X   pins                                  mmc0-default-pins              D   pins-clk              z                   '   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-rst              x                      e         mmc0-uhs-pins              E   pins-clk              z                   '   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-ds                              '   f      pins-rst              x                      e         mmc1-default-pins              H   pins-clk              o                   '   f      pins-cmd-dat              n  p  q  r  s                               e         mmc1-uhs-pins              I   pins-clk              o                   '   f      pins-cmd-dat              n  p  q  r  s                               e         mt6360-pins            Y   pins                                             pcie0-default-pins             S   pins                                    pcie0-idle-pins            T   pins                                 6         pcie1-default-pins             V   pins                                    pwm0-default-pins              5   pins-cmd-dat              a         spi1-pins              6   pins                                      spi-pins               9   pins                                      touch-pins             _   pins-irq                                       pins-reset                               uart0-pins             0   pins              b  c         uart1-pins             1   pins              d  e  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +            A              ,   power-domain@8                                  +            A           U      power-domain@9             	                            cmfg alt         o                        +            A      power-domain@10            
        A          power-domain@11                    A          power-domain@12                    A          power-domain@13                    A          power-domain@14                    A                power-domain@15                                            	      @      A      K                                                                                                                                cvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           o                        +            A      power-domain@16                  8              $      %      &      '      (      )      D  cvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         o                        +            A      power-domain@17                                              cvppsys1 vppsys1-0 vppsys1-1         o           A          power-domain@22                                                   $  cwepsys-0 wepsys-1 wepsys-2 wepsys-3         o           A          power-domain@23                                   cvdec0-0         o                        +            A       power-domain@24                                    cvdec1-0         o           A          power-domain@25                       !            cvdec2-0         o           A             power-domain@26                       "            cvenc0-larb          o                        +            A       power-domain@27                       #            cvenc1-larb          o           A             power-domain@18                              $       $      $         &  cvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           o                        +            A      power-domain@19                    o           A          power-domain@20                    o           A          power-domain@21                          Q        chdmi_tx         A             power-domain@28                       %       %   
        cimg-0 img-1         o                        +            A      power-domain@29                    A          power-domain@30                             %      &           cipe ipe-0 ipe-1         o           A             power-domain@31                  (     '       '      '      '      '           ccam-0 cam-1 cam-2 cam-3 cam-4           o                        +            A      power-domain@32                     A          power-domain@33            !        A          power-domain@34            "        A                   power-domain@0                      o           A          power-domain@1                     o           A          power-domain@2                     A          power-domain@3                     A          power-domain@4                           5      7        ccsi_rx_top csi_rx_top1          A          power-domain@5                        (           cether           A          power-domain@6                           X      n        cadsp adsp1                       +            o           A      power-domain@7                            g      "      n      2        caudio audio1 audio2 audio3          o           A                   watchdog@10007000             mediatek,mt8195-wdt                       p                y              /      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                                                    timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                e      	                  )      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                pwrap           e                                         	  cspi wrap                  $                 pmic              mediatek,mt6359          [        3                       adc           mediatek,mt6359-auxadc                   mt6359codec                                        regulators            mediatek,mt6359-regulator      buck_vs1            "vs1         1 5         I !        a             }      buck_vgpu11         "vgpu11          1         I 7                  a                              }      buck_vmodem         "vmodem          1         I           *        a         buck_vpu            "vpu         1         I 7                  a                              }      buck_vcore          "vcore           1         I                    a                              }      buck_vs2            "vs2         1 5         I j         a             }      buck_vpa            "vpa         1          I 7        a  ,      buck_vproc2         "vproc2          1         I 7          L        a                           buck_vproc1         "vproc1          1         I 7          L        a                           buck_vcore_sshub            "vcore_sshub         1         I 7      buck_vgpu11_sshub           "vgpu11_sshub            1         I 7      ldo_vaud18          "vaud18          1 w@        I w@        a            }      ldo_vsim1           "vsim1           1         I /M`      ldo_vibr            "vibr            1 O        I 2Z      ldo_vrf12           "vrf12           1         I           }      ldo_vusb            "vusb            1 -        I -        a           }           C      ldo_vsram_proc2         "vsram_proc2         1          I           L        a            }      ldo_vio18           "vio18           1         I         a           }      ldo_vcamio          "vcamio          1         I          }      ldo_vcn18           "vcn18           1 w@        I w@        a         ldo_vfe28           "vfe28           1 *        I *        a   x      ldo_vcn13           "vcn13           1         I        ldo_vcn33_1_bt          "vcn33_1_bt          1 *        I 5g      ldo_vcn33_1_wifi            "vcn33_1_wifi            1 *        I 5g      ldo_vaux18          "vaux18          1 w@        I w@        a            }      ldo_vsram_others            "vsram_others            1          I                   a         ldo_vefuse          "vefuse          1         I       ldo_vxo22           "vxo22           1 w@        I !         }      ldo_vrfck           "vrfck           1 `        I       ldo_vrfck_1         "vrfck           1         I j       ldo_vbif28          "vbif28          1 *        I *        a         ldo_vio28           "vio28           1 *        I 2Z         }      ldo_vemc            "vemc            1 ,@         I 2Z      ldo_vemc_1          "vemc            1 &%        I 2Z           F      ldo_vcn33_2_bt          "vcn33_2_bt          1 2Z        I 2Z           8      ldo_vcn33_2_wifi            "vcn33_2_wifi            1 *        I 5g      ldo_va12            "va12            1 O        I           }      ldo_va09            "va09            1 5         I O      ldo_vrf18           "vrf18           1         I P      ldo_vsram_md          	  "vsram_md            1          I           *        a         ldo_vufs            "vufs            1         I            G      ldo_vm18            "vm18            1         I          }      ldo_vbbck           "vbbck           1         I O         }      ldo_vsram_proc1         "vsram_proc1         1          I           L        a            }      ldo_vsim2           "vsim2           1         I /M`      ldo_vsram_others_sshub          "vsram_others_sshub          1          I          rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi                 p                            pmif spmimst                               E      (  cpmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $                                   +       pmic@6            mediatek,mt6315-regulator                     regulators     vbuck1          "Vbcpu           1         I 7        a                              }            pmic@7            mediatek,mt6315-regulator                     regulators     vbuck1          "Vgpu            1         I 7        a                                               infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  e                                                                                       P      mailbox@10320000              mediatek,mt8195-gce             2        @         e                                                        mailbox@10330000              mediatek,mt8195-gce             3        @         e                                                  p      scp@10500000              mediatek,mt8195-scp       0      P             r             p                 sram cfg l1tcm          e                     uokay               *           q      clock-controller@10720000             mediatek,mt8195-scp_adsp                r                               +      dsp@10803000              mediatek,mt8195-dsp              0                           	  cfg sram          ,        X         n         +          #      K  cadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             ,           rx tx              -   .      	  udisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox                           `                e                        -      mailbox@10817000              mediatek,mt8195-adsp-mbox                           p                e                        .      mt8195-afe-pcm@10890000           mediatek,mt8195-audio                                              ,           e      6                  /         	  audiosys                                                               g      "      #      n      e      a      b      c      d      2   +            cclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  udisabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                     	  cbaud bus            uokay            *   0        4default       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                     	  cbaud bus            uokay            *   1        4default       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                     	  cbaud bus          	  udisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                    	  cbaud bus          	  udisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                    	  cbaud bus          	  udisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                    	  cbaud bus          	  udisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                               cmain                     	  udisabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                              (      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 e                                                cparent-clk sel-clk spi-clk        	  udisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap                              e                                                   B   2   3      $  Nlvts-calib-data-1 lvts-calib-data-2         _                    svs@1100bc00              mediatek,mt8195-svs                              e                                    cmain            B   4   2      (  Nsvs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                e                         ,           u                 *      0        cmain mm         uokay            4default         *   5                 pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                e                     u                 +      N        cmain mm       	  udisabled                     spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 e                                        3        cparent-clk sel-clk spi-clk          uokay            *   6        4default                           @      can@0             microchip,mcp2518fd                        7        1-                             8           8         spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 e                                        4        cparent-clk sel-clk spi-clk          uokay            *   9        4default                   spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                e                                        5        cparent-clk sel-clk spi-clk        	  udisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                e                                        <        cparent-clk sel-clk spi-clk        	  udisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                e                                        =        cparent-clk sel-clk spi-clk        	  udisabled          spi@1101d000              mediatek,mt8195-spi-slave                               e                            R        cspi                                   	  udisabled          spi@1101e000              mediatek,mt8195-spi-slave                               e                            S        cspi                                   	  udisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         e                     macirq        .  caxi apb mac_main ptp_ref rmii_internal mac_cg         0     (       (         R      S      T   (                 R      S      T                                     ,                         :           ;           <                    +           6            uokay            Crgmii-rxid          L   =        W      ]            g      '  '        |                   4default sleep           *   >           ?   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916                          =         stmmac-axi-config                                                                     :      rx-queues-config                                   ;   queue0                             queue1                             queue2                             queue3                                tx-queues-config            (            >           <   queue0          P                    \          queue1          P                    \         queue2          P                    \         queue3          P                    \               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -     >              	  mac ippc            !                     ?                      +           e                            /            B        csys_ck ref_ck mcu_ck            j   @      A            o        }   B      g        uokay               C   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         e                            ,      -                          $        /                     B      $  csys_ck ref_ck mcu_ck dma_ck xhci_ck         uokay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #                              e                                                csource hclk source_cg           uokay            4default state_uhs           *   D           E                                                                                   L        	
   F        	   G         	#      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $                              e                                        $        csource hclk source_cg                                       uokay            4default state_uhs           *   H           I                             	1         	B         	O         	]                 	
   J        	   K         	#      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %                              e                                         I        csource hclk source_cg                                      	  udisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '                e                                                  B   2   3      $  Nlvts-calib-data-1 lvts-calib-data-2         _                    usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  mac ippc            e                     j   L      M                 .      /                          $     (                     (         $  csys_ck ref_ck mcu_ck dma_ck xhci_ck         }   B      h         o        uokay               C      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -    *>              	  mac ippc            !            *        ?                      +           e                           0                         (            (           csys_ck ref_ck mcu_ck            j   N            o        }   B      i        uokay               C   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         e                           1                         (           csys_ck          uokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -    +>              	  mac ippc            !            +        ?                      +           e                           2                         (            (   	        csys_ck ref_ck mcu_ck            j   O            o        }   B      j        uokay               C   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         e                           3                         (   	        csys_ck          uokay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +               /        @       	  pcie-mac            e                     	d             8  !                                                            	n       P              	x          0        V      #      &      +      K   (         /  cpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                G                      j   Q      	  	pcie-phy               ,            3           	                     `  	                  R                      R                     R                     R           uokay            4default idle            *   S           T   interrupt-controller             [                     3              R         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +               /       @       	  pcie-mac            e                     	d             8  !       $       $                  $       $                 	n       P              	x          (        W         X         Q   (         /  cpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                H                      j   M         	  	pcie-phy               ,           3           	                     `  	                  U                      U                     U                     U         	  udisabled            4default         *   V   interrupt-controller             [                     3              U         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2                e      9                     o   (      (           cspi sf axi                       +          	  udisabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                                              +      usb3-tx-imp@184,1                        	                  f      usb3-rx-imp@184,2                        	                 e      usb3-intr@185                        	                 d      usb3-tx-imp@186,1                        	                  c      usb3-rx-imp@186,2                        	                 b      usb3-intr@187                        	                 a      usb2-intr-p0@188,1                       	             usb2-intr-p1@188,2                       	            usb2-intr-p2@189,1                       	            usb2-intr-p3@189,2                       	            pciephy-rx-ln1@190,1                         	                  m      pciephy-tx-ln1-nmos@190,2                        	                 l      pciephy-tx-ln1-pmos@191,1                        	                  k      pciephy-rx-ln0@191,2                         	                 j      pciephy-tx-ln0-nmos@192,1                        	                  i      pciephy-tx-ln0-pmos@192,2                        	                 h      pciephy-glb-intr@193                         	                  g      dp-data@1ac                               lvts1-calib@1bc                         2      lvts2-calib@1d0              8           3      svs-calib@580                d           4      socinfo-data1@7a0                         t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !                     uokay       usb-phy@0                                        cref         	              N         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !                     uokay       usb-phy@0                                        cref         	              O         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                         mipi_tx0_pll                        	          	  udisabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                         mipi_tx1_pll                        	          	  udisabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               e                                    W          ;      	  cmain dma                         +          	  udisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                          "                e                                    W         ;      	  cmain dma                         +            uokay            -         *   X        4default    pmic@34           mediatek,mt6360            4                    e              IRQB             [        3           *   Y   charger           mediatek,mt6360-chg         	 @   usb-otg-vbus-regulator          "usb-otg-vbus            1 C(        I X         regulator             mediatek,mt6360-regulator           	   Z   buck1         	  "emi_vdd2            1         I                             }      buck2         	  "emi_vddq            1         I                             }           Z      ldo1          	  "tp1_p3v0            1 2Z        I 2Z                        }           ^      ldo2            "panel1_p1v8         1 w@        I w@                     ldo3            "vmc_pmu         1 O        I 6                          K      ldo5          	  "vmch_pmu            1 )2        I 6                          J      ldo6            "mt6360_ldo1         1          I                        ldo7            "emi_vmddr_en            1          I                           }               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               e                                    W         ;      	  cmain dma                         +          	  udisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              0                              W      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                e                                    [          ;      	  cmain dma                         +            uokay            -         *   \        4default       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                          "                e                                    [         ;      	  cmain dma                         +            uokay            -         *   ]        4default    touchscreen@5d            goodix,gt9271              ]                         	                  	                  
   ^        4default         *   _         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               e                                    [         ;      	  cmain dma                         +            uokay            -         *   `        4default       i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              0            "               e                                    [         ;      	  cmain dma                         +          	  udisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              @            "                e                                    [         ;      	  cmain dma                         +          	  udisabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              P                              [      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !                        ,           uokay       usb-phy@0                                           cref da_ref          	              L      usb-phy@700                                           cref da_ref          B   a   b   c        Nintr rx_imp tx_imp          	            
           M         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !                     uokay       usb-phy@0                                           cref da_ref          	              @      usb-phy@700                                           cref da_ref          B   d   e   f        Nintr rx_imp tx_imp          	              A         phy@11e80000              mediatek,mt8195-pcie-phy                                 sif         B   g   h   i   j   k   l   m      G  Nglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             ,           	            uokay               Q      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy                                            
  cunipro mp           	          	  udisabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @            n          0  e                                               job mmu gpu         
#   o      (     ,   
   ,      ,      ,      ,           
7core0 core1 core2 core3 core4         	  udisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg                                            n      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                           
J   p                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                
J   p                  
b              
v   q           ,           
   r                       <     p         p         p         p         p              
         display@14002000              mediatek,mt8195-mdp3-fg                               
J   p                                display@14003000              mediatek,mt8195-mdp3-stitch              0                
J   p      0                        display@14004000              mediatek,mt8195-mdp3-hdr                 @                
J   p      @                  "      display@14005000              mediatek,mt8195-mdp3-aal                 P                e      F               
J   p      P                  
           ,         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                
J   p      `            
b    %                    display@14007000              mediatek,mt8195-mdp3-tdshp               p                
J   p      p                  #      display@14008000              mediatek,mt8195-mdp3-color                               e      I               
J   p                        $           ,         display@14009000              mediatek,mt8195-mdp3-ovl                                 e      J               
J   p                        %           ,           
   r         display@1400a000              mediatek,mt8195-mdp3-padding                                 
J   p                                   ,         display@1400b000              mediatek,mt8195-mdp3-tcc                                 
J   p                              dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot                              
J   p                  
b    +                      
   r              ,           
         mutex@1400f000            mediatek,mt8195-vpp-mutex                                e      P               
J   p                                   ,         smi@14010000              mediatek,mt8195-smi-sub-common                                                         capb smi gals0           
   s           ,              t      smi@14011000              mediatek,mt8195-smi-sub-common                                                        capb smi gals0           
   s           ,                    smi@14012000              mediatek,mt8195-smi-common-vpp                                                                capb smi gals0 gals1            ,              s      larb@14013000             mediatek,mt8195-smi-larb                0                
           
   t                            capb smi            ,              w      iommu@14018000            mediatek,mt8195-iommu-vpp                             8  
   u   v   w   x   y   z   {   |   }   ~                    e      R                             cbclk                          ,              r      clock-controller@14e00000             mediatek,mt8195-wpesys                                                   clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0                                       clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             0                         larb@14e04000             mediatek,mt8195-smi-larb                @                
           
                               capb smi            ,                    larb@14e05000             mediatek,mt8195-smi-larb                P                
           
   s                                  capb smi gals               ,              y      syscon@14f00000           mediatek,mt8195-vppsys1 syscon                                          
J   p   	                        mutex@14f01000            mediatek,mt8195-vpp-mutex                               e      {               
J   p   	                    '           ,         larb@14f02000             mediatek,mt8195-smi-larb                                 
           
                                     capb smi gals               ,                    larb@14f03000             mediatek,mt8195-smi-larb                0                
           
   t                                  capb smi gals               ,              x      display@14f06000              mediatek,mt8195-mdp3-split              `                
J   p   	  `                        +      ,           ,         display@14f07000              mediatek,mt8195-mdp3-tcc                p                
J   p   	  p                        dma-controller@14f08000           mediatek,mt8195-mdp3-rdma                               
J   p   	              
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J   p   	                    	      display@14f0c000              mediatek,mt8195-mdp3-fg                             
J   p   	                          display@14f0d000              mediatek,mt8195-mdp3-fg                             
J   p   	                          display@14f0e000              mediatek,mt8195-mdp3-hdr                                
J   p   	                          display@14f0f000              mediatek,mt8195-mdp3-hdr                                
J   p   	                          display@14f10000              mediatek,mt8195-mdp3-hdr                                 
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                            display@14f11000              mediatek,mt8195-mdp3-aal                                e      i               
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J   p                                   ,         display@14f21000              mediatek,mt8195-mdp3-padding                                
J   p                                  ,         display@14f22000              mediatek,mt8195-mdp3-padding                                 
J   p                                   ,         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             0                
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                                 capb smi            ,   !                 larb@16015000             mediatek,mt8195-smi-larb                P                
           
                                 capb smi            ,   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa                                                 clock-controller@1606f000             mediatek,mt8195-camsys_yuva                                                 clock-controller@1608f000             mediatek,mt8195-camsys_rawb                                                 clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
                                    clock-controller@16140000             mediatek,mt8195-camsys_mraw                                                  larb@16141000             mediatek,mt8195-smi-larb                                
           
              '              '           capb smi gals               ,   "                 larb@16142000             mediatek,mt8195-smi-larb                                 
           
                                 capb smi            ,   "                 clock-controller@17200000             mediatek,mt8195-ccusys                                                    larb@17201000             mediatek,mt8195-smi-larb                                 
           
                                 capb smi            ,              }      video-codec@18000000              mediatek,mt8195-vcodec-dec          
v   q        
                          +                               @                !                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                
   r     r                 A                          csel vdec lat top                  A                         ,         video-codec@10000             mediatek,mtk-vcodec-lat                               e                   0  
                                              A                          csel vdec lat top                  A                         ,         video-codec@25000             mediatek,mtk-vcodec-core                 P                e                   P  
                                                                 A                            csel vdec lat top                  A                         ,            larb@1800d000             mediatek,mt8195-smi-larb                                 
           
                                 capb smi            ,                    larb@1800e000             mediatek,mt8195-smi-larb                                 
           
                                capb smi            ,                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc                                                  larb@1802e000             mediatek,mt8195-smi-larb                                
           
                                   capb smi            ,                    clock-controller@1802f000             mediatek,mt8195-vdecsys                                                  larb@1803e000             mediatek,mt8195-smi-larb                                
           
                    !            capb smi            ,                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1                                             !      clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                         clock-controller@1a000000             mediatek,mt8195-vencsys                                             "      larb@1a010000             mediatek,mt8195-smi-larb                                 
           
              "      "           capb smi            ,                    video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H  
     `     a     b     c     d     v     w     x     y        e      U               
v   q           "         	  cvenc_sel                  @                         ,                        +         jpgdec-master             mediatek,mt8195-jpgdec             ,         0  
     m     n     r     s     t     u                     +            !   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw                              0  
     m     n     r     s     t     u        e      W                  "           cjpgdec             ,         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw                              0  
     m     n     r     s     t     u        e      X                  "           cjpgdec             ,         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw                              0  
   r     r     r     r     r     r          e      \                  #           cjpgdec             ,            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                               #      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                                             
J                             jpgenc-master             mediatek,mt8195-jpgenc             ,            
   r     r     r     r                       +            !   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw                                 
     g     h     i     l        e      V                  "           cjpgenc             ,         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw                                 
   r     r     r     r          e      [                  #           cjpgenc             ,            larb@1b010000             mediatek,mt8195-smi-larb                                 
           
   s           #      #                  capb smi gals               ,              ~      ovl@1c000000              mediatek,mt8195-disp-ovl                                  e      |                  ,                          
              
J                   rdma@1c002000             mediatek,mt8195-disp-rdma                                 e      ~                  ,                         
               
J                   color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                e                        ,                         
J        0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                e                        ,                         
J        @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                e                        ,                         
J        P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                e                        ,                         
J        `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                e                        ,                 	        
J        p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              e                        ,                       *           cengine digital hs           j           	dphy          	  udisabled          dsc@1c009000              mediatek,mt8195-disp-dsc                                 e                        ,                         
J                  dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              e                        ,                       +           cengine digital hs           j           	dphy          	  udisabled          merge@1c014000            mediatek,mt8195-disp-merge              @                e                        ,                         
J        @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                e                           ,                    cpixel engine pll          	  udisabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                e                        ,                         
J        `            
b  U      larb@1c018000             mediatek,mt8195-smi-larb                                
            
                 (      (              capb smi gals               ,                    larb@1c019000             mediatek,mt8195-smi-larb                                
           
   s              (                     capb smi gals               ,              u      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                                                
J                                y              $      smi@1c01b000              mediatek,mt8195-smi-common-vdo                                     %      &      )      $        capb smi gals0 gals1            ,                    iommu@1c01f000            mediatek,mt8195-iommu-vdo                             8  
                                                  e                                      '        cbclk               ,                    mutex@1c101000            mediatek,mt8195-disp-mutex                              e                        ,              $           
J                    
b        larb@1c102000             mediatek,mt8195-smi-larb                                 
           
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   s           $      $                  capb smi gals               ,              v      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                e                        $              ,           
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J        @            
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J        P            
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J        `            
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J        p            
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J                    
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J                    
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J                    
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J                    
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J                     
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J        @            P            p                                                          h     $   %   $       $   #   $   !   $   $   $   "   $   1   $   &   $   '   $   (   $   )   $   *              cmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             ,           
   r   d   r   e        e                   (     $   3   $   4   $   5   $   6   $   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx              P                 B           Ndp_calibration_data            ,           e                     
        	  udisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `                 B           Ndp_calibration_data            ,           e                     
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                  cpu4-thermal            
                     "          trips      trip-alert          2 L        >          passive                  trip-crit           2         >        	  critical             cooling-maps       map0            I         0  N                        cpu5-thermal            
                     "         trips      trip-alert          2 L        >          passive                  trip-crit           2         >        	  critical             cooling-maps       map0            I         0  N                        cpu6-thermal            
                     "         trips      trip-alert          2 L        >          passive                  trip-crit           2         >        	  critical             cooling-maps       map0            I         0  N                        cpu7-thermal            
                     "         trips      trip-alert          2 L        >          passive                  trip-crit           2         >        	  critical             cooling-maps       map0            I         0  N                        vpu0-thermal            
                     "         trips      trip-alert          2 L        >          passive       trip-crit           2         >        	  critical                vpu1-thermal            
                     "      	   trips      trip-alert          2 L        >          passive       trip-crit           2         >        	  critical                gpu-thermal         
                     "      
   trips      trip-alert          2 L        >          passive       trip-crit           2         >        	  critical                gpu1-thermal            
                     "         trips      trip-alert          2 L        >          passive       trip-crit           2         >        	  critical                vdec-thermal            
                     "         trips      trip-alert          2 L        >          passive       trip-crit           2         >        	  critical                img-thermal         
                     "         trips      trip-alert          2 L        >          passive       trip-crit           2         >        	  critical                infra-thermal           
                     "         trips      trip-alert          2 L        >          passive       trip-crit           2         >        	  critical                cam0-thermal            
                     "         trips      trip-alert          2 L        >          passive       trip-crit           2         >        	  critical                cam1-thermal            
                     "         trips      trip-alert          2 L        >          passive       trip-crit           2         >        	  critical                   chosen          ]serial0:921600n8          firmware       optee             linaro,optee-tz         smc          memory@40000000          memory              @                reserved-memory                      +            !   optee@43200000           i            C                memory@50000000           shared-dma-pool             P                  i           *      memory@53000000           shared-dma-pool             S       @        memory@54600000          i            T`                memory@60000000           shared-dma-pool             `                  i      memory@62000000           shared-dma-pool             b       @           backlight-lcd0            pwm-backlight           p                 u      /                                      @      backlight-lcd1            pwm-backlight           p                 u      .                                      @      can-clk           fixed-clock                     -1-         can-clk            7      regulator-0           regulator-fixed         "edp_panel_3v3           1 2Z        I 2Z                 b                  4default         *         regulator-1           regulator-fixed         "edp_backlight_12v           1          I                   b      `            4default         *         gpio-keys         
    gpio-keys      button-volume-up             o           d              j         
  volume_up              s         regulator-2           regulator-fixed       	  "wifi_3v3            1 2Z        I 2Z        b                            }         	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 ethernet0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux output-high drive-strength input-enable input-disable bias-disable bias-pull-up drive-strength-microamp bias-pull-down output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-0 pinctrl-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select cs-gpios spi-max-frequency vdd-supply xceiver-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us mediatek,tx-delay-ps mediatek,mac-wol pinctrl-1 snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup vusb33-supply bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply irq-gpios reset-gpios AVDD28-supply mediatek,force-mode operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path no-map pwms enable-gpios brightness-levels num-interpolated-steps default-brightness-level enable-active-high debounce-interval label linux,code 