 [   8 P   (             O                             6    kontron,3-5-sbc-i1200 mediatek,mt8395 mediatek,mt8195                                    +            7Kontron 3.5"-SBC-i1200     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/mmc@11230000            /soc/mmc@11240000            /soc/serial@11001200             /soc/serial@11001300            /soc/serial@11001400            /soc/serial@11001500            /soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55          '            +psci            9               Mec3@        ]  4        p                            @                                 @                                            	      cpu@100         cpu           arm,cortex-a55          '           +psci            9               Mec3@        ]  4        p                            @                                 @                                            
      cpu@200         cpu           arm,cortex-a55          '           +psci            9               Mec3@        ]  4        p                            @                                 @                                                  cpu@300         cpu           arm,cortex-a55          '           +psci            9               Mec3@        ]  4        p                            @                                 @                                                  cpu@400         cpu           arm,cortex-a78          '           +psci            9              Mf        ]           p                            @                                 @                                                  cpu@500         cpu           arm,cortex-a78          '           +psci            9              Mf        ]           p                            @                                 @                                                  cpu@600         cpu           arm,cortex-a78          '           +psci            9              Mf        ]           p                            @                                 @                                                  cpu@700         cpu           arm,cortex-a78          '           +psci            9              Mf        ]           p                            @                                 @                                                  cpu-map    cluster0       core0               	      core1               
      core2                     core3                     core4                     core5                     core6                     core7                           idle-states         psci       cpu-retention-l           arm,idle-state                     (        9   2        J   _        Z  D                 cpu-retention-b           arm,idle-state                     (        9   -        J           Z                   cpu-off-l             arm,idle-state                    (        9   7        J           Z  H                 cpu-off-b             arm,idle-state                    (        9   2        J           Z                      l2-cache0             cache           k                         @                               w                 l2-cache1             cache           k                         @                               w                 l3-cache              cache           k                          @                    w                    dsu-pmu           arm,dsu-pmu                                   	   
                          fail          dmic-codec            dmic-codec                        2      mt8195-sound                     	  disabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             (      oscillator-26m            fixed-clock                     M        clk26m                   oscillator-32k            fixed-clock                     M           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw          '                 0                                   opp-table-gpu             operating-points-v2          !           m   opp-390000000           ,    >        3 	h      opp-410000000           ,    p        3 	      opp-431000000           ,            3 	      opp-473000000           ,    1h@        3 	<      opp-515000000           ,    F        3 	<      opp-556000000           ,    !#         3 	Ҧ      opp-598000000           ,    #        3 	      opp-640000000           ,    &%         3 	      opp-670000000           ,    'c        3 
      opp-700000000           ,    )'         3 
L      opp-730000000           ,    +        3 
}      opp-760000000           ,    -L         3 
`      opp-790000000           ,    /q        3 
4      opp-820000000           ,    05         3       opp-850000000           ,    2        3 @      opp-880000000           ,    4s         3 q         pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0            2smc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus           A        H                          interrupt-controller@c000000              arm,gic-v3          S           d                        {         '                                          	                     ppi-partitions     interrupt-partition-0              	   
                       interrupt-partition-1                                              syscon@10000000            mediatek,mt8195-topckgen syscon         '                                          syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          '                                                    syscon@10003000           mediatek,mt8195-pericfg syscon          '     0                              A      pinctrl@10005000              mediatek,mt8195-pinctrl         '     P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                                                      {                              S                 eth-default-pins               =   pins-txd              M  N  O  P                 pins-rxd              Q  R  S  T      pins-cc           U  V  W  X                 pins-mdio             Y  Z               pins-power            [   \                pins-reset            ]                pins-interrupt            ^                   eth-sleep-pins             >   pins-txd              M   N   O   P       pins-cc           U   X   W   V       pins-rxd              Q   R   S   T       pins-mdio             Y   Z                            gpio-keys-pins                pins              j                   i2c0-pins              Z   pins                	        "           /           i2c1-pins              [   pins              
          "           /           i2c2-default-pins              \   pins-bus                        "           /           i2c3-pins              ]   pins                        "           /           i2c4-pins              ^   pins                        "           /           i2c6-pins              W   pins                         "        /           mmc0-default-pins              C   pins-clk              z                   G   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                            "   e      pins-rst              x                   "   e         mmc0-uhs-pins              D   pins-clk              z                   G   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                            "   e      pins-ds                              G   f      pins-rst              x                   "   e         mmc1-default-pins              G   pins-clk              o                   G   f      pins-cmd-dat              n  p  q  r  s                            "   e         mmc1-detect-pins               H   pins-insert                     "         nor-default-pins               U   pins-ck-io                                    G      pins-cs                               "         pcie0-default-pins             Q   pins-bus                           "         pcie1-default-pins             T   pins-bus                           "   e         led-pins                  pins-power-en             k                   spi0-default-pins              4   pins-cs-mosi-clk                                 pins-miso                      G         spi1-default-pins              8   pins-cs-mosi-clk                                 pins-miso                      G         uart0-pins             /   pins-rx           c                  "      pins-tx           b         uart1-pins             0   pins-rx           g                  "      pins-tx           f      pins-rts              d      pins-cts              e                  uart2-pins             1   pins-rx           D                  "      pins-tx           C      pins-rts              B      pins-cts              A                  uart3-pins             2   pins-rx                            "   e      pins-tx                    uart4-pins             3   pins-rx                             "      pins-tx                       syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            '     `           power-controller          !    mediatek,mt8195-power-controller                         +            V              +   power-domain@8          '                        +            V      power-domain@9          '   	                            jmfg alt         v                        +            V      power-domain@10         '   
        V          power-domain@11         '           V          power-domain@12         '           V          power-domain@13         '           V          power-domain@14         '           V                power-domain@15         '                                   	      @      A      K                                                                                                                                jvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           v                        +            V      power-domain@16         '         8              $      %      &      '      (      )      D  jvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         v                        +            V      power-domain@17         '                                     jvppsys1 vppsys1-0 vppsys1-1         v           V          power-domain@22         '                                          $  jwepsys-0 wepsys-1 wepsys-2 wepsys-3         v           V          power-domain@23         '                          jvdec0-0         v                        +            V       power-domain@24         '                          jvdec1-0         v           V          power-domain@25         '                           jvdec2-0         v           V             power-domain@26         '              !            jvenc0-larb          v                        +            V       power-domain@27         '              "            jvenc1-larb          v           V             power-domain@18         '                     #       #      #         &  jvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           v                        +            V      power-domain@19         '           v           V          power-domain@20         '           v           V          power-domain@21         '                 Q        jhdmi_tx         V             power-domain@28         '              $       $   
        jimg-0 img-1         v                        +            V      power-domain@29         '           V          power-domain@30         '                    $      %           jipe ipe-0 ipe-1         v           V             power-domain@31         '         (     &       &      &      &      &           jcam-0 cam-1 cam-2 cam-3 cam-4           v                        +            V      power-domain@32         '            V          power-domain@33         '   !        V          power-domain@34         '   "        V                   power-domain@0          '            v           V          power-domain@1          '           v           V          power-domain@2          '           V          power-domain@3          '           V          power-domain@4          '                 5      7        jcsi_rx_top csi_rx_top1          V          power-domain@5          '              '           jether           V          power-domain@6          '                 X      n        jadsp adsp1                       +            v           V      power-domain@7          '                  g      "      n      2        jaudio audio1 audio2 audio3          v           V                   watchdog@10007000             mediatek,mt8195-wdt                  '     p                              .      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           '                                         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         '    p                      	                  (      pwrap@10024000            mediatek,mt8195-pwrap syscon            '    @                pwrap                                                    	  jspi wrap                  $                 pmic              mediatek,mt6359          {        S                       adc           mediatek,mt6359-auxadc                   mt6359codec       regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !        ,             H      buck_vgpu11         vgpu11                    7        \          ,           q                   H      buck_vmodem         vmodem                            \  *        ,         buck_vpu            vpu                   7        \          ,           q                   H      buck_vcore          vcore                              \          ,           q                   H      buck_vs2            vs2          5          j         ,             H      buck_vpa            vpa                    7        ,  ,      buck_vproc2         vproc2                    7        \  L        ,           q                   H      buck_vproc1         vproc1                    7        \  L        ,           q                   H      buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@        ,         ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z      ldo_vrf12           vrf12                               H      ldo_vusb            vusb             -         -        ,           H           B      ldo_vsram_proc2         vsram_proc2                            \  L        ,            H      ldo_vio18           vio18                             ,           H      ldo_vcamio          vcamio                          ldo_vcn18           vcn18            w@         w@        ,         ldo_vfe28           vfe28            *         *        ,   x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@        ,            H      ldo_vsram_others            vsram_others                               \          ,            H      ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !         H      ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *        ,         ldo_vio28           vio28            *         2Z         H      ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z           E      ldo_vcn33_2_bt          vcn33_2_bt           *         5g      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                   H      ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               \  *        ,            H      ldo_vufs            vufs                                 F      ldo_vm18            vm18                               H      ldo_vbbck           vbbck                     O         H      ldo_vsram_proc1         vsram_proc1                            \  L        ,            H      ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             '    p                            pmif spmimst                               E      (  jpmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $                                   +       mt6315@6              mediatek,mt6315-regulator           '          regulators     vbuck1          Vbcpu                     7        ,           \  j        q                   H            mt6315@7              mediatek,mt6315-regulator           '          regulators     vbuck1          Vgpu             	h         7        ,           \  j        q                   H           n               infra-iommu@10315000              mediatek,mt8195-iommu-infra         '    1P       P       P                                                                                         N      mailbox@10320000              mediatek,mt8195-gce         '    2        @                                                                 mailbox@10330000              mediatek,mt8195-gce         '    3        @                                                           o      scp@10500000              mediatek,mt8195-scp       0  '    P             r             p                 sram cfg l1tcm                               okay               )        mediatek/mt8195/scp.img            p      clock-controller@10720000             mediatek,mt8195-scp_adsp            '    r                               *      dsp@10803000              mediatek,mt8195-dsp          '    0                           	  cfg sram          ,        X         n         *          #      K  jadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             +           rx tx              ,   -      	  disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox                       '    `                                        ,      mailbox@10817000              mediatek,mt8195-adsp-mbox                       '    p                                        -      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           '                                   +                 6                  .         	  audiosys                                                               g      "      #      n      e      a      b      c      d      2   *            jclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  disabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                                                          	  jbaud bus            okay            default            /      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                                                          	  jbaud bus            okay            default            0               serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                                                          	  jbaud bus            okay            default            1               serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                                                         	  jbaud bus            okay            default            2      serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                                                         	  jbaud bus            okay            default            3      serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                                                         	  jbaud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           '                                    jmain                       okay                     syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           '     0                              '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                                                                     jparent-clk sel-clk spi-clk          okay            default            4        +       tpm@0         !    infineon,slb9670 tcg,tpm_tis-spi            '            ?I         thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         '                                                                        Q   5   6      $  ]lvts-calib-data-1 lvts-calib-data-2         n                    svs@1100bc00              mediatek,mt8195-svs         '                                                         jmain            Q   7   5      (  ]svs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           '                                              +                            *      0        jmain mm       	  disabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           '                                                           +      N        jmain mm       	  disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                                                             3        jparent-clk sel-clk spi-clk          okay            default            8        +          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                                                             4        jparent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '    0                                                        5        jparent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                                                            <        jparent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                                                            =        jparent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave           '                                                R        jspi                                   	  disabled          spi@1101e000              mediatek,mt8195-spi-slave           '                                                S        jspi                                   	  disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           '           @                              macirq        .  jaxi apb mac_main ptp_ref rmii_internal mac_cg         0     '       '         R      S      T   '                 R      S      T                                     +                         9           :           ;                                          okay          	  	rgmii-id               <        default sleep              =           >   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            '                 ^           '  '        7 8        I      ]               <         stmmac-axi-config           U           e           u                                    9      rx-queues-config                                   :   queue0                             queue1                             queue2                             queue3                                tx-queues-config                                   ;   queue0                                        queue1                                       queue2                                       queue3                                             usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           '            -     >              	  mac ippc            A                     ?                      +                                       /            B        jsys_ck ref_ck mcu_ck               ?      @                    &   A      g        okay            =host            E   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          '                       mac                                     ,      -                          $        /                     B      $  jsys_ck ref_ck mcu_ck dma_ck xhci_ck         okay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          '    #                                                                              jsource hclk source_cg           okay            default state_uhs              C           D        S           C         ] L         l         ~                                                        E           F      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          '    $                                                                      $        jsource hclk source_cg                                       okay            default state_uhs              G   H           G                         S           C                            		         	           I           J      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          '    %                                                                       I        jsource hclk source_cg                                      	  disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            '    '                                                                  Q   5   6      $  ]lvts-calib-data-1 lvts-calib-data-2         n                    usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           '    )             )>              	  mac ippc                                    K                 .      /                          $     '                     '         $  jsys_ck ref_ck mcu_ck dma_ck xhci_ck         &   A      h                 okay            E   B        	         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           '    *       -    *>              	  mac ippc            A            *        ?                      +                                      0                         '            '           jsys_ck ref_ck mcu_ck               L                    &   A      i        okay            E   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          '                       mac                                    1                         '           jsys_ck          okay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           '    +       -    +>              	  mac ippc            A            +        ?                      +                                      2                         '            '   	        jsys_ck ref_ck mcu_ck               M                    &   A      j        okay            E   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          '                       mac                                    3                         '   	        jsys_ck          okay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           '    /        @       	  pcie-mac                                 	3             8  A                                                            	=       N              	G          0        V      #      &      +      K   '         /  jpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                G                         O      	  	Vpcie-phy               +            S           	`                     `  	s                  P                      P                     P                     P           okay            default            Q   interrupt-controller             {                     S              P         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           '    /       @       	  pcie-mac                                 	3             8  A       $       $                  $       $                 	=       N              	G          (        W         X         Q   '         /  jpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                H                         R         	  	Vpcie-phy               +           S           	`                     `  	s                  S                      S                     S                     S           okay            default            T   interrupt-controller             {                     S              S         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         '    2                      9                     o   '      '           jspi sf axi                       +            okay            default            U   flash@0           jedec,spi-nor           '            ?u         	           	            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            '                                  +      usb3-tx-imp@184,1           '             	                  d      usb3-rx-imp@184,2           '             	                 c      usb3-intr@185           '             	                 b      usb3-tx-imp@186,1           '             	                  a      usb3-rx-imp@186,2           '             	                 `      usb3-intr@187           '             	                 _      usb2-intr-p0@188,1          '             	             usb2-intr-p1@188,2          '             	            usb2-intr-p2@189,1          '             	            usb2-intr-p3@189,2          '             	            pciephy-rx-ln1@190,1            '             	                  k      pciephy-tx-ln1-nmos@190,2           '             	                 j      pciephy-tx-ln1-pmos@191,1           '             	                  i      pciephy-rx-ln0@191,2            '             	                 h      pciephy-tx-ln0-nmos@192,1           '             	                  g      pciephy-tx-ln0-pmos@192,2           '             	                 f      pciephy-glb-intr@193            '             	                  e      dp-data@1ac         '                      lvts1-calib@1bc         '                5      lvts2-calib@1d0         '     8           6      svs-calib@580           '     d           7      socinfo-data1@7a0           '              t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A                     okay       usb-phy@0           '                             jref         	              L         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A                     okay       usb-phy@0           '                             jref         	              M         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         '                                mipi_tx0_pll                        	          	  disabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         '                                mipi_tx1_pll                        	          	  disabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '                 "                                                   V          ;      	  jmain dma                         +          	  disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '                "                                                    V         ;      	  jmain dma                         +            okay            M            W        default    pmic@34           mediatek,mt6360         '   4         {              e           IRQB            S      regulator             mediatek,mt6360-regulator           	   X        	   X        	   X   buck1         	  emi_vdd2             	'         w@        q                   H      buck2         	  emi_vddq                               q                   H      ldo1            mt6360_ldo1          O         6        q             ldo2            panel1_p1v8          w@         w@        q             ldo3            vmc_pmu          w@         2Z        q                  J      ldo5          	  vmch_pmu             2Z         2Z        q                  I      ldo6            mt6360_ldo6                              q             ldo7            emi_vmddr_en             w@         w@        q                H               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '                 "                                                   V         ;      	  jmain dma                         +          	  disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          '    0                              V      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '                 "                                                    Y          ;      	  jmain dma                         +            okay            default            Z        M       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '                "                                                    Y         ;      	  jmain dma                         +            okay            default            [        M       i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '                 "                                                   Y         ;      	  jmain dma                         +            okay            default            \        M       i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    0            "                                                   Y         ;      	  jmain dma                         +            okay            default            ]        M       i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    @            "                                                    Y         ;      	  jmain dma                         +            okay            M            ^        default       clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          '    P                              Y      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A                        +           okay       usb-phy@0           '                                jref da_ref          	              K      usb-phy@700         '                                  jref da_ref          Q   _   `   a        ]intr rx_imp tx_imp          	              R         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A                     okay       usb-phy@0           '                                jref da_ref          	              ?      usb-phy@700         '                                  jref da_ref          Q   b   c   d        ]intr rx_imp tx_imp          	              @         phy@11e80000              mediatek,mt8195-pcie-phy            '                     sif         Q   e   f   g   h   i   j   k      G  ]glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             +           	            okay               O      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           '                                 
  junipro mp           	          	  disabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           '             @            l          0                                                 job mmu gpu         	   m      (     +   
   +      +      +      +           	core0 core1 core2 core3 core4           okay            

   n      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          '                                  l      syscon@14000000           mediatek,mt8195-vppsys0 syscon          '                                 
   o                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma           '                     
   o                  
.              
B   p           +           
O   q                       <     o         o         o         o         o              
V         display@14002000              mediatek,mt8195-mdp3-fg         '                      
   o                                display@14003000              mediatek,mt8195-mdp3-stitch         '     0                
   o      0                        display@14004000              mediatek,mt8195-mdp3-hdr            '     @                
   o      @                  "      display@14005000              mediatek,mt8195-mdp3-aal            '     P                      F               
   o      P                  
           +         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '     `                
   o      `            
.    %                    display@14007000              mediatek,mt8195-mdp3-tdshp          '     p                
   o      p                  #      display@14008000              mediatek,mt8195-mdp3-color          '                           I               
   o                        $           +         display@14009000              mediatek,mt8195-mdp3-ovl            '                           J               
   o                        %           +           
O   q         display@1400a000              mediatek,mt8195-mdp3-padding            '                     
   o                                   +         display@1400b000              mediatek,mt8195-mdp3-tcc            '                     
   o                              dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '                     
   o                  
.    +                      
O   q              +           
V         mutex@1400f000            mediatek,mt8195-vpp-mutex           '                           P               
   o                                   +         smi@14010000              mediatek,mt8195-smi-sub-common          '                                               japb smi gals0           
a   r           +              s      smi@14011000              mediatek,mt8195-smi-sub-common          '                                              japb smi gals0           
a   r           +                    smi@14012000              mediatek,mt8195-smi-common-vpp          '                                                      japb smi gals0 gals1            +              r      larb@14013000             mediatek,mt8195-smi-larb            '    0                
n           
a   s                            japb smi            +              v      iommu@14018000            mediatek,mt8195-iommu-vpp           '                  8  
   t   u   v   w   x   y   z   {   |   }   ~                       R                             jbclk                          +              q      clock-controller@14e00000             mediatek,mt8195-wpesys          '                                         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         '                              clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         '    0                         larb@14e04000             mediatek,mt8195-smi-larb            '    @                
n           
a                               japb smi            +                    larb@14e05000             mediatek,mt8195-smi-larb            '    P                
n           
a   r                                  japb smi gals               +              x      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          '                                
   o   	                        mutex@14f01000            mediatek,mt8195-vpp-mutex           '                          {               
   o   	                    '           +         larb@14f02000             mediatek,mt8195-smi-larb            '                     
n           
a                                     japb smi gals               +                    larb@14f03000             mediatek,mt8195-smi-larb            '    0                
n           
a   s                                  japb smi gals               +              w      display@14f06000              mediatek,mt8195-mdp3-split          '    `                
   o   	  `                        +      ,           +         display@14f07000              mediatek,mt8195-mdp3-tcc            '    p                
   o   	  p                        dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           '                    
   o   	              
.                          
O                 +           
V         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           '                    
   o   	              
.                  
        
O                 +           
V         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           '                    
   o   	              
.                          
O   q              +           
V         display@14f0b000              mediatek,mt8195-mdp3-fg         '                    
   o   	                    	      display@14f0c000              mediatek,mt8195-mdp3-fg         '                    
   o   	                          display@14f0d000              mediatek,mt8195-mdp3-fg         '                    
   o   	                          display@14f0e000              mediatek,mt8195-mdp3-hdr            '                    
   o   	                          display@14f0f000              mediatek,mt8195-mdp3-hdr            '                    
   o   	                          display@14f10000              mediatek,mt8195-mdp3-hdr            '                     
   o   
                            display@14f11000              mediatek,mt8195-mdp3-aal            '                          i               
   o   
                               +         display@14f12000              mediatek,mt8195-mdp3-aal            '                           j               
   o   
                                +         display@14f13000              mediatek,mt8195-mdp3-aal            '    0                      k               
   o   
  0                  !           +         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '    @                
   o   
  @            
.                        display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '    P                
   o   
  P            
.                  $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '    `                
   o   
  `            
.                  %      display@14f17000              mediatek,mt8195-mdp3-tdshp          '    p                
   o   
  p                        display@14f18000              mediatek,mt8195-mdp3-tdshp          '                    
   o   
                    (      display@14f19000              mediatek,mt8195-mdp3-tdshp          '                    
   o   
                    )      display@14f1a000              mediatek,mt8195-mdp3-merge          '                    
   o   
                               +         display@14f1b000              mediatek,mt8195-mdp3-merge          '                    
   o   
                               +         display@14f1c000              mediatek,mt8195-mdp3-color          '                          t               
   o   
                               +         display@14f1d000              mediatek,mt8195-mdp3-color          '                    
   o   
                    u                                +         display@14f1e000              mediatek,mt8195-mdp3-color          '                          v               
   o   
                               +         display@14f1f000              mediatek,mt8195-mdp3-ovl            '                          w               
   o   
                                +           
O            display@14f20000              mediatek,mt8195-mdp3-padding            '                     
   o                                   +         display@14f21000              mediatek,mt8195-mdp3-padding            '                    
   o                                  +         display@14f22000              mediatek,mt8195-mdp3-padding            '                     
   o                                   +         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '    0                
   o     0            
.                          
O                 +           
V         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '    @                
   o     @            
.                          
O                 +           
V         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '    P                
   o     P            
.                          
O   q              +           
V         clock-controller@15000000             mediatek,mt8195-imgsys          '                                    $      larb@15001000             mediatek,mt8195-smi-larb            '                     
n   	        
a              $       $       $   
        japb smi gals               +                    smi@15002000              mediatek,mt8195-smi-sub-common          '                         $      $                 japb smi gals0           
a   r           +                    smi@15003000              mediatek,mt8195-smi-sub-common          '     0                   $       $       $   
        japb smi gals0           
a              +                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         '                                         larb@15120000             mediatek,mt8195-smi-larb            '                     
n   
        
a              $                  japb smi            +                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          '                              clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         '    "                                     larb@15230000             mediatek,mt8195-smi-larb            '    #                 
n           
a              $                  japb smi            +                    clock-controller@15330000             mediatek,mt8195-ipesys          '    3                               %      larb@15340000             mediatek,mt8195-smi-larb            '    4                 
n           
a              %      %           japb smi            +              y      clock-controller@16000000             mediatek,mt8195-camsys          '                                    &      larb@16001000             mediatek,mt8195-smi-larb            '                     
n           
a              &       &       &           japb smi gals               +                    larb@16002000             mediatek,mt8195-smi-larb            '                      
n           
a              &      &           japb smi            +              z      smi@16004000              mediatek,mt8195-smi-sub-common          '     @                   &       &       &           japb smi gals0           
a              +                    smi@16005000              mediatek,mt8195-smi-sub-common          '     P                   &      &                 japb smi gals0           
a   r           +                    larb@16012000             mediatek,mt8195-smi-larb            '                     
n           
a                                 japb smi            +               {      larb@16013000             mediatek,mt8195-smi-larb            '    0                
n           
a                                 japb smi            +                     larb@16014000             mediatek,mt8195-smi-larb            '    @                
n           
a                                 japb smi            +   !                 larb@16015000             mediatek,mt8195-smi-larb            '    P                
n           
a                                 japb smi            +   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa         '                                        clock-controller@1606f000             mediatek,mt8195-camsys_yuva         '                                        clock-controller@1608f000             mediatek,mt8195-camsys_rawb         '                                        clock-controller@160af000             mediatek,mt8195-camsys_yuvb         '    
                                    clock-controller@16140000             mediatek,mt8195-camsys_mraw         '                                         larb@16141000             mediatek,mt8195-smi-larb            '                    
n           
a              &              &           japb smi gals               +   "                 larb@16142000             mediatek,mt8195-smi-larb            '                     
n           
a                                 japb smi            +   "                 clock-controller@17200000             mediatek,mt8195-ccusys          '                                          larb@17201000             mediatek,mt8195-smi-larb            '                     
n           
a                                 japb smi            +              |      video-codec@18000000              mediatek,mt8195-vcodec-dec          
B   p        
O                          +            '                   @                A                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         '                       
O   q     q                 A                          jsel vdec lat top                  A                         +         video-codec@10000             mediatek,mtk-vcodec-lat         '                                         0  
O                                              A                          jsel vdec lat top                  A                         +         video-codec@25000             mediatek,mtk-vcodec-core            '     P                                   P  
O                                                                 A                          jsel vdec lat top                  A                         +            larb@1800d000             mediatek,mt8195-smi-larb            '                     
n           
a                                 japb smi            +                    larb@1800e000             mediatek,mt8195-smi-larb            '                     
n           
a                                japb smi            +                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         '                                         larb@1802e000             mediatek,mt8195-smi-larb            '                    
n           
a                                 japb smi            +                    clock-controller@1802f000             mediatek,mt8195-vdecsys         '                                        larb@1803e000             mediatek,mt8195-smi-larb            '                    
n           
a                                 japb smi            +              ~      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           '                                         clock-controller@190f3000             mediatek,mt8195-apusys_pll          '    0                         clock-controller@1a000000             mediatek,mt8195-vencsys         '                                    !      larb@1a010000             mediatek,mt8195-smi-larb            '                     
n           
a              !      !           japb smi            +                    video-codec@1a020000              mediatek,mt8195-vcodec-enc          '                   H  
O     `     a     b     c     d     v     w     x     y              U               
B   p           !         	  jvenc_sel                  @                         +                        +         jpgdec-master             mediatek,mt8195-jpgdec             +         0  
O     m     n     r     s     t     u                     +            A   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw           '                   0  
O     m     n     r     s     t     u              W                  !           jjpgdec             +         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw           '                   0  
O     m     n     r     s     t     u              X                  !           jjpgdec             +         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw           '                   0  
O   q     q     q     q     q     q                \                  "           jjpgdec             +            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           '                                    "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            '                                                 
                             jpgenc-master             mediatek,mt8195-jpgenc             +            
O   q     q     q     q                       +            A   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw           '                      
O     g     h     i     l              V                  !           jjpgenc             +         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw           '                      
O   q     q     q     q                [                  "           jjpgenc             +            larb@1b010000             mediatek,mt8195-smi-larb            '                     
n           
a   r           "      "                  japb smi gals               +              }      ovl@1c000000              mediatek,mt8195-disp-ovl            '                            |                  +                          
O              
                   rdma@1c002000             mediatek,mt8195-disp-rdma           '                            ~                  +                         
O               
                   color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           '     0                                        +                         
        0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           '     @                                        +                         
        @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           '     P                                        +                         
        P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           '     `                                        +                         
        `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         '     p                                        +                 	        
        p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         '                                             +                       *           jengine digital hs                      	Vdphy          	  disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            '                                             +                         
                  dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         '                                             +                       +           jengine digital hs                      	Vdphy          	  disabled          merge@1c014000            mediatek,mt8195-disp-merge          '    @                                        +                         
        @          dp-intf@1c015000              mediatek,mt8195-dp-intf         '    P                                           ,                    jpixel engine pll          	  disabled          mutex@1c016000            mediatek,mt8195-disp-mutex          '    `                                        +                         
        `            
.  U      larb@1c018000             mediatek,mt8195-smi-larb            '                    
n            
a                 (      (              japb smi gals               +                    larb@1c019000             mediatek,mt8195-smi-larb            '                    
n           
a   r              (                     japb smi gals               +              t      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          '                                      
                                              #      smi@1c01b000              mediatek,mt8195-smi-common-vdo          '                           %      &      )      $        japb smi gals0 gals1            +                    iommu@1c01f000            mediatek,mt8195-iommu-vdo           '                  8  
                                                                                        '        jbclk               +                    mutex@1c101000            mediatek,mt8195-disp-mutex          '                                            +              #           
                    
.        larb@1c102000             mediatek,mt8195-smi-larb            '                     
n           
a              #       #       #           japb smi gals               +                    larb@1c103000             mediatek,mt8195-smi-larb            '    0                
n           
a   r           #      #                  japb smi gals               +              u      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           '    @                                        #              +           
O      @        
        @            
V         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           '    P                                        #              +           
O   q   `        
        P            
V         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           '    `                                        #              +           
O      A        
        `            
V         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           '    p                                        #              +           
O   q   a        
        p            
V         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           '                                            #              +           
O      B        
                    
V         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           '                                            #              +           
O   q   b        
                    
V         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           '                                            #              +           
O      C        
                    
V         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           '                                            #              +           
O   q   c        
                    
V         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          '                                            #   	   #           jmerge merge_async              +           
                     
           #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          '                                            #   
   #           jmerge merge_async              +           
                     
           #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          '                                            #      #           jmerge merge_async              +           
                     
           #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          '                                            #      #           jmerge merge_async              +           
                     
           #         vpp-merge@1c110000            mediatek,mt8195-disp-merge          '                                             #      #           jmerge merge_async              +           
                      
           #         dp-intf@1c113000              mediatek,mt8195-dp-intf         '    0                                        +              #   /   #                 jpixel engine pll          	  disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  '    @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  
        @            P            p                                                          h     #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *              jmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             +           
O   q   d   q   e                           (     #   3   #   4   #   5   #   6   #   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx          '    P                 Q           ]dp_calibration_data            +                                
        	  disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx           '    `                 Q           ]dp_calibration_data            +                                
        	  disabled             thermal-zones      cpu0-thermal            
          
           
         trips      trip-alert          
 L        
          "passive                  trip-crit           
         
        	  "critical             cooling-maps       map0                     0     	   
                  cpu1-thermal            
          
           
         trips      trip-alert          
 L        
          "passive                  trip-crit           
         
        	  "critical             cooling-maps       map0                     0     	   
                  cpu2-thermal            
          
           
         trips      trip-alert          
 L        
          "passive                  trip-crit           
         
        	  "critical             cooling-maps       map0                     0     	   
                  cpu3-thermal            
          
           
         trips      trip-alert          
 L        
          "passive                  trip-crit           
         
        	  "critical             cooling-maps       map0                     0     	   
                  cpu4-thermal            
          
           
          trips      trip-alert          
 L        
          "passive                  trip-crit           
         
        	  "critical             cooling-maps       map0                     0                          cpu5-thermal            
          
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 X   	 "    6h    I                    thermal-sensor-1              generic-adc-thermal         n                          sensor-channel          X    ^h    nx        j      '  {  :    N     a  o  u0  /       @          P        u  `   a     Q p   D $   9 8   0 L   ) _   # s        (        8        H       
 X   	 "    6h    I                    thermal-sensor-2              generic-adc-thermal         n                          sensor-channel          X    ^h    nx        j      '  {  :    N     a  o  u0  /       @          P        u  `   a     Q p   D $   9 8   0 L   ) _   # s        (        8        H       
 X   	 "    6h    I                       	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 mmc0 mmc1 serial0 serial1 serial2 serial3 serial4 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up drive-strength-microamp bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 uart-has-rtscts mediatek,pad-select spi-max-frequency nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 reset-assert-us reset-deassert-us reset-gpios snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup dr_mode vusb33-supply bus-width hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells LDO_VIN1-supply LDO_VIN2-supply LDO_VIN3-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval default-state function color regulator-boot-on no-map io-channels io-channel-names temperature-lookup-table 