 T   8 H   (            x G                             .    radxa,nio-12l mediatek,mt8395 mediatek,mt8195                                    +            7Radxa NIO 12L         	   =embedded       aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/mailbox@10320000            a/soc/mailbox@10330000            f/soc/hdr-engine@1c114000             m/soc/mutex@1c016000          t/soc/mutex@1c101000          {/soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/i2c@11e02000            /soc/i2c@11e03000            /soc/i2c@11e04000           /soc/i2c@11e00000           
/soc/i2c@11e01000           /soc/ethernet@11021000          /soc/serial@11001100            !/soc/serial@11001200            )/soc/spi@11010000           ./soc/spi@11012000         cpus                         +       cpu@0           3cpu           arm,cortex-a55          ?            Cpsci            Q               eec3@        u  4                                    @                                 @                                                             cpu@100         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4                                    @                                 @                                                             cpu@200         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4                                    @                                 @                                                             cpu@300         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4                                    @                                 @                                                             cpu@400         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                      	                      
                 cpu@500         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                      	                      
                 cpu@600         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                      	                      
                 cpu@700         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                      	                      
                 cpu-map    cluster0       core0           #         core1           #         core2           #         core3           #         core4           #         core5           #         core6           #         core7           #               idle-states         'psci       cpu-retention-l           arm,idle-state          4           K        \   2        m   _        }  D                 cpu-retention-b           arm,idle-state          4           K        \   -        m           }                   cpu-off-l             arm,idle-state          4          K        \   7        m           }  H                 cpu-off-b             arm,idle-state          4          K        \   2        m           }                      l2-cache0             cache                                    @                                                l2-cache1             cache                                    @                                          	      l3-cache              cache                                     @                                        dsu-pmu           arm,dsu-pmu                                                                fail          dmic-codec            dmic-codec                        2      mt8195-sound                     	  disabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             ,      oscillator-26m            fixed-clock                     e        clk26m                   oscillator-32k            fixed-clock                     e           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw          ?                 0               *                    opp-table-gpu             operating-points-v2          D           u   opp-390000000           O    >        V 	h      opp-410000000           O    p        V 	      opp-431000000           O            V 	      opp-473000000           O    1h@        V 	<      opp-515000000           O    F        V 	<      opp-556000000           O    !#         V 	Ҧ      opp-598000000           O    #        V 	      opp-640000000           O    &%         V 	      opp-670000000           O    'c        V 
      opp-700000000           O    )'         V 
L      opp-730000000           O    +        V 
}      opp-760000000           O    -L         V 
`      opp-790000000           O    /q        V 
4      opp-820000000           O    05         V       opp-850000000           O    2        V @      opp-880000000           O    4s         V q         pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0            Jsmc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus           d        k                          interrupt-controller@c000000              arm,gic-v3          v                                            ?                                          	                     ppi-partitions     interrupt-partition-0                                        interrupt-partition-1                                              syscon@10000000            mediatek,mt8195-topckgen syscon         ?                                          syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          ?                                                    syscon@10003000           mediatek,mt8195-pericfg syscon          ?     0                              B      pinctrl@10005000              mediatek,mt8195-pinctrl         ?     P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                                                                                    v                          eth-default-pins               >   pins-cc           U  V  W  X        &         pins-mdio             Y  Z         5      pins-power            [   \          B      pins-rst              ]       pins-rxd              Q  R  S  T      pins-txd              M  N  O  P        &            eth-sleep-pins             ?   pins-cc           U   V   W   X       pins-mdio             Y   Z          N         [      pins-rxd              Q   R   S   T       pins-txd              M   N   O   P          i2c2-pins              c   pins-bus                        i          &           v           i2c4-pins              f   pins-bus                        i          v           i2c6-pins              \   pins                         N         mmc0-default-pins              G   pins-clk              z           f        &         pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y        i   e        &            5      pins-rst              x        i   e        &            mmc0-uhs-pins              H   pins-clk              z           f        &         pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y        i   e        &            5      pins-ds                      f        &         pins-rst              x        i   e        &            mmc1-default-pins              K   pins-clk              o           f        &         pins-cmd-dat              n  p  q  r  s        i   e        &            5         mmc1-detect-pins               L   pins-insert                     i         mt6360-pins            ]   pins-irq              d   e          5         i         pcie0-default-pins             W   pins-bus                           i         pcie1-default-pins             Z   pins-bus                            N         spi1-default-pins              8   pins-bus                             N         spi2-default-pins              9   pins-bus                             N         uart0-pins             3   pins-bus              b  c         uart1-pins             4   pins-bus              f  g         usb3p0-default-pins            C   pins-vbus             ?         5         usb2p0-default-pins            R   pins-iddig                     5         i      pins-vbus                               wifi-vreg-pins                pins-wifi-pmu-en              A          B      pins-wifi-vreg-en             C             syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            ?     `           power-controller          !    mediatek,mt8195-power-controller                         +                          /   power-domain@8          ?                        +                             power-domain@9          ?   	                            mfg alt                                 +                             power-domain@10         ?   
                  power-domain@11         ?                     power-domain@12         ?                     power-domain@13         ?                     power-domain@14         ?                           power-domain@15         ?                                   	      @      A      K                                                                                                                                vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                   +                  power-domain@16         ?         8              $      %      &      '      (      )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                 +                  power-domain@17         ?                                       vppsys1 vppsys1-0 vppsys1-1                              power-domain@22         ?               !      !      !      !         $  wepsys-0 wepsys-1 wepsys-2 wepsys-3                              power-domain@23         ?              "            vdec0-0                                 +                   power-domain@24         ?              #            vdec1-0                              power-domain@25         ?              $            vdec2-0                                 power-domain@26         ?              %            venc0-larb                                  +                   power-domain@27         ?              &            venc1-larb                                  power-domain@18         ?                     '       '      '         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                   +                  power-domain@19         ?                                power-domain@20         ?                                power-domain@21         ?                 Q        hdmi_tx                      power-domain@28         ?              (       (   
        img-0 img-1                                 +                  power-domain@29         ?                     power-domain@30         ?                    (      )           ipe ipe-0 ipe-1                                 power-domain@31         ?         (     *       *      *      *      *           cam-0 cam-1 cam-2 cam-3 cam-4                                   +                  power-domain@32         ?                      power-domain@33         ?   !                  power-domain@34         ?   "                           power-domain@0          ?                                 power-domain@1          ?                                power-domain@2          ?                     power-domain@3          ?                     power-domain@4          ?                 5      7        csi_rx_top csi_rx_top1                    power-domain@5          ?              +           ether                     power-domain@6          ?                 X      n        adsp adsp1                       +                             power-domain@7          ?                  g      "      n      2        audio audio1 audio2 audio3                                        watchdog@10007000             mediatek,mt8195-wdt                  ?     p                              2      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           ?                                         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         ?    p                      	                  ,      pwrap@10024000            mediatek,mt8195-pwrap syscon            ?    @                pwrap                                                    	  spi wrap                   $                 pmic              mediatek,mt6359                  v           '            adc           mediatek,mt6359-auxadc          ;         mt6359codec       regulators            mediatek,mt6359-regulator      buck_vs1            Mvs1         \ 5         t !                           buck_vgpu11         Mvgpu11          \         t 7                                                      buck_vmodem         Mvmodem          \         t           *                 buck_vpu            Mvpu         \         t 7                                                      buck_vcore          Mvcore           \         t                                                                   buck_vs2            Mvs2         \ 5         t j                            buck_vpa            Mvpa         \          t 7          ,      buck_vproc2         Mvproc2          \         t 7          L                                            buck_vproc1         Mvproc1          \         t 7          L                                            buck_vcore_sshub            Mvcore_sshub         \         t 7      buck_vgpu11_sshub           Mvgpu11_sshub            \         t 7      ldo_vaud18          Mvaud18          \ w@        t w@                          ldo_vsim1           Mvsim1           \         t /M`      ldo_vibr            Mvibr            \ O        t 2Z           d      ldo_vrf12           Mvrf12           \         t                 ldo_vusb            Mvusb            \ -        t -                              D      ldo_vsram_proc2         Mvsram_proc2         \          t           L                          ldo_vio18           Mvio18           \         t                          ldo_vcamio          Mvcamio          \         t                ldo_vcn18           Mvcn18           \ w@        t w@                 ldo_vfe28           Mvfe28           \ *        t *           x      ldo_vcn13           Mvcn13           \         t        ldo_vcn33_1_bt          Mvcn33_1_bt          \ *        t 5g      ldo_vcn33_1_wifi            Mvcn33_1_wifi            \ *        t 5g      ldo_vaux18          Mvaux18          \ w@        t w@                          ldo_vsram_others            Mvsram_others            \ q        t q                                      ldo_vefuse          Mvefuse          \         t       ldo_vxo22           Mvxo22           \ w@        t !               ldo_vrfck           Mvrfck           \ `        t       ldo_vrfck_1         Mvrfck           \         t j       ldo_vbif28          Mvbif28          \ *        t *                 ldo_vio28           Mvio28           \ *        t 2Z               ldo_vemc            Mvemc            \ ,@         t 2Z      ldo_vemc_1          Mvemc            \ &%        t 2Z           I      ldo_vcn33_2_bt          Mvcn33_2_bt          \ 2Z        t 2Z      ldo_vcn33_2_wifi            Mvcn33_2_wifi            \ *        t 5g      ldo_va12            Mva12            \ O        t                 ldo_va09            Mva09            \ 5         t O      ldo_vrf18           Mvrf18           \         t P      ldo_vsram_md          	  Mvsram_md            \          t           *                          ldo_vufs            Mvufs            \         t            J      ldo_vm18            Mvm18            \         t                ldo_vbbck           Mvbbck           \         t O               ldo_vsram_proc1         Mvsram_proc1         \          t           L                          ldo_vsim2           Mvsim2           \         t /M`      ldo_vsram_others_sshub          Mvsram_others_sshub          \          t          rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             ?    p                            pmif spmimst                               E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux                $                                   +       pmic@6            mediatek,mt6315-regulator           ?          regulators     vbuck1          MVbcpu           \         t 7                                                 
            pmic@7            mediatek,mt6315-regulator           ?          regulators     vbuck1          MVgpu            \         t 7                                                       infra-iommu@10315000              mediatek,mt8195-iommu-infra         ?    1P       P       P                                                                                         T      mailbox@10320000              mediatek,mt8195-gce         ?    2        @                                                                 mailbox@10330000              mediatek,mt8195-gce         ?    3        @                                                           v      scp@10500000              mediatek,mt8195-scp       0  ?    P             r             p                 sram cfg l1tcm                               okay               -           w      clock-controller@10720000             mediatek,mt8195-scp_adsp            ?    r                               .      dsp@10803000              mediatek,mt8195-dsp          ?    0                           	  cfg sram          ,        X         n         .          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             /           rx tx           )   0   1      	  disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox                       ?    `                                        0      mailbox@10817000              mediatek,mt8195-adsp-mbox                       ?    p                                        1      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           ?                     0              /                 6               B   2         	  Iaudiosys                                                               g      "      #      n      e      a      b      c      d      2   .            clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  disabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                          	  baud bus            okay            U   3        _default       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                          	  baud bus            okay            U   4        _default       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                          	  baud bus          	  disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                         	  baud bus          	  disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                         	  baud bus          	  disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                         	  baud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           ?                                    main            ;         	  disabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           ?     0                              +      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                                     parent-clk sel-clk spi-clk        	  disabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         ?                                                         B               m   5   6      $  ylvts-calib-data-1 lvts-calib-data-2                             svs@1100bc00              mediatek,mt8195-svs         ?                                                         main            m   7   5      (  ysvs-calibration-data t-calibration-data         B              Isvs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           ?                                              /                            *      0        main mm       	  disabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           ?                                                           +      N        main mm       	  disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                             3        parent-clk sel-clk spi-clk          okay            U   8        _default                   spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                             4        parent-clk sel-clk spi-clk          okay            U   9        _default                   spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?    0                                                        5        parent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                            <        parent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                            =        parent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave           ?                                                R        spi                                    	  disabled          spi@1101e000              mediatek,mt8195-spi-slave           ?                                                S        spi                                    	  disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           ?           @                              macirq        .  axi apb mac_main ptp_ref rmii_internal mac_cg         0     +       +         R      S      T   +                  R      S      T                                     /                         :           ;           <                   !           ,            okay            9rgmii-rxid          B   =        _default sleep           U   >        M   ?        W           l        }      ]                  N     mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            ?              =         stmmac-axi-config                                                                     :      rx-queues-config                                   ;   queue0                             queue1                             queue2                             queue3                                tx-queues-config                        4           <   queue0          F                    R          queue1          F                    R         queue2          F                    R         queue3          F                    R               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?            -     >              	  mac ippc            d                     ?                      +                                       /            B        sys_ck ref_ck mcu_ck            `   @      A            e        s   B      g        okay            _default         U   C        host                        D   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       mac                                      ,      -                          $        /                     B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         okay               E      port       endpoint               F           `            mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    #                                                                              source hclk source_cg           okay            _default state_uhs           U   G        M   H                             L         	         	         	'         	6         	E         	M         	S        	a   I        	m   J      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    $                                                                      $        source hclk source_cg                                        okay            _default state_uhs           U   K   L        M   K                             	z        	                  	         	E         	         	        	a   M        	m   N      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    %                                                                       I        source hclk source_cg                                       	  disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            ?    '                                                    B              m   5   6      $  ylvts-calib-data-1 lvts-calib-data-2                             usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           ?    )             )>              	  mac ippc                                 `   O                  .      /                          $     +                     +         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         s   B      h         e        okay             	           D           P        	         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?    *       -    *>              	  mac ippc            d            *        ?                      +                                       0                         +            +           sys_ck ref_ck mcu_ck            `   Q            e        s   B      i        okay            _default         U   R           D   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       mac                                     1                         +           sys_ck          okay               P         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?    +       -    +>              	  mac ippc            d            +        ?                      +                                       2                         +            +   	        sys_ck ref_ck mcu_ck            `   S            e        s   B      j      	  disabled       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       mac                                     3                         +   	        sys_ck        	  disabled             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           3pci                      +           ?    /        @       	  pcie-mac                                 	             8  d                                                            	       T              	          0        V      #      &      +      K   +         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                 G                      `   U      	  	pcie-phy               /            v           
	                     `  
                  V                      V                     V                     V           okay            _default         U   W   interrupt-controller                                  v              V         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           3pci                      +           ?    /       @       	  pcie-mac                                 	             8  d       $       $                  $       $                 	       T              	          (        W         X         Q   +         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                 H                      `   X         	  	pcie-phy               /           v           
	                     `  
                  Y                      Y                     Y                     Y           okay            _default         U   Z   interrupt-controller                                  v              Y         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         ?    2                      9                     o   +      +           spi sf axi                       +          	  disabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            ?                                  +      usb3-tx-imp@184,1           ?             
*                  l      usb3-rx-imp@184,2           ?             
*                 k      usb3-intr@185           ?             
*                 j      usb3-tx-imp@186,1           ?             
*                  i      usb3-rx-imp@186,2           ?             
*                 h      usb3-intr@187           ?             
*                 g      usb2-intr-p0@188,1          ?             
*             usb2-intr-p1@188,2          ?             
*            usb2-intr-p2@189,1          ?             
*            usb2-intr-p3@189,2          ?             
*            pciephy-rx-ln1@190,1            ?             
*                  s      pciephy-tx-ln1-nmos@190,2           ?             
*                 r      pciephy-tx-ln1-pmos@191,1           ?             
*                  q      pciephy-rx-ln0@191,2            ?             
*                 p      pciephy-tx-ln0-nmos@192,1           ?             
*                  o      pciephy-tx-ln0-pmos@192,2           ?             
*                 n      pciephy-glb-intr@193            ?             
*                  m      dp-data@1ac         ?                      lvts1-calib@1bc         ?                5      lvts2-calib@1d0         ?     8           6      svs-calib@580           ?     d           7      socinfo-data1@7a0           ?              t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           d                     okay       usb-phy@0           ?                             ref         
/              Q         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           d                   	  disabled       usb-phy@0           ?                             ref         
/              S         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         ?                                mipi_tx0_pll                        
/          	  disabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         ?                                mipi_tx1_pll                        
/          	  disabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                                   [          ;      	  main dma                         +          	  disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                "                                                    [         ;      	  main dma                         +            okay            e         U   \        _default    pmic@34           mediatek,mt6360         ?   4        '      e           IRQB                     v           U   ]   charger           mediatek,mt6360-chg         
: @   usb-otg-vbus-regulator          Musb-otg-vbus            \ C(        t X           E         regulator             mediatek,mt6360-regulator           
S   ^        
c   _   buck1         	  Memi_vdd2            \         t                                   buck2         	  Memi_vddq            \         t                                        _      ldo1            Mext_lcd_3v3         \ 2Z        t 2Z                              ldo2            Mpanel1_p1v8         \ w@        t w@                     ldo3            Mvmc_pmu         \ O        t 6                          N      ldo5          	  Mvmch_pmu            \ 2Z        t 2Z                                   M      ldo6            Mmt6360_ldo6         \          t                        ldo7            Memi_vmddr_en            \          t                                    typec             mediatek,mt6360-tcpc            '      d           PD_IRQB    connector             usb-c-connector         
sUSB-C           
ydual            
         
dual            
sink            
"d        
",   ports                        +       port@0          ?       endpoint               `           F         port@2          ?      endpoint               a           e                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                                   [         ;      	  main dma                         +          	  disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          ?    0                              [      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                                    b          ;      	  main dma                         +          	  disabled          i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                "                                                    b         ;      	  main dma                         +          	  disabled          i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                                   b         ;      	  main dma                         +            okay            e         U   c        _default    typec-mux@48              ite,it5205          ?   H         
         
        
   d   port       endpoint               e           a               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    0            "                                                   b         ;      	  main dma                         +          	  disabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    @            "                                                    b         ;      	  main dma                         +            okay            e         U   f        _default       clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          ?    P                              b      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           d                        /           okay       usb-phy@0           ?                                ref da_ref          
/              O      usb-phy@700         ?                                  ref da_ref          m   g   h   i        yintr rx_imp tx_imp          
/              X         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           d                     okay       usb-phy@0           ?                                ref da_ref          
/              @      usb-phy@700         ?                                  ref da_ref          m   j   k   l        yintr rx_imp tx_imp          
/              A         phy@11e80000              mediatek,mt8195-pcie-phy            ?                     sif         m   m   n   o   p   q   r   s      G  yglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             /           
/            okay               U      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           ?                                 
  unipro mp           
/          	  disabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           ?             @            t          0                                                 job mmu gpu         
   u      (     /   
   /      /      /      /           core0 core1 core2 core3 core4           okay                     clock-controller@13fbf000             mediatek,mt8195-mfgcfg          ?                                  t      syscon@14000000           mediatek,mt8195-vppsys0 syscon          ?                                 "   v                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma           ?                     "   v                  :              N   w           /           [   x                       <  )   v         v         v         v         v              b         display@14002000              mediatek,mt8195-mdp3-fg         ?                      "   v                                display@14003000              mediatek,mt8195-mdp3-stitch         ?     0                "   v      0                        display@14004000              mediatek,mt8195-mdp3-hdr            ?     @                "   v      @                  "      display@14005000              mediatek,mt8195-mdp3-aal            ?     P                      F               "   v      P                  
           /         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?     `                "   v      `            :    %                    display@14007000              mediatek,mt8195-mdp3-tdshp          ?     p                "   v      p                  #      display@14008000              mediatek,mt8195-mdp3-color          ?                           I               "   v                        $           /         display@14009000              mediatek,mt8195-mdp3-ovl            ?                           J               "   v                        %           /           [   x         display@1400a000              mediatek,mt8195-mdp3-padding            ?                     "   v                                   /         display@1400b000              mediatek,mt8195-mdp3-tcc            ?                     "   v                              dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?                     "   v                  :    +                      [   x              /           b         mutex@1400f000            mediatek,mt8195-vpp-mutex           ?                           P               "   v                                   /         smi@14010000              mediatek,mt8195-smi-sub-common          ?                                               apb smi gals0           m   y           /              z      smi@14011000              mediatek,mt8195-smi-sub-common          ?                                              apb smi gals0           m   y           /                    smi@14012000              mediatek,mt8195-smi-common-vpp          ?                                                      apb smi gals0 gals1            /              y      larb@14013000             mediatek,mt8195-smi-larb            ?    0                z           m   z                            apb smi            /              }      iommu@14018000            mediatek,mt8195-iommu-vpp           ?                  8     {   |   }   ~                                            R                             bclk                          /              x      clock-controller@14e00000             mediatek,mt8195-wpesys          ?                                   !      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         ?                              clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         ?    0                         larb@14e04000             mediatek,mt8195-smi-larb            ?    @                z           m              !      !           apb smi            /                    larb@14e05000             mediatek,mt8195-smi-larb            ?    P                z           m   y           !      !                 apb smi gals               /                    syscon@14f00000           mediatek,mt8195-vppsys1 syscon          ?                                "   v   	                         mutex@14f01000            mediatek,mt8195-vpp-mutex           ?                          {               "   v   	                     '           /         larb@14f02000             mediatek,mt8195-smi-larb            ?                     z           m                                       apb smi gals               /                    larb@14f03000             mediatek,mt8195-smi-larb            ?    0                z           m   z                                    apb smi gals               /              ~      display@14f06000              mediatek,mt8195-mdp3-split          ?    `                "   v   	  `                          +       ,           /         display@14f07000              mediatek,mt8195-mdp3-tcc            ?    p                "   v   	  p                         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           ?                    "   v   	              :                           [                 /           b         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           ?                    "   v   	              :                   
        [                 /           b         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           ?                    "   v   	              :                           [   x              /           b         display@14f0b000              mediatek,mt8195-mdp3-fg         ?                    "   v   	                     	      display@14f0c000              mediatek,mt8195-mdp3-fg         ?                    "   v   	                           display@14f0d000              mediatek,mt8195-mdp3-fg         ?                    "   v   	                           display@14f0e000              mediatek,mt8195-mdp3-hdr            ?                    "   v   	                           display@14f0f000              mediatek,mt8195-mdp3-hdr            ?                    "   v   	                           display@14f10000              mediatek,mt8195-mdp3-hdr            ?                     "   v   
                             display@14f11000              mediatek,mt8195-mdp3-aal            ?                          i               "   v   
                                /         display@14f12000              mediatek,mt8195-mdp3-aal            ?                           j               "   v   
                                 /         display@14f13000              mediatek,mt8195-mdp3-aal            ?    0                      k               "   v   
  0                   !           /         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    @                "   v   
  @            :                         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    P                "   v   
  P            :                   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    `                "   v   
  `            :                   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          ?    p                "   v   
  p                         display@14f18000              mediatek,mt8195-mdp3-tdshp          ?                    "   v   
                     (      display@14f19000              mediatek,mt8195-mdp3-tdshp          ?                    "   v   
                     )      display@14f1a000              mediatek,mt8195-mdp3-merge          ?                    "   v   
                                /         display@14f1b000              mediatek,mt8195-mdp3-merge          ?                    "   v   
                                /         display@14f1c000              mediatek,mt8195-mdp3-color          ?                          t               "   v   
                                /         display@14f1d000              mediatek,mt8195-mdp3-color          ?                    "   v   
                    u                                 /         display@14f1e000              mediatek,mt8195-mdp3-color          ?                          v               "   v   
                                /         display@14f1f000              mediatek,mt8195-mdp3-ovl            ?                          w               "   v   
                                 /           [            display@14f20000              mediatek,mt8195-mdp3-padding            ?                     "   v                                    /         display@14f21000              mediatek,mt8195-mdp3-padding            ?                    "   v                                   /         display@14f22000              mediatek,mt8195-mdp3-padding            ?                     "   v                                    /         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    0                "   v     0            :                           [                 /           b         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    @                "   v     @            :                           [                 /           b         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    P                "   v     P            :                           [   x              /           b         clock-controller@15000000             mediatek,mt8195-imgsys          ?                                    (      larb@15001000             mediatek,mt8195-smi-larb            ?                     z   	        m              (       (       (   
        apb smi gals               /                    smi@15002000              mediatek,mt8195-smi-sub-common          ?                         (      (                 apb smi gals0           m   y           /                    smi@15003000              mediatek,mt8195-smi-sub-common          ?     0                   (       (       (   
        apb smi gals0           m              /                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         ?                                         larb@15120000             mediatek,mt8195-smi-larb            ?                     z   
        m              (                  apb smi            /                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          ?                              clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         ?    "                                     larb@15230000             mediatek,mt8195-smi-larb            ?    #                 z           m              (                  apb smi            /                    clock-controller@15330000             mediatek,mt8195-ipesys          ?    3                               )      larb@15340000             mediatek,mt8195-smi-larb            ?    4                 z           m              )      )           apb smi            /                    clock-controller@16000000             mediatek,mt8195-camsys          ?                                    *      larb@16001000             mediatek,mt8195-smi-larb            ?                     z           m              *       *       *           apb smi gals               /                    larb@16002000             mediatek,mt8195-smi-larb            ?                      z           m              *      *           apb smi            /                    smi@16004000              mediatek,mt8195-smi-sub-common          ?     @                   *       *       *           apb smi gals0           m              /                    smi@16005000              mediatek,mt8195-smi-sub-common          ?     P                   *      *                 apb smi gals0           m   y           /                    larb@16012000             mediatek,mt8195-smi-larb            ?                     z           m                                 apb smi            /                     larb@16013000             mediatek,mt8195-smi-larb            ?    0                z           m                                 apb smi            /                     larb@16014000             mediatek,mt8195-smi-larb            ?    @                z           m                                 apb smi            /   !                 larb@16015000             mediatek,mt8195-smi-larb            ?    P                z           m                                 apb smi            /   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa         ?                                        clock-controller@1606f000             mediatek,mt8195-camsys_yuva         ?                                        clock-controller@1608f000             mediatek,mt8195-camsys_rawb         ?                                        clock-controller@160af000             mediatek,mt8195-camsys_yuvb         ?    
                                    clock-controller@16140000             mediatek,mt8195-camsys_mraw         ?                                         larb@16141000             mediatek,mt8195-smi-larb            ?                    z           m              *              *           apb smi gals               /   "                 larb@16142000             mediatek,mt8195-smi-larb            ?                     z           m                                 apb smi            /   "                 clock-controller@17200000             mediatek,mt8195-ccusys          ?                                          larb@17201000             mediatek,mt8195-smi-larb            ?                     z           m                                 apb smi            /                    video-codec@18000000              mediatek,mt8195-vcodec-dec          N   w        [                          +            ?                   @                d                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         ?                       [   x     x                 A   "      "                 sel vdec lat top                   A                         /         video-codec@10000             mediatek,mtk-vcodec-lat         ?                                         0  [                                              A   "      "                 sel vdec lat top                   A                         /         video-codec@25000             mediatek,mtk-vcodec-core            ?     P                                   P  [                                                                 A   #      #                 sel vdec lat top                   A                         /            larb@1800d000             mediatek,mt8195-smi-larb            ?                     z           m              "       "            apb smi            /                    larb@1800e000             mediatek,mt8195-smi-larb            ?                     z           m                    "            apb smi            /                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         ?                                   "      larb@1802e000             mediatek,mt8195-smi-larb            ?                    z           m              #       #            apb smi            /                    clock-controller@1802f000             mediatek,mt8195-vdecsys         ?                                  #      larb@1803e000             mediatek,mt8195-smi-larb            ?                    z           m                    $            apb smi            /                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           ?                                  $      clock-controller@190f3000             mediatek,mt8195-apusys_pll          ?    0                         clock-controller@1a000000             mediatek,mt8195-vencsys         ?                                    %      larb@1a010000             mediatek,mt8195-smi-larb            ?                     z           m              %      %           apb smi            /                    video-codec@1a020000              mediatek,mt8195-vcodec-enc          ?                   H  [     `     a     b     c     d     v     w     x     y              U               N   w           %         	  venc_sel                   @                         /                        +         jpgdec-master             mediatek,mt8195-jpgdec             /         0  [     m     n     r     s     t     u                     +            d   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw           ?                   0  [     m     n     r     s     t     u              W                  %           jpgdec             /         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw           ?                   0  [     m     n     r     s     t     u              X                  %           jpgdec             /         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw           ?                   0  [   x     x     x     x     x     x                \                  &           jpgdec             /            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           ?                                    &      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            ?                    )                             "                             jpgenc-master             mediatek,mt8195-jpgenc             /            [   x     x     x     x                       +            d   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw           ?                      [     g     h     i     l              V                  %           jpgenc             /         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw           ?                      [   x     x     x     x                [                  &           jpgenc             /            larb@1b010000             mediatek,mt8195-smi-larb            ?                     z           m   y           &      &                  apb smi gals               /                    ovl@1c000000              mediatek,mt8195-disp-ovl            ?                            |                  /                          [              "                   rdma@1c002000             mediatek,mt8195-disp-rdma           ?                            ~                  /                         [               "                   color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           ?     0                                        /                         "        0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           ?     @                                        /                         "        @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           ?     P                                        /                         "        P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           ?     `                                        /                         "        `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         ?     p                                        /                 	        "        p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         ?                                             /                       *           engine digital hs           `           	dphy          	  disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            ?                                             /                         "                  dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         ?                                             /                       +           engine digital hs           `           	dphy          	  disabled          merge@1c014000            mediatek,mt8195-disp-merge          ?    @                                        /                         "        @          dp-intf@1c015000              mediatek,mt8195-dp-intf         ?    P                                           ,                    pixel engine pll          	  disabled          mutex@1c016000            mediatek,mt8195-disp-mutex          ?    `                                        /                         "        `            :  U      larb@1c018000             mediatek,mt8195-smi-larb            ?                    z            m                 (      (              apb smi gals               /                    larb@1c019000             mediatek,mt8195-smi-larb            ?                    z           m   y              (                     apb smi gals               /              {      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          ?                     )                 "                                              '      smi@1c01b000              mediatek,mt8195-smi-common-vdo          ?                           %      &      )      $        apb smi gals0 gals1            /                    iommu@1c01f000            mediatek,mt8195-iommu-vdo           ?                  8                                                                                          '        bclk               /                    mutex@1c101000            mediatek,mt8195-disp-mutex          ?                                            /              '           "                    :        larb@1c102000             mediatek,mt8195-smi-larb            ?                     z           m              '       '       '           apb smi gals               /                    larb@1c103000             mediatek,mt8195-smi-larb            ?    0                z           m   y           '      '                  apb smi gals               /              |      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           ?    @                                        '              /           [      @        "        @            b         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           ?    P                                        '              /           [   x   `        "        P            b         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           ?    `                                        '              /           [      A        "        `            b         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           ?    p                                        '              /           [   x   a        "        p            b         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           ?                                            '              /           [      B        "                    b         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           ?                                            '              /           [   x   b        "                    b         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           ?                                            '              /           [      C        "                    b         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           ?                                            '              /           [   x   c        "                    b         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          ?                                            '   	   '           merge merge_async              /           "                             B   '         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          ?                                            '   
   '           merge merge_async              /           "                             B   '         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          ?                                            '      '           merge merge_async              /           "                             B   '         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          ?                                            '      '           merge merge_async              /           "                             B   '         vpp-merge@1c110000            mediatek,mt8195-disp-merge          ?                                             '      '           merge merge_async              /           "                              B   '         dp-intf@1c113000              mediatek,mt8195-dp-intf         ?    0                                        /              '   /   '                 pixel engine pll          	  disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  ?    @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  "        @            P            p                                                          h     '   %   '       '   #   '   !   '   $   '   "   '   1   '   &   '   '   '   (   '   )   '   *              mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             /           [   x   d   x   e                           (  B   '   3   '   4   '   5   '   6   '   7      E  Ivdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx          ?    P                 m           ydp_calibration_data            /                                        	  disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx           ?    `                 m           ydp_calibration_data            /                                        	  disabled             thermal-zones      cpu0-thermal                                          trips      trip-alert          
 L                   Epassive                  trip-crit           
                 	   Ecritical             cooling-maps       map0            !         0  &                        cpu1-thermal                                          trips      trip-alert          
 L                   Epassive                  trip-crit           
                 	   Ecritical             cooling-maps       map0            !         0  &                        cpu2-thermal                                          trips      trip-alert          
 L                   Epassive                  trip-crit           
                 	   Ecritical             cooling-maps       map0            !         0  &                        cpu3-thermal                                          trips      trip-alert          
 L                   Epassive                  trip-crit           
                 	   Ecritical             cooling-maps       map0            !         0  &                        cpu4-thermal                                           trips      trip-alert          
 L                   Epassive                  trip-crit           
                 	   Ecritical             cooling-maps       map0            !         0  &                        cpu5-thermal                                          trips      trip-alert          
 L                   Epassive                  trip-crit           
                 	   Ecritical             cooling-maps       map0            !         0  &                        cpu6-thermal                                          trips      trip-alert          
 L                   Epassive                  trip-crit           
                 	   Ecritical             cooling-maps       map0            !         0  &                        cpu7-thermal                                          trips      trip-alert          
 L                   Epassive                  trip-crit           
                 	   Ecritical             cooling-maps       map0            !         0  &                        vpu0-thermal                                          trips      trip-alert          
 L                   Epassive       trip-crit           
                 	   Ecritical                vpu1-thermal                                       	   trips      trip-alert          
 L                   Epassive       trip-crit           
                 	   Ecritical                gpu-thermal                                    
   trips      trip-alert          
 L                   Epassive       trip-crit           
                 	   Ecritical                gpu1-thermal                                          trips      trip-alert          
 L                   Epassive       trip-crit           
                 	   Ecritical                vdec-thermal                                          trips      trip-alert          
 L                   Epassive       trip-crit           
                 	   Ecritical                img-thermal                                       trips      trip-alert          
 L                   Epassive       trip-crit           
                 	   Ecritical                infra-thermal                                         trips      trip-alert          
 L                   Epassive       trip-crit           
                 	   Ecritical                cam0-thermal                                          trips      trip-alert          
 L                   Epassive       trip-crit           
                 	   Ecritical                cam1-thermal                                          trips      trip-alert          
 L                   Epassive       trip-crit           
                 	   Ecritical                   chosen          5serial0:921600n8          firmware       optee             linaro,optee-tz         Jsmc          memory@40000000         3memory          ?    @                regulator-wifi-3v3-en             regulator-fixed         Mwifi_3v3_en                  \ 2Z        t 2Z         A              C            _default         U           T   P      regulator-vsys            regulator-fixed         Mvsys                      _        \ LK@        t LK@        T              P      regulator-vsys-buck           regulator-fixed       
  Mvsys_buck                     _        \ LK@        t LK@        T              ^      regulator-vcc5v0-sys              regulator-fixed         Mvcc5v0_sys                    _                 reserved-memory                      +            d   optee@43200000          ?    C                   q      memory@50000000           shared-dma-pool         ?    P                  q           -      memory@53000000           shared-dma-pool         ?    S       @        memory@54600000         ?    T`                   q      memory@60000000           shared-dma-pool         ?    `                  q      memory@62000000           shared-dma-pool         ?    b       @              	compatible interrupt-parent #address-cells #size-cells model chassis-type dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 ethernet0 serial0 serial1 spi0 spi1 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit pinmux drive-strength input-enable output-high bias-disable input-disable bias-pull-up drive-strength-microamp bias-pull-down output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-0 pinctrl-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,tx-delay-ps mediatek,mac-wol snps,reset-gpio snps,reset-delays-us snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup role-switch-default-mode usb-role-switch vusb33-supply vbus-supply remote-endpoint bus-width max-frequency hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 usb2-lpm-disable mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN1-supply LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos mode-switch orientation-switch vcc-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path enable-active-high vin-supply regulator-boot-on no-map 