  E   8  `   (              (                                 nvidia,p2571 nvidia,tegra210                                     +         '   7NVIDIA Tegra210 P2571 reference design     pcie@1003000              nvidia,tegra210-pcie             =pci       0   I     0             8                               Mpads afi cs          W       b          c         	   bintr msi             r                                                                b                                        +                                                                                                           B                                           F      H          ,         pex afi pll_e cml                  F      H      J         pex afi pcie_x           default idle                                  	   disabled       pci@1,0          =pci                                  I                                         	   disabled                         +                              pci@2,0          =pci                                 I                                         	   disabled                         +                                 host1x@50000000           nvidia,tegra210-host1x           I    P        @          W       A          C            bsyncpt host1x                           host1x                             
   host1x mc                        +                T       T                  (         dpaux@54040000            nvidia,tegra210-dpaux            I    T                  W                              /         dpaux parent                            dpaux           /         	   disabled       pinmux-aux        	  =dpaux-io            Daux         M         pinmux-i2c        	  =dpaux-io            Di2c         M         pinmux-off        	  =dpaux-io            Doff         M         i2c-bus                      +             vi@54080000           nvidia,tegra210-vi           I    T                  W       E         	   disabled            U              e     4                       /                        +                    T         csi@838           nvidia,tegra210-csi          I  8         	   disabled             U                       G        e                          |eee9       (         4                       G         csi cilab cilcd cile csi_tpg            /            tsec@54100000             nvidia,tegra210-tsec             I    T                  W       2                  S         tsec                   S         tsec          	   disabled          dc@54200000           nvidia,tegra210-dc           I    T                   W       I                           dc                          dc          (                 	   
                        dc@54240000           nvidia,tegra210-dc           I    T$                  W       J                           dc                          dc          (                 	   
                       dsi@54300000              nvidia,tegra210-dsi          I    T0                        0                     dsi lp parent                  0         dsi         /                       	   disabled                         +            M   	      vic@54340000              nvidia,tegra210-vic          I    T4                  W       H                           vic                         vic         (              /         nvjpg@54380000            nvidia,tegra210-nvjpg            I    T8               	   disabled          dsi@54400000              nvidia,tegra210-dsi          I    T@                        R                     dsi lp parent                  R         dsi         /                       	   disabled                         +            M   
      nvdec@54480000            nvidia,tegra210-nvdec            I    TH               	   disabled          nvenc@544c0000            nvidia,tegra210-nvenc            I    TL               	   disabled          tsec@54500000             nvidia,tegra210-tsec             I    TP                  W       P                           tsec                            tsec          	   disabled          sor@54540000              nvidia,tegra210-sor          I    TT                  W       L         (                         /               sor out parent dp safe                          sor                                             aux i2c off         /         	   disabled            M         sor@54580000              nvidia,tegra210-sor1             I    TX                  W       K         (                         /               sor out parent dp safe                          sor                                             aux i2c off         /         	   disabled            M         dpaux@545c0000            nvidia,tegra210-dpaux            I    T\                  W                              /         dpaux parent                            dpaux           /         	   disabled       pinmux-aux        	  =dpaux-io            Daux         M         pinmux-i2c        	  =dpaux-io            Di2c         M         pinmux-off        	  =dpaux-io            Doff         M         i2c-bus                      +             isp@54600000              nvidia,tegra210-isp          I    T`                  W       G                                          isp       	   disabled          isp@54680000              nvidia,tegra210-isp          I    Th                  W       F                                          isp       	   disabled          i2c@546c0000              nvidia,tegra210-i2c-vi           I    Tl                  W                               Q         div-clk slow                            i2c         /         	   disabled                         +             interrupt-controller@50041000             arm,gic-400          r                  @   I    P            P              P@             P`                  W      	                      M         gpu@57000000              nvidia,gm20b              I    W              X                   W                             bstall nonstall                      +               gpu pwr ref                         gpu         (            	   disabled          interrupt-controller@60004000             nvidia,tegra210-ictlr         `   I    ` @        @    ` A        @    ` B        @    ` C        @    ` D        @    ` E        @                  r                       M         timer@60005000            nvidia,tegra210-timer            I    ` P                 W                                      )          *          y                                                                                                           timer         clock@60006000            nvidia,tegra210-car          I    ` `                                      M         flow-controller@60007000              nvidia,tegra210-flowctrl             I    ` p              gpio@6000d000         )    nvidia,tegra210-gpio nvidia,tegra30-gpio             I    `               `   W                  !          "          #          7          W          Y          }                                r                  dma@60020000          .    nvidia,tegra210-apbdma nvidia,tegra148-apbdma            I    `                 W       h          i          j          k          l          m          n          o          p          q          r          s          t          u          v          w                                                                                                                                                                                  "         dma                "         dma                    M         apbmisc@70000800          /    nvidia,tegra210-apbmisc nvidia,tegra20-apbmisc            I    p         d    p               pinmux@700008d4           nvidia,tegra210-pinmux            I    p           p 0                boot                   pinmux-sdmmc1-1v8-drv           M      sdmmc1          "drive_sdmmc1            .           H            pinmux-sdmmc1-3v3-drv           M      sdmmc1          "drive_sdmmc1            .           H            pinmux-sdmmc2-1v8-drv           M       sdmmc2          "drive_sdmmc2            .           H            pinmux-sdmmc3-1v8-drv           M   $   sdmmc3          "drive_sdmmc3            .           H            pinmux-sdmmc3-3v3-drv           M   #   sdmmc3          "drive_sdmmc3            .           H            pinmux-sdmmc4-1v8-drv           M   %   sdmmc4          "drive_sdmmc4            .           H            pinmux          M      pex_l0_rst_n_pa0            "pex_l0_rst_n_pa0            `           l            |                                 pex_l0_clkreq_n_pa1         "pex_l0_clkreq_n_pa1         rsvd1           `           l           |                                  pex_wake_n_pa2          "pex_wake_n_pa2          rsvd1           `           l           |                                  pex_l1_rst_n_pa3            "pex_l1_rst_n_pa3            rsvd1           `           l           |                                  pex_l1_clkreq_n_pa4         "pex_l1_clkreq_n_pa4         rsvd1           `           l           |                                  sata_led_active_pa5         "sata_led_active_pa5         `           l            |                     pa6         "pa6         rsvd1           `           l           |                      dap1_fs_pb0         "dap1_fs_pb0         rsvd1           `           l           |                      dap1_din_pb1            "dap1_din_pb1            rsvd1           `           l           |                      dap1_dout_pb2           "dap1_dout_pb2           rsvd1           `           l           |                      dap1_sclk_pb3           "dap1_sclk_pb3           rsvd1           `           l           |                      spi2_mosi_pb4           "spi2_mosi_pb4           rsvd2           `           l           |                      spi2_miso_pb5           "spi2_miso_pb5           rsvd2           `           l           |                      spi2_sck_pb6            "spi2_sck_pb6            rsvd2           `           l           |                      spi2_cs0_pb7            "spi2_cs0_pb7            rsvd2           `           l           |                      spi1_mosi_pc0           "spi1_mosi_pc0           rsvd1           `           l           |                      spi1_miso_pc1           "spi1_miso_pc1           rsvd1           `           l           |                      spi1_sck_pc2            "spi1_sck_pc2            rsvd1           `           l           |                      spi1_cs0_pc3            "spi1_cs0_pc3            rsvd1           `           l           |                      spi1_cs1_pc4            "spi1_cs1_pc4            rsvd1           `           l           |                      spi4_sck_pc5            "spi4_sck_pc5            rsvd1           `           l           |                      spi4_cs0_pc6            "spi4_cs0_pc6            rsvd1           `           l           |                      spi4_mosi_pc7           "spi4_mosi_pc7           rsvd1           `           l           |                      spi4_miso_pd0           "spi4_miso_pd0           rsvd1           `           l           |                      uart3_tx_pd1            "uart3_tx_pd1            rsvd2           `           l           |                      uart3_rx_pd2            "uart3_rx_pd2            rsvd2           `           l           |                      uart3_rts_pd3           "uart3_rts_pd3           rsvd2           `           l           |                      uart3_cts_pd4           "uart3_cts_pd4           `            l            |                     dmic1_clk_pe0           "dmic1_clk_pe0           i2s3            `            l            |                     dmic1_dat_pe1           "dmic1_dat_pe1           i2s3            `            l            |                     dmic2_clk_pe2           "dmic2_clk_pe2           i2s3            `            l            |                     dmic2_dat_pe3           "dmic2_dat_pe3           i2s3            `            l            |                     dmic3_clk_pe4           "dmic3_clk_pe4           `            l            |                      dmic3_dat_pe5           "dmic3_dat_pe5           rsvd2           `           l           |                      pe6         "pe6         rsvd0           `           l           |                      pe7         "pe7         pwm3            `            l            |                      gen3_i2c_scl_pf0            "gen3_i2c_scl_pf0            i2c3            `            l            |                                 gen3_i2c_sda_pf1            "gen3_i2c_sda_pf1            i2c3            `            l            |                                 uart2_tx_pg0            "uart2_tx_pg0            `            l            |                     uart2_rx_pg1            "uart2_rx_pg1            uartb           `           l           |                      uart2_rts_pg2           "uart2_rts_pg2           rsvd2           `           l           |                      uart2_cts_pg3           "uart2_cts_pg3           rsvd2           `           l           |                      wifi_en_ph0         "wifi_en_ph0         `            l            |                      wifi_rst_ph1            "wifi_rst_ph1            rsvd0           `           l           |                      wifi_wake_ap_ph2            "wifi_wake_ap_ph2            `           l            |                     ap_wake_bt_ph3          "ap_wake_bt_ph3          `            l            |                      bt_rst_ph4          "bt_rst_ph4          `            l            |                      bt_wake_ap_ph5          "bt_wake_ap_ph5          `           l            |                     ph6         "ph6         rsvd0           `           l           |                      ap_wake_nfc_ph7         "ap_wake_nfc_ph7         rsvd0           `           l           |                      nfc_en_pi0          "nfc_en_pi0          `            l            |                      nfc_int_pi1         "nfc_int_pi1         `            l            |                     gps_en_pi2          "gps_en_pi2          rsvd0           `           l           |                      gps_rst_pi3         "gps_rst_pi3         rsvd0           `           l           |                      uart4_tx_pi4            "uart4_tx_pi4            uartd           `            l            |                      uart4_rx_pi5            "uart4_rx_pi5            uartd           `            l            |                     uart4_rts_pi6           "uart4_rts_pi6           uartd           `            l            |                      uart4_cts_pi7           "uart4_cts_pi7           uartd           `            l            |                     gen1_i2c_sda_pj0            "gen1_i2c_sda_pj0            i2c1            `            l            |                                 gen1_i2c_scl_pj1            "gen1_i2c_scl_pj1            i2c1            `            l            |                                 gen2_i2c_scl_pj2            "gen2_i2c_scl_pj2            i2c2            `            l            |                                gen2_i2c_sda_pj3            "gen2_i2c_sda_pj3            i2c2            `            l            |                                dap4_fs_pj4         "dap4_fs_pj4         rsvd1           `           l           |                      dap4_din_pj5            "dap4_din_pj5            rsvd1           `           l           |                      dap4_dout_pj6           "dap4_dout_pj6           rsvd1           `           l           |                      dap4_sclk_pj7           "dap4_sclk_pj7           rsvd1           `           l           |                      pk0         "pk0         rsvd2           `           l           |                      pk1         "pk1         rsvd2           `           l           |                      pk2         "pk2         rsvd2           `           l           |                      pk3         "pk3         rsvd2           `           l           |                      pk4         "pk4         rsvd1           `           l           |                      pk5         "pk5         rsvd1           `           l           |                      pk6         "pk6         rsvd1           `           l           |                      pk7         "pk7         rsvd1           `           l           |                      pl0         "pl0         rsvd0           `           l           |                      pl1         "pl1         rsvd1           `           l           |                      sdmmc1_clk_pm0          "sdmmc1_clk_pm0          sdmmc1          `            l            |                     sdmmc1_cmd_pm1          "sdmmc1_cmd_pm1          sdmmc1          `           l            |                     sdmmc1_dat3_pm2         "sdmmc1_dat3_pm2         sdmmc1          `           l            |                     sdmmc1_dat2_pm3         "sdmmc1_dat2_pm3         sdmmc1          `           l            |                     sdmmc1_dat1_pm4         "sdmmc1_dat1_pm4         sdmmc1          `           l            |                     sdmmc1_dat0_pm5         "sdmmc1_dat0_pm5         sdmmc1          `           l            |                     sdmmc3_clk_pp0          "sdmmc3_clk_pp0          sdmmc3          `            l            |                     sdmmc3_cmd_pp1          "sdmmc3_cmd_pp1          sdmmc3          `           l            |                     sdmmc3_dat3_pp2         "sdmmc3_dat3_pp2         sdmmc3          `           l            |                     sdmmc3_dat2_pp3         "sdmmc3_dat2_pp3         sdmmc3          `           l            |                     sdmmc3_dat1_pp4         "sdmmc3_dat1_pp4         sdmmc3          `           l            |                     sdmmc3_dat0_pp5         "sdmmc3_dat0_pp5         sdmmc3          `           l            |                     cam1_mclk_ps0           "cam1_mclk_ps0           rsvd1           `           l           |                      cam2_mclk_ps1           "cam2_mclk_ps1           rsvd1           `           l           |                      cam_i2c_scl_ps2         "cam_i2c_scl_ps2         i2cvi           `            l            |                                 cam_i2c_sda_ps3         "cam_i2c_sda_ps3         i2cvi           `            l            |                                 cam_rst_ps4         "cam_rst_ps4         rsvd1           `           l           |                      cam_af_en_ps5           "cam_af_en_ps5           rsvd2           `           l           |                      cam_flash_en_ps6            "cam_flash_en_ps6            rsvd2           `           l           |                      cam1_pwdn_ps7           "cam1_pwdn_ps7           rsvd1           `           l           |                      cam2_pwdn_pt0           "cam2_pwdn_pt0           rsvd1           `           l           |                      cam1_strobe_pt1         "cam1_strobe_pt1         rsvd1           `           l           |                      uart1_tx_pu0            "uart1_tx_pu0            uarta           `            l            |                      uart1_rx_pu1            "uart1_rx_pu1            uarta           `           l            |                     uart1_rts_pu2           "uart1_rts_pu2           uarta           `            l            |                      uart1_cts_pu3           "uart1_cts_pu3           uarta           `           l            |                     lcd_bl_pwm_pv0          "lcd_bl_pwm_pv0          pwm0            `            l            |                      lcd_bl_en_pv1           "lcd_bl_en_pv1           `            l            |                      lcd_rst_pv2         "lcd_rst_pv2         rsvd0           `           l           |                      lcd_gpio1_pv3           "lcd_gpio1_pv3           rsvd1           `           l           |                      lcd_gpio2_pv4           "lcd_gpio2_pv4           pwm1            `            l            |                      ap_ready_pv5            "ap_ready_pv5            rsvd0           `           l           |                      touch_rst_pv6           "touch_rst_pv6           `            l            |                      touch_clk_pv7           "touch_clk_pv7           rsvd1           `           l           |                      modem_wake_ap_px0           "modem_wake_ap_px0           rsvd0           `           l           |                      touch_int_px1           "touch_int_px1           rsvd0           `           l           |                      motion_int_px2          "motion_int_px2          rsvd0           `           l           |                      als_prox_int_px3            "als_prox_int_px3            rsvd0           `           l           |                      temp_alert_px4          "temp_alert_px4          `           l            |                     button_power_on_px5         "button_power_on_px5         rsvd0           `           l           |                      button_vol_up_px6           "button_vol_up_px6           `           l            |                     button_vol_down_px7         "button_vol_down_px7         `           l            |                     button_slide_sw_py0         "button_slide_sw_py0         rsvd0           `           l           |                      button_home_py1         "button_home_py1         `           l            |                     lcd_te_py2          "lcd_te_py2          rsvd1           `           l           |                      pwr_i2c_scl_py3         "pwr_i2c_scl_py3         i2cpmu          `            l            |                                 pwr_i2c_sda_py4         "pwr_i2c_sda_py4         i2cpmu          `            l            |                                 clk_32k_out_py5         "clk_32k_out_py5         soc         `           l            |                     pz0         "pz0         `           l            |                     pz1         "pz1         sdmmc1          `           l            |                     pz2         "pz2         rsvd2           `           l           |                      pz3         "pz3         rsvd1           `           l           |                      pz4         "pz4         `            l            |                      pz5         "pz5         soc         `           l            |                     dap2_fs_paa0            "dap2_fs_paa0            i2s2            `            l            |                     dap2_sclk_paa1          "dap2_sclk_paa1          i2s2            `            l            |                     dap2_din_paa2           "dap2_din_paa2           i2s2            `            l            |                     dap2_dout_paa3          "dap2_dout_paa3          i2s2            `            l            |                     aud_mclk_pbb0           "aud_mclk_pbb0           aud         `            l            |                      dvfs_pwm_pbb1           "dvfs_pwm_pbb1           cldvfs          `            l           |                      dvfs_clk_pbb2           "dvfs_clk_pbb2           `            l            |                      gpio_x1_aud_pbb3            "gpio_x1_aud_pbb3            rsvd0           `           l           |                      gpio_x3_aud_pbb4            "gpio_x3_aud_pbb4            rsvd0           `           l           |                      hdmi_cec_pcc0           "hdmi_cec_pcc0           cec         `            l            |                                hdmi_int_dp_hpd_pcc1            "hdmi_int_dp_hpd_pcc1            `           l            |                                 spdif_out_pcc2          "spdif_out_pcc2          rsvd1           `           l           |                      spdif_in_pcc3           "spdif_in_pcc3           `            l            |                     usb_vbus_en0_pcc4           "usb_vbus_en0_pcc4           usb         `            l            |                                usb_vbus_en1_pcc5           "usb_vbus_en1_pcc5           usb         `            l            |                                dp_hpd0_pcc6            "dp_hpd0_pcc6            rsvd1           `           l           |                      pcc7            "pcc7            rsvd0           `           l           |                                  spi2_cs1_pdd0           "spi2_cs1_pdd0           rsvd1           `           l           |                      qspi_sck_pee0           "qspi_sck_pee0           rsvd1           `           l           |                      qspi_cs_n_pee1          "qspi_cs_n_pee1          rsvd1           `           l           |                      qspi_io0_pee2           "qspi_io0_pee2           rsvd1           `           l           |                      qspi_io1_pee3           "qspi_io1_pee3           rsvd1           `           l           |                      qspi_io2_pee4           "qspi_io2_pee4           rsvd1           `           l           |                      qspi_io3_pee5           "qspi_io3_pee5           rsvd1           `           l           |                      core_pwr_req            "core_pwr_req            core            `            l            |                      cpu_pwr_req         "cpu_pwr_req         cpu         `            l            |                      pwr_int_n         
  "pwr_int_n           pmi         `           l            |                     clk_32k_in          "clk_32k_in          clk         `            l            |                     jtag_rtck         
  "jtag_rtck           jtag            `            l            |                      clk_req         "clk_req         sys         `            l            |                      shutdown          	  "shutdown          	  shutdown            `            l            |                            serial@70006000       )    nvidia,tegra210-uart nvidia,tegra20-uart             I    p `        @                    W       $                                          okay          serial@70006040       )    nvidia,tegra210-uart nvidia,tegra20-uart             I    p `@       @                    W       %                                               	      	        rx tx         	   disabled          serial@70006200       )    nvidia,tegra210-uart nvidia,tegra20-uart             I    p b        @                    W       .                  7               7              
      
        rx tx         	   disabled          serial@70006300       )    nvidia,tegra210-uart nvidia,tegra20-uart             I    p c        @                    W       Z                  A               A                            rx tx         	   disabled          pwm@7000a000          '    nvidia,tegra210-pwm nvidia,tegra20-pwm           I    p                                                           pwm       	   disabled          i2c@7000c000          (    nvidia,tegra210-i2c nvidia,tegra124-i2c          I    p                  W       &                        +                            div-clk                         i2c                             rx tx         	   disabled          i2c@7000c400          (    nvidia,tegra210-i2c nvidia,tegra124-i2c          I    p                  W       T                        +                   6         div-clk                6         i2c                             rx tx         	   disabled          i2c@7000c500          (    nvidia,tegra210-i2c nvidia,tegra124-i2c          I    p                  W       \                        +                   C         div-clk                C         i2c                             rx tx         	   disabled          i2c@7000c700          (    nvidia,tegra210-i2c nvidia,tegra124-i2c          I    p                  W       x                        +                   g         div-clk                g         i2c                             rx tx                                    default idle          	   disabled          i2c@7000d000          (    nvidia,tegra210-i2c nvidia,tegra124-i2c          I    p                  W       5                        +                   /         div-clk                /         i2c                             rx tx            okay                   i2c@7000d100          (    nvidia,tegra210-i2c nvidia,tegra124-i2c          I    p                  W       ?                        +                            div-clk                         i2c                             rx tx                                    default idle          	   disabled          spi@7000d400          (    nvidia,tegra210-spi nvidia,tegra114-spi          I    p                  W       ;                        +                   )         spi                )         spi                             rx tx         	   disabled          spi@7000d600          (    nvidia,tegra210-spi nvidia,tegra114-spi          I    p                  W       R                        +                   ,         spi                ,         spi                             rx tx         	   disabled          spi@7000d800          (    nvidia,tegra210-spi nvidia,tegra114-spi          I    p                  W       S                        +                   .         spi                .         spi                             rx tx         	   disabled          spi@7000da00          (    nvidia,tegra210-spi nvidia,tegra114-spi          I    p                  W       ]                        +                   D         spi                D         spi                             rx tx         	   disabled          rtc@7000e000          '    nvidia,tegra210-rtc nvidia,tegra20-rtc           I    p                  W                                          rtc       pmc@7000e400              nvidia,tegra210-pmc          I    p                       %            pclk clk32k_in                      r                             M      pinmux     pex-dpd-disable         )pex-bias pex-clk1 pex-clk2                   M         pex-dpd-enable          )pex-bias pex-clk1 pex-clk2                   M         sdmmc1-1v8          )sdmmc1          .            M         sdmmc1-3v3          )sdmmc1          .           M         sdmmc3-1v8          )sdmmc3          .            M   "      sdmmc3-3v3          )sdmmc3          .           M   !         powergates     aud                      k                       ;            M   '      sor       P                                       0      R                  8      8                     0      R                  8        ;            M         venc                         4                           4        ;            M         vic                                       ;            M         xusba                                         ;            M         xusbb                 !               _        ;            M   &      xusbc                  Y               Y        ;            M               fuse@7000f800             nvidia,tegra210-efuse            I    p                                 fuse                   '         fuse          memory-controller@70019000            nvidia,tegra210-mc           I    p                                 mc           W       M           O                      M         external-memory-controller@7001b000           nvidia,tegra210-emc       0   I    p            p            p                       9         emc          W       N           \           u           M   J      sata@70020000             nvidia,tegra210-ahci          0   I    pp             p        p     p                  W                         |      {         sata sata-oob                  |            {         sata sata-cold sata-oob       	   disabled          hda@70030000          '    nvidia,tegra210-hda nvidia,tegra30-hda           I    p                  W       Q                  }            o         hda hda2hdmi hda2codec_2x                  }            o         hda hda2hdmi hda2codec_2x           /         	   disabled          usb@70090000              nvidia,tegra210-xusb          0   I    p	             p	            p	                 Mhcd fpci ipfs            W       '          (         X         Y                     j          "                            x   xusb_host xusb_host_src xusb_falcon_src xusb_ss xusb_ss_div2 xusb_ss_src xusb_hs_src xusb_fs_src pll_u_480m clk_m pll_e                Y                     xusb_host xusb_ss xusb_src          /              xusb_host xusb_ss                    	   disabled          padctl@7009f000           nvidia,tegra210-xusb-padctl          I    p	                 W       1                           padctl                   	   disabled            M      pads       usb2                            trk       	   disabled       lanes      usb2-0        	   disabled                      usb2-1        	   disabled                      usb2-2        	   disabled                      usb2-3        	   disabled                            hsic                            trk       	   disabled       lanes      hsic-0        	   disabled                      hsic-1        	   disabled                            pcie                           pll                         phy       	   disabled       lanes      pcie-0        	   disabled                      pcie-1        	   disabled                      pcie-2        	   disabled                      pcie-3        	   disabled                      pcie-4        	   disabled                      pcie-5        	   disabled                      pcie-6        	   disabled                            sata                           pll                         phy       	   disabled       lanes      sata-0        	   disabled                               ports      usb2-0        	   disabled          usb2-1        	   disabled          usb2-2        	   disabled          usb2-3        	   disabled          hsic-0        	   disabled          usb3-0        	   disabled          usb3-1        	   disabled          usb3-2        	   disabled          usb3-3        	   disabled                mmc@700b0000              nvidia,tegra210-sdhci            I    p                  W                                        sdhci tmclk                         sdhci         0   sdmmc-3v3 sdmmc-1v8 sdmmc-3v3-drv sdmmc-1v8-drv                                                                      }           {        >   {        f           y           U           4     .        e     4        | ; ;       	   disabled          mmc@700b0200              nvidia,tegra210-sdhci            I    p                 W                         	               sdhci tmclk                	         sdhci            sdmmc-1v8-drv                                   >           f           y          	   disabled          mmc@700b0400              nvidia,tegra210-sdhci            I    p                 W                         E               sdhci tmclk                E         sdhci         0   sdmmc-3v3 sdmmc-1v8 sdmmc-3v3-drv sdmmc-1v8-drv             !            "           #           $                       }           {        >   {        f           y         	   disabled          mmc@700b0600              nvidia,tegra210-sdhci            I    p                 W                                        sdhci tmclk                         sdhci            sdmmc-3v3-drv sdmmc-1v8-drv             %            %                   >           f           y            U           4        e     4           (                  okay                              usb@700d0000              nvidia,tegra210-xudc          0   I    p             p            p                 Mbase fpci ipfs           W       ,         (        !           >          "         dev ss ss_src fs_src hs_src         /   &           dev ss                   	   disabled          thermal-sensor@700e2000           nvidia,tegra210-soctherm              I    p             ` `                 Msoctherm-reg car-reg             W       0          3            bthermal edp                d      N         tsensor soctherm                   N      	   soctherm                       M   G   throttle-cfgs      heavy              d           U                   u           M   I            mipi@700e3000             nvidia,tegra210-mipi             I    p0                       8      	   mipi-cal            /                      M         clock@70110000            nvidia,tegra210-dfll          @   I    p             p             p            p                 W       >                 )     (      /         soc ref i2c                            
   dvco dfll                       7dfllCPU_out       	   disabled            M   @      aconnect@702c0000             nvidia,tegra210-aconnect                         k         ape apb2ape         /   '                     +            p,      p,           	   disabled       ahub@702d0800             nvidia,tegra210-ahub             Ip-                   j         ahub            U      j        e              |                      +            p-  p-           	   disabled       admaif@702d0000           nvidia,tegra210-admaif           Ip-                (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (   	   (   	   (   
   (   
      R  rx1 tx1 rx2 tx2 rx3 tx3 rx4 tx4 rx5 tx5 rx6 tx6 rx7 tx7 rx8 tx8 rx9 tx9 rx10 tx10         	   disabled       ports                        +       port@0           I       endpoint            J   )        M   3         port@1           I      endpoint            J   *        M   4         port@2           I      endpoint            J   +        M   5         port@3           I      endpoint            J   ,        M   6         port@4           I      endpoint            J   -        M   7         port@5           I      endpoint            J   .        M   8         port@6           I      endpoint            J   /        M   9         port@7           I      endpoint            J   0        M   :         port@8           I      endpoint            J   1        M   ;         port@9           I   	   endpoint            J   2        M   <               i2s@702d1000              nvidia,tegra210-i2s          Ip-                        	         i2s sync_input          U              e              | p         ZI2S1          	   disabled          i2s@702d1100              nvidia,tegra210-i2s          Ip-                        
         i2s sync_input          U              e              | p         ZI2S2          	   disabled          i2s@702d1200              nvidia,tegra210-i2s          Ip-                                 i2s sync_input          U              e              | p         ZI2S3          	   disabled          i2s@702d1300              nvidia,tegra210-i2s          Ip-                   e              i2s sync_input          U      e        e              | p         ZI2S4          	   disabled          i2s@702d1400              nvidia,tegra210-i2s          Ip-                   f              i2s sync_input          U      f        e              | p         ZI2S5          	   disabled          sfc@702d2000              nvidia,tegra210-sfc          Ip-             ZSFC1          	   disabled          sfc@702d2200              nvidia,tegra210-sfc          Ip-"            ZSFC2          	   disabled          sfc@702d2400              nvidia,tegra210-sfc          Ip-$            ZSFC3          	   disabled          sfc@702d2600              nvidia,tegra210-sfc          Ip-&            ZSFC4          	   disabled          amx@702d3000              nvidia,tegra210-amx          Ip-0            ZAMX1          	   disabled          amx@702d3100              nvidia,tegra210-amx          Ip-1            ZAMX2          	   disabled          adx@702d3800              nvidia,tegra210-adx          Ip-8            ZADX1          	   disabled          adx@702d3900              nvidia,tegra210-adx          Ip-9            ZADX2          	   disabled          dmic@702d4000             nvidia,tegra210-dmic             Ip-@                            dmic            U              e              | .         ZDMIC1         	   disabled          dmic@702d4100             nvidia,tegra210-dmic             Ip-A                            dmic            U              e              | .         ZDMIC2         	   disabled          dmic@702d4200             nvidia,tegra210-dmic             Ip-B                            dmic            U              e              | .         ZDMIC3         	   disabled          processing-engine@702d8000            nvidia,tegra210-ope          Ip-                         +                     ZOPE1          	   disabled       equalizer@702d8100            nvidia,tegra210-peq          Ip-          dynamic-range-compressor@702d8200             nvidia,tegra210-mbdrc            Ip-             processing-engine@702d8400            nvidia,tegra210-ope          Ip-                         +                     ZOPE2          	   disabled       equalizer@702d8500            nvidia,tegra210-peq          Ip-          dynamic-range-compressor@702d8600             nvidia,tegra210-mbdrc            Ip-             mvc@702da000              nvidia,tegra210-mvc          Ip-            ZMVC1          	   disabled          mvc@702da200              nvidia,tegra210-mvc          Ip-            ZMVC2          	   disabled          amixer@702dbb00           nvidia,tegra210-amixer           Ip-            ZMIXER1        	   disabled          ports                        +       port@0           I       endpoint            J   3        M   )         port@1           I      endpoint            J   4        M   *         port@2           I      endpoint            J   5        M   +         port@3           I      endpoint            J   6        M   ,         port@4           I      endpoint            J   7        M   -         port@5           I      endpoint            J   8        M   .         port@6           I      endpoint            J   9        M   /         port@7           I      endpoint            J   :        M   0         port@8           I      endpoint            J   ;        M   1         port@9           I   	   endpoint            J   <        M   2               dma-controller@702e2000           nvidia,tegra210-adma             Ip.                  =        W                                                                                                  !          "          #          $          %          &          '          (          )          *          +          ,          -                             j         d_audio       	   disabled            M   (      interrupt-controller@702f9000             nvidia,tegra210-agic             r                     Ip/    p/              W       f                          clk       	   disabled            M   =         spi@70410000              nvidia,tegra210-qspi             I    pA                  W       
                        +                                 qspi qspi_out                                              rx tx         	   disabled          usb@7d000000          )    nvidia,tegra210-ehci nvidia,tegra30-ehci             I    }         @          W                  lutmi                            usb                         usb         u   >      	   disabled          usb-phy@7d000000          /    nvidia,tegra210-usb-phy nvidia,tegra30-usb-phy            I    }         @     }         @         lutmi                                        reg pll_u utmi-pads                               usb utmi-pads                                                           	                                          -           C            V      	   disabled            M   >      usb@7d004000          )    nvidia,tegra210-ehci nvidia,tegra30-ehci             I    } @       @          W                  lutmi                   :         usb                :         usb         u   ?      	   disabled          usb-phy@7d004000          /    nvidia,tegra210-usb-phy nvidia,tegra30-usb-phy            I    } @       @     }         @         lutmi                   :                     reg pll_u utmi-pads                :               usb utmi-pads                                                           	                                          -           C         	   disabled            M   ?      cpus                         +       cpu@0            =cpu           arm,cortex-a57           I                  &              @         cpu_g pll_x pll_p dfll          t            A           B        psci            M   C      cpu@1            =cpu           arm,cortex-a57           I              A           B        psci            M   D      cpu@2            =cpu           arm,cortex-a57           I              A           B        psci            M   E      cpu@3            =cpu           arm,cortex-a57           I              A           B        psci            M   F      idle-states         psci       cpu-sleep             arm,idle-state          @             d                                      
  cpu-sleep         	   disabled            M   A         l2-cache              cache           )            5        M   B         pmu           arm,cortex-a57-pmu        0   W                                                C   C   D   E   F      sound         	   disabled                                  pll_a plla_out0         U                  x        e                      |            thermal-zones      cpu-thermal         V          l            z   G       trips      cpu-shutdown-trip            d                  	   Dcritical          throttle-trip                               Dhot         M   H         cooling-maps       map0               H           I                  mem-thermal         V            l            z   G      trips      mem-nominal-trip              P                   Dpassive         M   K      mem-throttle-trip            p                   Dactive          M   L      mem-hot-trip                                Dhot       mem-shutdown-trip            X                  	   Dcritical             cooling-maps       dram-passive               J                   K      dram-active            J                 L            gpu-thermal         V          l            z   G      trips      gpu-shutdown-trip            X                  	   Dcritical          throttle-trip                               Dhot         M   M         cooling-maps       map0               M           I                  pllx-thermal            V            l            z   G      trips      pllx-shutdown-trip           X                  	   Dcritical          pllx-throttle-trip                              Dhot          cooling-maps                timer             arm,armv8-timer       0   W                              
                             aliases         /rtc@7000e000           /serial@70006000          chosen          serial0:115200n8          memory@80000000          =memory           I                    clock-32k             fixed-clock                                M         psci              arm,psci-0.2            smc          	compatible interrupt-parent #address-cells #size-cells model device_type reg reg-names interrupts interrupt-names #interrupt-cells interrupt-map-mask interrupt-map bus-range ranges clocks clock-names resets reset-names pinctrl-names pinctrl-0 pinctrl-1 status assigned-addresses nvidia,num-lanes iommus power-domains groups function phandle assigned-clocks assigned-clock-parents assigned-clock-rates nvidia,outputs nvidia,head nvidia,mipi-calibrate pinctrl-2 interrupt-controller #clock-cells #reset-cells #gpio-cells gpio-controller #dma-cells nvidia,pins nvidia,pull-down-strength nvidia,pull-up-strength nvidia,pull nvidia,tristate nvidia,enable-input nvidia,open-drain nvidia,io-hv nvidia,function reg-shift dmas dma-names #pwm-cells clock-frequency nvidia,invert-interrupt low-power-disable low-power-enable power-source #power-domain-cells #iommu-cells nvidia,memory-controller #cooling-cells power-domain-names nvidia,xusb-padctl nvidia,pmc #phy-cells pinctrl-3 nvidia,pad-autocal-pull-up-offset-3v3 nvidia,pad-autocal-pull-down-offset-3v3 nvidia,pad-autocal-pull-up-offset-1v8 nvidia,pad-autocal-pull-down-offset-1v8 nvidia,default-tap nvidia,default-trim nvidia,dqs-trim mmc-hs400-1_8v bus-width non-removable #thermal-sensor-cells nvidia,priority nvidia,cpu-throt-percent nvidia,gpu-throt-level #nvidia,mipi-calibrate-cells clock-output-names remote-endpoint sound-name-prefix phy_type nvidia,phy nvidia,hssync-start-delay nvidia,idle-wait-delay nvidia,elastic-limit nvidia,term-range-adj nvidia,xcvr-setup nvidia,xcvr-lsfslew nvidia,xcvr-lsrslew nvidia,hssquelch-level nvidia,hsdiscon-level nvidia,xcvr-hsslew nvidia,has-utmi-pad-registers clock-latency cpu-idle-states next-level-cache enable-method entry-method arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us wakeup-latency-us idle-state-name cache-level cache-unified interrupt-affinity polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device arm,no-tick-in-suspend rtc1 serial0 stdout-path 