 D   8 d   (            )@ ,                                                      :   ti,am572x-beagle-x15 ti,am5728 ti,dra742 ti,dra74 ti,dra7            &            7TI AM5728 BeagleBoard-X15      chosen        B   =/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0         aliases       ?   I/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0        ?   N/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0        ?   S/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0        ?   X/ocp/interconnect@48000000/segment@0/target-module@7a000/i2c@0        ?   ]/ocp/interconnect@48000000/segment@0/target-module@7c000/i2c@0        B   b/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0         B   j/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0         B   r/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0         B   z/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0         B   /ocp/interconnect@48000000/segment@0/target-module@66000/serial@0         B   /ocp/interconnect@48000000/segment@0/target-module@68000/serial@0         B   /ocp/interconnect@48400000/segment@0/target-module@20000/serial@0         B   /ocp/interconnect@48400000/segment@0/target-module@22000/serial@0         B   /ocp/interconnect@48400000/segment@0/target-module@24000/serial@0         E   /ocp/interconnect@4ae00000/segment@20000/target-module@b000/serial@0          X   /ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@1       X   /ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@2       B   /ocp/interconnect@4ae00000/segment@30000/target-module@c000/can@0         ?   /ocp/interconnect@48400000/segment@0/target-module@80000/can@0        "   /ocp/target-module@4b300000/spi@0            /ocp/ipu@58820000            /ocp/ipu@55020000            /ocp/dsp@40800000            /ocp/dsp@41000000         F   /ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0/rtc@6f         Z   /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_rtc         ?   /ocp/interconnect@48800000/segment@0/target-module@38000/rtc@0          /connector        timer            arm,armv7-timer       	  disabled          0                                
           &         interrupt-controller@48211000            arm,cortex-a15-gic                   4         @  E    H!            H!              H!@             H!`                       	           &           I         interrupt-controller@48281000         &   ti,omap5-wugen-mpu ti,omap4-wugen-mpu                    4           E    H(                 &           I         cpus                                 cpu@0           Qcpu          arm,cortex-a15          E            ]           q           xcpu                                                              I         cpu@1           Qcpu          arm,cortex-a15          E           ]           q           xcpu                                         opp-table            operating-points-v2-ti-cpu                              I      opp-1000000000              ;          , P 0 , P 0                             opp-1176000000              FV          @  @ @  @                    opp-1500000000              Yh/          v ~  v ~                        ocp          simple-pm-bus                      q   	           
                                                                "                     I  
   l3-noc@44000000          ti,dra7-l3-noc          ED      E               -                       
         interconnect@4a000000            ti,dra7-l4-cfg simple-pm-bus                       q                   xfck         EJ      J     J           
  Aap la ia0                                  $      J         J         J               "        I     segment@0            simple-pm-bus                                 \                                             @   @      P   P      `   `                        `  `     p  p                                      
   
      
  
                                                 @  @     P  P     `  `     p  p     	   	      	  	       target-module@2000           ti,sysc-omap4 ti,sysc           E               Arev                                                 scm@0            ti,dra7-scm-core simple-bus         E                                                             I     scm_conf@0           syscon simple-bus           E                                                           I      pbias_regulator@e00          ti,pbias-dra7 ti,pbias-omap         E                         I     pbias_mmc_omap5         Kpbias_mmc_omap5         Z w@        r 2Z        I            phy-gmii-sel@554             ti,dra7xx-phy-gmii-sel          E  T                      I         clocks                                    I     clock-dss-deshdcp-0@558                      ti,gate-clock           dss_deshdcp_clk         q                       E  X        I        clock-ehrpwm0-tbclk-20@558                       ti,gate-clock           ehrpwm0_tbclk           q                      E  X        I         clock-ehrpwm1-tbclk-21@558                       ti,gate-clock           ehrpwm1_tbclk           q                      E  X        I         clock-ehrpwm2-tbclk-22@558                       ti,gate-clock           ehrpwm2_tbclk           q                      E  X        I         clock-sys-32k@6c4                        ti,mux-clock            sys_32k_ck          q                               E          I   U            pinmux@1400          ti,dra7-padconf pinctrl-single          E     h                                             4                                ?        I      mmc1-default-pins         0    T     X     \     `     d     h           I         mmc1-sdr12-pins       0    T     X     \     `     d     h           I        mmc1-hs-pins          0    T   X   \   `   d   h         I         mmc1-sdr25-pins       0    T   X   \   `   d   h         I        mmc1-sdr50-pins       0    T   X   \   `   d   h         I        mmc1-ddr50-pins       0    T    X    \    `    d    h          I        mmc1-sdr104-pins          0    T    X    \    `    d    h          I        mmc2-default-pins         P                                                            I         mmc2-hs-pins          P                                                            I         mmc2-ddr-3-3v-rev11-pins          P                                                  I         mmc2-ddr-1-8v-rev11-pins          P                                                  I        mmc2-ddr-rev20-pins       P                                                            I        mmc2-hs200-pins       P                                                  I        mmc4-default-pins         0                            I        mmc4-hs-pins          0                            I        mmc3-default-pins         0    |                              I        mmc3-hs-pins          0    |                              I        mmc3-sdr12-pins       0    |                              I        mmc3-sdr25-pins       0    |                              I        mmc3-sdr50-pins       0    |                              I        mmc4-sdr12-pins       0                            I        mmc4-sdr25-pins       0                            I            scm_conf@1c04            syscon          E                          I         scm_conf@1c24            syscon          E  $   $        I   d      dma-router@b78           ti,dra7-dma-crossbar            E  x           .           9           F            V           I         dma-router@c78           ti,dra7-dma-crossbar            E  x   |        .           9           F            V           I               target-module@5000           ti,sysc-omap4 ti,sysc           E  P            Arev                                        P       cm_core_aon@0            ti,dra7-cm-core-aon simple-bus                                   E                                    I  !   clocks                                    I  "   clock-atl-clkin0                         ti,dra7-atl-clock           atl_clkin0_ck           q                  I         clock-atl-clkin1                         ti,dra7-atl-clock           atl_clkin1_ck           q                  I         clock-atl-clkin2                         ti,dra7-atl-clock           atl_clkin2_ck           q                  I         clock-atl-clkin3                         ti,dra7-atl-clock           atl_clkin3_ck           q                  I         clock-hdmi-clkin                         fixed-clock         hdmi_clkin_ck           b            I   5      clock-mlb-clkin                      fixed-clock         mlb_clkin_ck            b            I         clock-mlbp-clkin                         fixed-clock         mlbp_clkin_ck           b            I         clock-pciesref-acs                       fixed-clock         pciesref_acs_clk_ck         b         I   E      clock-ref-clkin0                         fixed-clock         ref_clkin0_ck           b            I  #      clock-ref-clkin1                         fixed-clock         ref_clkin1_ck           b            I  $      clock-ref-clkin2                         fixed-clock         ref_clkin2_ck           b            I  %      clock-ref-clkin3                         fixed-clock         ref_clkin3_ck           b            I  &      clock-rmii                       fixed-clock         rmii_clk_ck         b            I  '      clock-sdvenc-clkin                       fixed-clock         sdvenc_clkin_ck         b            I  (      clock-secure-32k-clk-src                         fixed-clock         secure_32k_clk_src_ck           b           I   ~      clock-sys-clk32-crystal                      fixed-clock         sys_clk32_crystal_ck            b           I         clock-sys-clk32-pseudo                       fixed-factor-clock          sys_clk32_pseudo_ck         q           r           }  b        I         clock-virt-12000000                      fixed-clock         virt_12000000_ck            b          I   l      clock-virt-13000000                      fixed-clock         virt_13000000_ck            b ]@        I  )      clock-virt-16800000                      fixed-clock         virt_16800000_ck            b Y         I   n      clock-virt-19200000                      fixed-clock         virt_19200000_ck            b$         I   o      clock-virt-20000000                      fixed-clock         virt_20000000_ck            b1-         I   m      clock-virt-26000000                      fixed-clock         virt_26000000_ck            b        I   p      clock-virt-27000000                      fixed-clock         virt_27000000_ck            b        I   q      clock-virt-38400000                      fixed-clock         virt_38400000_ck            bI         I   r      clock-sys-clkin2                         fixed-clock         sys_clkin2          bX         I   s      clock-usb-otg-clkin                      fixed-clock         usb_otg_clkin_ck            b            I   {      clock-video1-clkin                       fixed-clock         video1_clkin_ck         b            I   ?      clock-video1-m2-clkin                        fixed-clock         video1_m2_clkin_ck          b            I   4      clock-video2-clkin                       fixed-clock         video2_clkin_ck         b            I   @      clock-video2-m2-clkin                        fixed-clock         video2_m2_clkin_ck          b            I   3      clock@1e0                        ti,omap4-dpll-m4xen-clock           dpll_abe_ck         q              E                I         clock-dpll-abe-x2                        ti,omap4-dpll-x2-clock          dpll_abe_x2_ck          q           I         clock-dpll-abe-m2x2-8@1f0                        ti,divider-clock            dpll_abe_m2x2_ck            q                                 E                            I         clock-abe@108                        ti,divider-clock            abe_clk         q                      E                   I   u      clock-dpll-abe-m2-8@1f0                      ti,divider-clock            dpll_abe_m2_ck          q                                 E                            I   w      clock-dpll-abe-m3x2-8@1f4                        ti,divider-clock            dpll_abe_m3x2_ck            q                                 E                            I         clock@12c         
   ti,clksel           E  ,                                        clock@23            E            ti,mux-clock            dpll_core_byp_mux           q                          I            clock@120                        ti,omap4-dpll-core-clock            dpll_core_ck            q              E     $  ,  (        I         clock-dpll-core-x2                       ti,omap4-dpll-x2-clock          dpll_core_x2_ck         q           I         clock-dpll-core-h12x2-8@13c                      ti,divider-clock            dpll_core_h12x2_ck          q              ?                   E  <                          I          clock-mpu-dpll-hs-clk-div                        fixed-factor-clock          mpu_dpll_hs_clk_div         q            r           }           I   !      clock@160                        ti,omap5-mpu-dpll-clock         dpll_mpu_ck         q      !        E  `  d  l  h        I         clock-dpll-mpu-m2-8@170                      ti,divider-clock            dpll_mpu_m2_ck          q                                 E  p                          I   "      clock-mpu-dclk-div                       fixed-factor-clock          mpu_dclk_div            q   "        r           }           I         clock-dsp-dpll-hs-clk-div                        fixed-factor-clock          dsp_dpll_hs_clk_div         q            r           }           I   #      clock@240         
   ti,clksel           E  @                                        clock@23            E            ti,mux-clock            dpll_dsp_byp_mux            q      #                    I   $         clock@234                        ti,omap4-dpll-clock         dpll_dsp_ck         q      $        E  4  8  @  <           %        #F         I   %      clock-dpll-dsp-m2-8@244                      ti,divider-clock            dpll_dsp_m2_ck          q   %                              E  D                             &        #F         I   &      clock-iva-dpll-hs-clk-div                        fixed-factor-clock          iva_dpll_hs_clk_div         q            r           }           I   '      clock@1ac         
   ti,clksel           E                                          clock@23            E            ti,mux-clock            dpll_iva_byp_mux            q      '                    I   (         clock@1a0                        ti,omap4-dpll-clock         dpll_iva_ck         q      (        E                   )        Ep}@        I   )      clock-dpll-iva-m2-8@1b0                      ti,divider-clock            dpll_iva_m2_ck          q   )                              E                               *        %        I   *      clock-iva-dclk                       fixed-factor-clock        	  iva_dclk            q   *        r           }           I         clock@2e4         
   ti,clksel           E                                          clock@23            E            ti,mux-clock            dpll_gpu_byp_mux            q                          I   +         clock@2d8                        ti,omap4-dpll-clock         dpll_gpu_ck         q      +        E                   ,        Ly@        I   ,      clock-dpll-gpu-m2-8@2e8                      ti,divider-clock            dpll_gpu_m2_ck          q   ,                              E                               -        _(k        I   -      clock-dpll-core-m2-8@130                         ti,divider-clock            dpll_core_m2_ck         q                                 E  0                          I   .      clock-core-dpll-out-dclk-div                         fixed-factor-clock          core_dpll_out_dclk_div          q   .        r           }           I         clock@21c         
   ti,clksel           E                                          clock@23            E            ti,mux-clock            dpll_ddr_byp_mux            q                          I   /         clock@210                        ti,omap4-dpll-clock         dpll_ddr_ck         q      /        E                I   0      clock-dpll-ddr-m2-8@220                      ti,divider-clock            dpll_ddr_m2_ck          q   0                              E                             I   x      clock@2b4         
   ti,clksel           E                                          clock@23            E            ti,mux-clock            dpll_gmac_byp_mux           q                          I   1         clock@2a8                        ti,omap4-dpll-clock         dpll_gmac_ck            q      1        E                I   2      clock-dpll-gmac-m2-8@2b8                         ti,divider-clock            dpll_gmac_m2_ck         q   2                              E                            I   y      clock-video2-dclk-div                        fixed-factor-clock          video2_dclk_div         q   3        r           }           I         clock-video1-dclk-div                        fixed-factor-clock          video1_dclk_div         q   4        r           }           I         clock-hdmi-dclk-div                      fixed-factor-clock          hdmi_dclk_div           q   5        r           }           I         clock-per-dpll-hs-clk-div                        fixed-factor-clock          per_dpll_hs_clk_div         q           r           }           I   H      clock-usb-dpll-hs-clk-div                        fixed-factor-clock          usb_dpll_hs_clk_div         q           r           }           I   L      clock-eve-dpll-hs-clk-div                        fixed-factor-clock          eve_dpll_hs_clk_div         q            r           }           I   6      clock@290         
   ti,clksel           E                                          clock@23            E            ti,mux-clock            dpll_eve_byp_mux            q      6                    I   7         clock@284                        ti,omap4-dpll-clock         dpll_eve_ck         q      7        E                I   8      clock-dpll-eve-m2-8@294                      ti,divider-clock            dpll_eve_m2_ck          q   8                              E                            I   9      clock-eve-dclk-div                       fixed-factor-clock          eve_dclk_div            q   9        r           }           I         clock-dpll-core-h13x2-8@140                      ti,divider-clock            dpll_core_h13x2_ck          q              ?                   E  @                          I  *      clock-dpll-core-h14x2-8@144                      ti,divider-clock            dpll_core_h14x2_ck          q              ?                   E  D                          I   V      clock-dpll-core-h22x2-8@154                      ti,divider-clock            dpll_core_h22x2_ck          q              ?                   E  T                          I   B      clock-dpll-core-h23x2-8@158                      ti,divider-clock            dpll_core_h23x2_ck          q              ?                   E  X                          I   [      clock-dpll-core-h24x2-8@15c                      ti,divider-clock            dpll_core_h24x2_ck          q              ?                   E  \                          I  +      clock-dpll-ddr-x2                        ti,omap4-dpll-x2-clock          dpll_ddr_x2_ck          q   0        I   :      clock-dpll-ddr-h11x2-8@228                       ti,divider-clock            dpll_ddr_h11x2_ck           q   :           ?                   E  (                          I  ,      clock-dpll-dsp-x2                        ti,omap4-dpll-x2-clock          dpll_dsp_x2_ck          q   %        I   ;      clock-dpll-dsp-m3x2-8@248                        ti,divider-clock            dpll_dsp_m3x2_ck            q   ;                              E  H                             <        ׄ         I   <      clock-dpll-gmac-x2                       ti,omap4-dpll-x2-clock          dpll_gmac_x2_ck         q   2        I   =      clock-dpll-gmac-h11x2-8@2c0                      ti,divider-clock            dpll_gmac_h11x2_ck          q   =           ?                   E                            I   >      clock-dpll-gmac-h12x2-8@2c4                      ti,divider-clock            dpll_gmac_h12x2_ck          q   =           ?                   E                            I  -      clock-dpll-gmac-h13x2-8@2c8                      ti,divider-clock            dpll_gmac_h13x2_ck          q   =           ?                   E                            I         clock-dpll-gmac-m3x2-8@2bc                       ti,divider-clock            dpll_gmac_m3x2_ck           q   =                              E                            I         clock-gmii-m-clk-div                         fixed-factor-clock          gmii_m_clk_div          q   >        r           }           I  .      clock-hdmi-clk2-div                      fixed-factor-clock          hdmi_clk2_div           q   5        r           }           I  /      clock-hdmi-div                       fixed-factor-clock          hdmi_div_clk            q   5        r           }           I  0      clock@100         
   ti,clksel           E                                           clock@4         E            ti,divider-clock            l3_iclk_div                    q                                 I            clock-l4-root-clk-div                        fixed-factor-clock          l4_root_clk_div         q           r           }           I         clock-video1-clk2-div                        fixed-factor-clock          video1_clk2_div         q   ?        r           }           I  1      clock-video1-div                         fixed-factor-clock          video1_div_clk          q   ?        r           }           I  2      clock-video2-clk2-div                        fixed-factor-clock          video2_clk2_div         q   @        r           }           I  3      clock-video2-div                         fixed-factor-clock          video2_div_clk          q   @        r           }           I  4      clock-dummy                      fixed-clock       	  dummy_ck            b            I  5         clockdomains            I  6      clock@300            ti,omap4-cm         mpu_cm          E                                                         I  7   clock@20             ti,clkctrl          mpu_clkctrl         E                          I            clock@400            ti,omap4-cm         dsp1_cm         E                                                         I  8   clock@20             ti,clkctrl          dsp1_clkctrl            E                          I            clock@500            ti,omap4-cm         ipu_cm          E                                                         I  9   clock@20             ti,clkctrl          ipu1_clkctrl            E                             A                  B        I   A      clock@50             ti,clkctrl          ipu_clkctrl         E   P   4                   I            clock@600            ti,omap4-cm         dsp2_cm         E                                                         I  :   clock@20             ti,clkctrl          dsp2_clkctrl            E                          I            clock@700            ti,omap4-cm         rtc_cm          E      `                                           `        I  ;   clock@20             ti,clkctrl          rtc_clkctrl         E       (                   I            clock@760            ti,omap4-cm         vpe_cm          E  `                                          `           I  <   clock@0          ti,clkctrl          vpe_clkctrl         E                          I                  target-module@8000           ti,sysc-omap4 ti,sysc           E              Arev                                                cm_core@0            ti,dra7-cm-core simple-bus                                   E      0                   0         I  =   clocks                                    I  >   clock@200                        ti,omap4-dpll-clock         dpll_pcie_ref_ck            q              E                 I   C      clock-dpll-pcie-ref-m2ldo-8@210                      ti,divider-clock            dpll_pcie_ref_m2ldo_ck          q   C                              E                            I   D      clock-apll-pcie-in-clk-mux-7@4ae06118            ti,mux-clock            apll_pcie_in_clk_mux            q   D   E                    E                        I   F      clock@21c                        ti,dra7-apll-clock          apll_pcie_ck            q   F   C        E             I   G      clock-optfclk-pciephy-div-8@4a00821c             ti,divider-clock            optfclk_pciephy_div         q   G                    E          $                                    I   f      clock-apll-pcie-clkvcoldo                        fixed-factor-clock          apll_pcie_clkvcoldo         q   G        r           }           I  ?      clock-apll-pcie-clkvcoldo-div                        fixed-factor-clock          apll_pcie_clkvcoldo_div         q   G        r           }           I  @      clock-apll-pcie-m2                       fixed-factor-clock          apll_pcie_m2_ck         q   G        r           }           I   }      clock@14c         
   ti,clksel           E  L                                        clock@23            E            ti,mux-clock            dpll_per_byp_mux            q      H                    I   I         clock@140                        ti,omap4-dpll-clock         dpll_per_ck         q      I        E  @  D  L  H        I   J      clock-dpll-per-m2-8@150                      ti,divider-clock            dpll_per_m2_ck          q   J                              E  P                          I   K      clock-func-96m-aon-dclk-div                      fixed-factor-clock          func_96m_aon_dclk_div           q   K        r           }           I         clock@18c         
   ti,clksel           E                                          clock@23            E            ti,mux-clock            dpll_usb_byp_mux            q      L                    I   M         clock@180                        ti,omap4-dpll-j-type-clock          dpll_usb_ck         q      M        E                I   N      clock-dpll-usb-m2-8@190                      ti,divider-clock            dpll_usb_m2_ck          q   N                              E                            I   R      clock-dpll-pcie-ref-m2-8@210                         ti,divider-clock            dpll_pcie_ref_m2_ck         q   C                              E                            I   |      clock-dpll-per-x2                        ti,omap4-dpll-x2-clock          dpll_per_x2_ck          q   J        I   O      clock-dpll-per-h11x2-8@158                       ti,divider-clock            dpll_per_h11x2_ck           q   O           ?                   E  X                          I   P      clock-dpll-per-h12x2-8@15c                       ti,divider-clock            dpll_per_h12x2_ck           q   O           ?                   E  \                          I  A      clock-dpll-per-h13x2-8@160                       ti,divider-clock            dpll_per_h13x2_ck           q   O           ?                   E  `                          I  B      clock-dpll-per-h14x2-8@164                       ti,divider-clock            dpll_per_h14x2_ck           q   O           ?                   E  d                          I   W      clock-dpll-per-m2x2-8@150                        ti,divider-clock            dpll_per_m2x2_ck            q   O                              E  P                          I   Q      clock-dpll-usb-clkdcoldo                         fixed-factor-clock          dpll_usb_clkdcoldo          q   N        r           }           I   T      clock-func-128m                      fixed-factor-clock          func_128m_clk           q   P        r           }           I  C      clock-func-12m-fclk                      fixed-factor-clock          func_12m_fclk           q   Q        r           }           I  D      clock-func-24m                       fixed-factor-clock          func_24m_clk            q   K        r           }           I  E      clock-func-48m-fclk                      fixed-factor-clock          func_48m_fclk           q   Q        r           }           I  F      clock-func-96m-fclk                      fixed-factor-clock          func_96m_fclk           q   Q        r           }           I  G      clock-l3init-60m@104                         ti,divider-clock            l3init_60m_fclk         q   R        E          $              I  H      clock-clkout2-8@6b0                      ti,gate-clock           clkout2_clk         q   S                   E          I  	      clock-l3init-960m-gfclk-8@6c0                        ti,gate-clock           l3init_960m_gfclk           q   T                   E          I  I      clock-usb-phy1-always-on-clk32k-8@640                        ti,gate-clock           usb_phy1_always_on_clk32k           q   U                   E  @        I   `      clock-usb-phy2-always-on-clk32k-8@688                        ti,gate-clock           usb_phy2_always_on_clk32k           q   U                   E          I   b      clock-usb-phy3-always-on-clk32k-8@698                        ti,gate-clock           usb_phy3_always_on_clk32k           q   U                   E          I   c      clock-gpu-core-gclk-mux-24@1220                      ti,mux-clock            gpu_core_gclk_mux           q   V   W   -                   E              X           -        I   X      clock-gpu-hyd-gclk-mux-26@1220                       ti,mux-clock            gpu_hyd_gclk_mux            q   V   W   -                   E              Y           -        I   Y      clock-l3instr-ts-gclk-div-24@e50                         ti,divider-clock            l3instr_ts_gclk_div         q   Z                   E  P        $                  I  J      clock-vip1-gclk-mux-24@1020                      ti,mux-clock            vip1_gclk_mux           q      [                   E           I  K      clock-vip2-gclk-mux-24@1028                      ti,mux-clock            vip2_gclk_mux           q      [                   E  (        I  L      clock-vip3-gclk-mux-24@1030                      ti,mux-clock            vip3_gclk_mux           q      [                   E  0        I  M         clockdomains            I  N   clock-coreaon-clkdm          ti,clockdomain          coreaon_clkdm           q   N        I  O         clock@600            ti,omap4-cm         coreaon_cm          E                                                         I  P   clock@20             ti,clkctrl          coreaon_clkctrl         E                          I   g         clock@700            ti,omap4-cm         l3main1_cm          E                                                         I  Q   clock@20             ti,clkctrl          l3main1_clkctrl         E       t                   I   	         clock@900            ti,omap4-cm         ipu2_cm         E  	                                           	            I  R   clock@20             ti,clkctrl          ipu2_clkctrl            E                          I            clock@a00            ti,omap4-cm         dma_cm          E  
                                           
            I  S   clock@20             ti,clkctrl          dma_clkctrl         E                          I   ^         clock@b00            ti,omap4-cm         emif_cm         E                                                         I  T   clock@20             ti,clkctrl          emif_clkctrl            E                          I  U         clock@c00            ti,omap4-cm         atl_cm          E                                                         I  V   clock@0          ti,clkctrl          atl_clkctrl         E                          I            clock@d00            ti,omap4-cm       	  l4cfg_cm            E                                                         I  W   clock@20             ti,clkctrl          l4cfg_clkctrl           E                          I            clock@e00            ti,omap4-cm         l3instr_cm          E                                                         I  X   clock@20             ti,clkctrl          l3instr_clkctrl         E                          I   
         clock@f00            ti,omap4-cm         iva_cm          E                                                         I  Y   clock@20             ti,clkctrl          iva_clkctrl         E                          I            clock@1000           ti,omap4-cm         cam_cm          E                                                         I  Z   clock@20             ti,clkctrl          cam_clkctrl         E       ,                   I            clock@1100           ti,omap4-cm         dss_cm          E                                                         I  [   clock@20             ti,clkctrl          dss_clkctrl         E                          I            clock@1200           ti,omap4-cm         gpu_cm          E                                                         I  \   clock@20             ti,clkctrl          gpu_clkctrl         E                          I            clock@1300           ti,omap4-cm       
  l3init_cm           E                                                         I  ]   clock@20             ti,clkctrl          l3init_clkctrl          E       l                         I   _      clock@b0             ti,clkctrl          pcie_clkctrl            E                         I   e      clock@d0             ti,clkctrl          gmac_clkctrl            E                         I            clock@1700           ti,omap4-cm       	  l4per_cm            E                                                         I  ^   clock@28             ti,clkctrl          l4per_clkctrl         (  E   (   d      $      <  @     p                         \  \              ]        I         clock@1a0            ti,clkctrl          l4sec_clkctrl           E     ,                   I         clock@c          ti,clkctrl          l4per2_clkctrl        @  E                          8     `     x   $     <                   I   \      clock@14             ti,clkctrl          l4per3_clkctrl          E              0                      I                  target-module@56000          ti,sysc-omap2 ti,sysc           E `     `,    `(           Arev sysc syss           0  #        =                     K                     Y           q   ^                xfck                                       `       dma-controller@0             ti,omap4430-sdma ti,omap-sdma           E             0                             	          
           .           f            9           I            target-module@5e000          ti,sysc       	  disabled                                                     target-module@80000          ti,sysc-omap2 ti,sysc           E                        Arev sysc syss           0           K                  Y           q   _               xfck                                               ocp2scp@0            ti,omap-ocp2scp                                                     E           phy@4000             ti,dra7x-usb2 ti,omap-usb2          E  @            s              q   `   _              xwkupclk refclk                         a        I         phy@5000              ti,dra7x-usb2-phy2 ti,omap-usb2         E  P            s     t        q   b   _               xwkupclk refclk                         a        I         phy@4400             ti,omap-usb3            E  D      H    d  L    @        Aphy_rx phy_tx pll_ctrl          s     p        q   c      _              xwkupclk sysclk refclk                       I               target-module@90000          ti,sysc-omap2 ti,sysc           E 	      	     	            Arev sysc syss           0           K                  Y           q   _               xfck                                       	        ocp2scp@0            ti,omap-ocp2scp                                                     E           pciephy@4000             ti,phy-pipe3-pcie           E  @      D    d        Aphy_rx phy_tx           s   d              d         4  q   C   D   e          e       	   e       
   f         ;  xdpll_ref dpll_ref_m2 wkupclk refclk div-clk phy-div sysclk                      I         pciephy@5000             ti,phy-pipe3-pcie           E  P      T    d        Aphy_rx phy_tx           s   d               d         4  q   C   D   e         e      	   e      
   f         ;  xdpll_ref dpll_ref_m2 wkupclk refclk div-clk phy-div sysclk                    	  disabled            I         phy@6000             ti,phy-pipe3-sata           E  `      d    d  h    @        Aphy_rx phy_tx pll_ctrl          s     t        q      _   h           xsysclk refclk                                    I   i            target-module@a0000          ti,sysc       	  disabled                                          
           target-module@d9000          ti,sysc-omap4-sr ti,sysc            E 8           Asysc            0           K                     q   g               xfck                                                 target-module@dd000          ti,sysc-omap4-sr ti,sysc            E 8           Asysc            0           K                     q   g               xfck                                                 target-module@e0000          ti,sysc       	  disabled                                                     target-module@f4000          ti,sysc-omap4 ti,sysc           E @     @         	  Arev sysc            0           K                  q                  xfck                                       @       mailbox@0            ti,omap4-mailbox            E             $                                                                       	  disabled            I  _         target-module@f6000          ti,sysc-omap2 ti,sysc           E `     `    `           Arev sysc syss           0           K                  Y           q                  xfck                                       `       spinlock@0           ti,omap4-hwspinlock         E                          I  `            segment@100000           simple-pm-bus                                               0  0                                                       0  0     @  @     P  P     `  `     p  p                                                                        0  0     @  @     P  P     `  `     p  p                                          0  0     @  @     P  P     `  `     p  p                            0  0     @  @     P  P     `  `     p  p                                                                                                        "   target-module@2000           ti,sysc       	  disabled                                                      target-module@8000           ti,sysc       	  disabled                                                     target-module@40000          ti,sysc-omap4 ti,sysc           E                	  Arev sysc            =                  K                        h        q   _   h            xfck                                               sata@0           snps,dwc-ahci           E                            1              i      	  sata-phy            q   _   h                      okay            I  a         target-module@51000          ti,sysc       	  disabled                                                    target-module@53000          ti,sysc       	  disabled                                          0          target-module@55000          ti,sysc       	  disabled                                          P          target-module@57000          ti,sysc       	  disabled                                          p          target-module@59000          ti,sysc       	  disabled                                                    target-module@5b000          ti,sysc       	  disabled                                                    target-module@5d000          ti,sysc       	  disabled                                                    target-module@5f000          ti,sysc       	  disabled                                                    target-module@61000          ti,sysc       	  disabled                                                    target-module@63000          ti,sysc       	  disabled                                          0          target-module@65000          ti,sysc       	  disabled                                          P          target-module@67000          ti,sysc       	  disabled                                          p          target-module@69000          ti,sysc       	  disabled                                                    target-module@6b000          ti,sysc       	  disabled                                                    target-module@6d000          ti,sysc       	  disabled                                                    target-module@71000          ti,sysc       	  disabled                                                    target-module@73000          ti,sysc       	  disabled                                          0          target-module@75000          ti,sysc       	  disabled                                          P          target-module@77000          ti,sysc       	  disabled                                          p          target-module@79000          ti,sysc       	  disabled                                                    target-module@7b000          ti,sysc       	  disabled                                                    target-module@7d000          ti,sysc       	  disabled                                                    target-module@81000          ti,sysc       	  disabled                                                    target-module@83000          ti,sysc       	  disabled                                          0          target-module@85000          ti,sysc       	  disabled                                          P          target-module@87000          ti,sysc       	  disabled                                          p             segment@200000           simple-pm-bus                                      !       !                                                                                  !        !        !      0  !0     @  !@     P  !P       "       "       !       !       !       !        "        "     @  "@     P  "P     `  "`     p  "p       "       "       "       "        #        #        #      0  #0     @  #@     P  #P     `  #`     p  #p       !       !       target-module@0          ti,sysc       	  disabled                                                      target-module@a000           ti,sysc       	  disabled                                                     target-module@c000           ti,sysc       	  disabled                                                     target-module@e000           ti,sysc       	  disabled                                                     target-module@10000          ti,sysc       	  disabled                                                     target-module@12000          ti,sysc       	  disabled                                                     target-module@14000          ti,sysc       	  disabled                                          @          target-module@18000          ti,sysc       	  disabled                                                    target-module@1a000          ti,sysc       	  disabled                                                    target-module@1c000          ti,sysc       	  disabled                                                    target-module@1e000          ti,sysc       	  disabled                                                    target-module@20000          ti,sysc       	  disabled                                                     target-module@24000          ti,sysc       	  disabled                                          @          target-module@26000          ti,sysc       	  disabled                                          `          target-module@2a000          ti,sysc       	  disabled                                                    target-module@2c000          ti,sysc       	  disabled                                                    target-module@2e000          ti,sysc       	  disabled                                                    target-module@30000          ti,sysc       	  disabled                                                     target-module@32000          ti,sysc       	  disabled                                                     target-module@34000          ti,sysc       	  disabled                                          @          target-module@36000          ti,sysc       	  disabled                                          `                interconnect@4ae00000            ti,dra7-l4-wkup simple-pm-bus              j        q   k                xfck         EJ     J    J          
  Aap la ia0                                  0      J        J        J        J             I  b   segment@0            simple-pm-bus                                  l                                 `   `                @   @      P   P                         target-module@4000           ti,sysc-omap2 ti,sysc           E  @      @         	  Arev sysc            K                     q   k   0            xfck                                        @       counter@0            ti,omap-counter32k          E       @        I  c         target-module@6000           ti,sysc-omap4 ti,sysc           E  `            Arev                                        `        prm@0            ti,dra7-prm simple-bus          E      0                                                              0         I  d   clocks                                    I  e   clock-sys-clkin1@110                         ti,mux-clock            sys_clkin1          q   l   m   n   o   p   q   r        E                   I         clock@118         
   ti,clksel           E                                          clock@0         E             ti,mux-clock            abe_dpll_sys_clk_mux            q      s                    I   t         clock-abe-dpll-bypass-clk-mux@114                        ti,mux-clock            abe_dpll_bypass_clk_mux         q   t   U        E          I         clock-abe-dpll-clk-mux@10c                       ti,mux-clock            abe_dpll_clk_mux            q   t   U        E          I         clock-abe-24m@11c                        ti,divider-clock            abe_24m_fclk            q           E          $              I   ]      clock-aess@178                       ti,divider-clock          
  aess_fclk           q   u        E  x                   I   v      clock-abe-giclk-div@174                      ti,divider-clock            abe_giclk_div           q   v        E  t                   I  f      clock-abe-lp-clk-div@1d8                         ti,divider-clock            abe_lp_clk_div          q           E          $               I         clock-abe-sys-clk-div@120                        ti,divider-clock            abe_sys_clk_div         q           E                      I  g      clock-adc-gfclk-mux@1dc                      ti,mux-clock            adc_gfclk_mux           q      s   U        E          I  h      clock-sys-clk1-dclk-div@1c8                      ti,divider-clock            sys_clk1_dclk_div           q              @        E                   I         clock-sys-clk2-dclk-div@1cc                      ti,divider-clock            sys_clk2_dclk_div           q   s           @        E                   I         clock-per-abe-x1-dclk-div@1bc                        ti,divider-clock            per_abe_x1_dclk_div         q   w           @        E                   I         clock@18c         
   ti,clksel           E                                          clock@0         E             ti,divider-clock            dsp_gclk_div            q   &           @                             I            clock-gpu-dclk@1a0                       ti,divider-clock          	  gpu_dclk            q   -           @        E                   I         clock-emif-phy-dclk-div@190                      ti,divider-clock            emif_phy_dclk_div           q   x           @        E                   I         clock-gmac-250m-dclk-div@19c                         ti,divider-clock            gmac_250m_dclk_div          q   y           @        E                   I   z      clock-gmac-main                      fixed-factor-clock          gmac_main_clk           q   z        r           }           I         clock-l3init-480m-dclk-div@1ac                       ti,divider-clock            l3init_480m_dclk_div            q   R           @        E                   I         clock-usb-otg-dclk-div@184                       ti,divider-clock            usb_otg_dclk_div            q   {           @        E                   I         clock-sata-dclk-div@1c0                      ti,divider-clock            sata_dclk_div           q              @        E                   I         clock-pcie2-dclk-div@1b8                         ti,divider-clock            pcie2_dclk_div          q   |           @        E                   I         clock-pcie-dclk-div@1b4                      ti,divider-clock            pcie_dclk_div           q   }           @        E                   I         clock-emu-dclk-div@194                       ti,divider-clock            emu_dclk_div            q              @        E                   I         clock-secure-32k-dclk-div@1c4                        ti,divider-clock            secure_32k_dclk_div         q   ~           @        E                   I         clock-clkoutmux0-clk-mux@158                         ti,mux-clock            clkoutmux0_clk_mux        X  q                              z                                            E  X        I  i      clock-clkoutmux1-clk-mux@15c                         ti,mux-clock            clkoutmux1_clk_mux        X  q                              z                                            E  \        I  j      clock-clkoutmux2-clk-mux@160                         ti,mux-clock            clkoutmux2_clk_mux        X  q                              z                                            E  `        I   S      clock-custefuse-sys-gfclk-div                        fixed-factor-clock          custefuse_sys_gfclk_div         q           r           }           I  k      clock-eve@180                        ti,mux-clock            eve_clk         q   9   <        E          I  l      clock-hdmi-dpll-clk-mux@164                      ti,mux-clock            hdmi_dpll_clk_mux           q      s        E  d        I  m      clock-mlb@134                        ti,divider-clock            mlb_clk         q              @        E  4                 I  n      clock-mlbp@130                       ti,divider-clock          	  mlbp_clk            q              @        E  0                 I  o      clock-per-abe-x1-gfclk2-div@138                      ti,divider-clock            per_abe_x1_gfclk2_div           q   w           @        E  8                 I  p      clock-timer-sys-clk-div@144                      ti,divider-clock            timer_sys_clk_div           q           E  D                   I         clock-video1-dpll-clk-mux@168                        ti,mux-clock            video1_dpll_clk_mux         q      s        E  h        I  q      clock-video2-dpll-clk-mux@16c                        ti,mux-clock            video2_dpll_clk_mux         q      s        E  l        I  r      clock-wkupaon-iclk-mux@108                       ti,mux-clock            wkupaon_iclk_mux            q              E          I   Z         clockdomains            I  s      clock@1800           ti,omap4-cm         wkupaon_cm          E                                                         I  t   clock@20             ti,clkctrl          wkupaon_clkctrl         E       l                   I   k         prm@300       "   ti,dra7-prm-inst ti,omap-prm-inst           E              	            I         prm@400       "   ti,dra7-prm-inst ti,omap-prm-inst           E                         	            I         prm@500       "   ti,dra7-prm-inst ti,omap-prm-inst           E                         	            I         prm@628       "   ti,dra7-prm-inst ti,omap-prm-inst           E  (           	            I         prm@700       "   ti,dra7-prm-inst ti,omap-prm-inst           E                         	            I         prm@f00       "   ti,dra7-prm-inst ti,omap-prm-inst           E                         	            I         prm@1000          "   ti,dra7-prm-inst ti,omap-prm-inst           E              	            I  u      prm@1100          "   ti,dra7-prm-inst ti,omap-prm-inst           E              	            I  v      prm@1200          "   ti,dra7-prm-inst ti,omap-prm-inst           E              	            I  w      prm@1300          "   ti,dra7-prm-inst ti,omap-prm-inst           E                         	            I   h      prm@1400          "   ti,dra7-prm-inst ti,omap-prm-inst           E              	            I         prm@1600          "   ti,dra7-prm-inst ti,omap-prm-inst           E              	            I  x      prm@1724          "   ti,dra7-prm-inst ti,omap-prm-inst           E  $           	            I   j      prm@1b00          "   ti,dra7-prm-inst ti,omap-prm-inst           E      @                   	            I         prm@1b40          "   ti,dra7-prm-inst ti,omap-prm-inst           E  @   @        	            I  y      prm@1b80          "   ti,dra7-prm-inst ti,omap-prm-inst           E     @        	            I  z      prm@1bc0          "   ti,dra7-prm-inst ti,omap-prm-inst           E     @        	            I  {      prm@1c00          "   ti,dra7-prm-inst ti,omap-prm-inst           E      `        	            I  |      prm@1c60          "   ti,dra7-prm-inst ti,omap-prm-inst           E  `            	            I  }      prm@1c80          "   ti,dra7-prm-inst ti,omap-prm-inst           E             	            I               target-module@c000           ti,sysc-omap4 ti,sysc           E              Arev                                               scm_conf@0           syscon          E               I               segment@10000            simple-pm-bus                                  `                      @  @      P  P                                       target-module@0          ti,sysc-omap2 ti,sysc           E                          Arev sysc syss           0           K                     Y           q   k          k            
  xfck dbclk                                                  gpio@0           ti,omap4-gpio           E                                  *        :                    4           I            target-module@4000           ti,sysc-omap2 ti,sysc           E  @      @     @           Arev sysc syss           0   "        K                     Y           q   k               xfck                                        @       wdt@0            ti,omap3-wdt            E                      K           I  ~         target-module@8000           ti,sysc-omap4-timer ti,sysc         E                 	  Arev sysc            0           K                     q   k                xfck                                                     F         Z        I     timer@0          ti,omap5430-timer           E               q   k               xfck                             e           k                  U        I           target-module@c000           ti,sysc       	  disabled                                                        segment@20000            simple-pm-bus                                      `  `                                          0  0      p  p                                                               target-module@0          ti,sysc-omap4-timer ti,sysc         E                   	  Arev sysc            0           K                     q   k   (            xfck                                                timer@0          ti,omap5430-timer           E                      Z            e         t        I           target-module@2000           ti,sysc       	  disabled                                                      target-module@6000           ti,sysc       	  disabled                                   H        `         p                (         *         0             target-module@b000           ti,sysc-omap2 ti,sysc           E  P     T     X           Arev sysc syss           0           K                     Y           q   k   `            xfck                                               serial@0             ti,dra742-uart          E                                 bl       	  disabled            I           target-module@f000           ti,sysc       	  disabled                                                        segment@30000            simple-pm-bus                                                                                   0  0      @  @      P  P      `  `      p  p                               target-module@1000           ti,sysc       	  disabled                                                     target-module@3000           ti,sysc       	  disabled                                           0          target-module@5000           ti,sysc       	  disabled                                           P          target-module@7000           ti,sysc       	  disabled                                           p          target-module@9000           ti,sysc       	  disabled                                                     target-module@c000           ti,sysc-omap4 ti,sysc           E              Arev         q   k   h            xfck                                                can@0            ti,dra7-d_can           E                     X                              q   k   h         	  disabled            I                 interconnect@48000000            ti,dra7-l4-per1 simple-pm-bus                      q                  xfck       0  EH      H     H     H     H     H             Aap la ia0 ia1 ia2 ia3                                        H           H               I     segment@0            simple-pm-bus                                                                                          0  0     @  @     P  P     `  `     p  p                   P  P     `  `     p  p                                                                                                                                  0  0            0  0     @  @              0  0                   `  `     p  p                                   	  	     	  	     	  	     	  	     	  	     	  	                   	   	       	   	      
@  
@     
`  
`     
  
   @  
  
     
  
     
  
     `  `     p  p     @  @     P  P                                                 P  P     `  `     
   
      
0  
0                                
P  
P                                   target-module@20000          ti,sysc-omap2 ti,sysc           E  P     T     X           Arev sysc syss           0           K                     Y           q     (            xfck                                               serial@0             ti,dra742-uart          E                      E           bl         okay                  5      6        tx rx           -          E                I           target-module@32000          ti,sysc-omap4-timer ti,sysc         E                 	  Arev sysc            0           K                     q                  xfck                                               timer@0          ti,omap5430-timer           E               q                    xfck timer_sys_ck                   !           I           target-module@34000          ti,sysc-omap4-timer ti,sysc         E @     @         	  Arev sysc            0           K                     q                  xfck                                       @            I     timer@0          ti,omap5430-timer           E               q                    xfck timer_sys_ck                   "           I            target-module@36000          ti,sysc-omap4-timer ti,sysc         E `     `         	  Arev sysc            0           K                     q                   xfck                                       `            I     timer@0          ti,omap5430-timer           E               q                     xfck timer_sys_ck                   #           I            target-module@3e000          ti,sysc-omap4-timer ti,sysc         E               	  Arev sysc            0           K                     q      (            xfck                                              timer@0          ti,omap5430-timer           E               q      (              xfck timer_sys_ck                   (           I            target-module@51000          ti,sysc-omap2 ti,sysc           E                     Arev sysc syss           0           K                     Y           q                         
  xfck dbclk                                                      F                 I     gpio@0           ti,omap4-gpio           E                                  *        :                    4           I            target-module@53000          ti,sysc-omap2 ti,sysc           E 0     0    1           Arev sysc syss           0           K                     Y           q                         
  xfck dbclk                                         0       gpio@0           ti,omap4-gpio           E                      t            *        :                    4           I           target-module@55000          ti,sysc-omap2 ti,sysc           E P     P    Q           Arev sysc syss           0           K                     Y           q      8          8         
  xfck dbclk                                         P            I     gpio@0           ti,omap4-gpio           E                                  *        :                    4           I            target-module@57000          ti,sysc-omap2 ti,sysc           E p     p    q           Arev sysc syss           0           K                     Y           q      @          @         
  xfck dbclk                                         p            I     gpio@0           ti,omap4-gpio           E                                  *        :                    4           I           target-module@59000          ti,sysc-omap2 ti,sysc           E                     Arev sysc syss           0           K                     Y           q      H          H         
  xfck dbclk                                                gpio@0           ti,omap4-gpio           E                                  *        :                    4           I            target-module@5b000          ti,sysc-omap2 ti,sysc           E                     Arev sysc syss           0           K                     Y           q      P          P         
  xfck dbclk                                                gpio@0           ti,omap4-gpio           E                                  *        :                    4           I           target-module@5d000          ti,sysc-omap2 ti,sysc           E                     Arev sysc syss           0           K                     Y           q      X          X         
  xfck dbclk                                                gpio@0           ti,omap4-gpio           E                                  *        :                    4           I            target-module@60000          ti,sysc-omap2 ti,sysc           E                        Arev sysc syss           0          K                     Y           q                  xfck                                               i2c@0            ti,omap4-i2c            E                      8                                     okay            b         I     rtc@6f           microchip,mcp7941x          E   o        -                  $        irq wakeup                              I              target-module@66000          ti,sysc-omap2 ti,sysc           E `P    `T    `X           Arev sysc syss           0           K                     Y           q     H            xfck                                       `       serial@0             ti,dra742-uart          E                      d           bl       	  disabled                  ?      @        tx rx           I           target-module@68000          ti,sysc-omap2 ti,sysc           E P    T    X           Arev sysc syss           0           K                     Y           q      0            xfck                                              serial@0             ti,dra742-uart          E                      e           bl       	  disabled                  O      P        tx rx           I           target-module@6a000          ti,sysc-omap2 ti,sysc           E P    T    X           Arev sysc syss           0           K                     Y           q                 xfck                                              serial@0             ti,dra742-uart          E               -          C           bl       	  disabled                  1      2        tx rx           I           target-module@6c000          ti,sysc-omap2 ti,sysc           E P    T    X           Arev sysc syss           0           K                     Y           q                  xfck                                              serial@0             ti,dra742-uart          E                      D           bl       	  disabled                  3      4        tx rx           I           target-module@6e000          ti,sysc-omap2 ti,sysc           E P    T    X           Arev sysc syss           0           K                     Y           q     0            xfck                                              serial@0             ti,dra742-uart          E                      A           bl       	  disabled                  7      8        tx rx           I           target-module@70000          ti,sysc-omap2 ti,sysc           E                        Arev sysc syss           0          K                     Y           q      x            xfck                                               i2c@0            ti,omap4-i2c            E                      3                                     okay            b         I     tps659038@58             ti,tps659038            E   X         &                          4                                      I      tps659038_pmic           ti,tps659038-pmic      regulators     smps12          Ksmps12          Z P        r                   *        I         smps3           Ksmps3           Z p        r p                  *        I        smps45          Ksmps45          Z P        r                   *        I        smps6           Ksmps6           Z P        r 0                  *        I        smps8           Ksmps8           Z w@        r w@                  *        I        ldo1            Kldo1            Z w@        r 2Z         *                 I         ldo2            Kldo2            Z 2Z        r 2Z                  *        I        ldo3            Kldo3            Z w@        r w@                  *        I        ldo4            Kldo4            Z w@        r w@                  *        I         ldo9            Kldo9            Z         r                   *        I        ldoln           Kldoln           Z w@        r w@                  *        I         ldousb          Kldousb          Z 2Z        r 2Z         *        I   a      regen1          Kregen1           *                 I               tps659038_rtc            ti,palmas-rtc            &                                  I        tps659038_pwr_button             ti,palmas-pwrbutton          &                                  <           I        tps659038_gpio           ti,palmas-gpio           *        :           I        tps659038_usb            ti,palmas-usb-vid            Y        r                  I            tmp102@48         
   ti,tmp102           E   H         &                         |           I         tlv320aic3104@18                         ti,tlv320aic3104            E              S                   okay               (                                                    I        eeprom@50            atmel,24c32         E   P        I              target-module@72000          ti,sysc-omap2 ti,sysc           E                        Arev sysc syss           0          K                     Y           q                  xfck                                               i2c@0            ti,omap4-i2c            E                      4                                   	  disabled            I           target-module@78000          ti,sysc-omap2 ti,sysc           E                     Arev sysc syss           0          K                     Y           q      0            xfck                                              elm@0            ti,am3352-elm           E                              	  disabled            I           target-module@7a000          ti,sysc-omap2 ti,sysc           E                     Arev sysc syss           0          K                     Y           q                  xfck                                              i2c@0            ti,omap4-i2c            E                      9                                   	  disabled            I           target-module@7c000          ti,sysc-omap2 ti,sysc           E                     Arev sysc syss           0          K                     Y           q      (            xfck                                              i2c@0            ti,omap4-i2c            E                      7                                   	  disabled            I           target-module@86000          ti,sysc-omap4-timer ti,sysc         E `     `         	  Arev sysc            0           K                     q                   xfck                                       `       timer@0          ti,omap5430-timer           E               q                     xfck timer_sys_ck                   )           I            target-module@88000          ti,sysc-omap4-timer ti,sysc         E               	  Arev sysc            0           K                     q                  xfck                                              timer@0          ti,omap5430-timer           E               q                    xfck timer_sys_ck                   *           I            target-module@90000          ti,sysc-omap2 ti,sysc           E 	    	         	  Arev sysc            0           K               q                   xfck                                       	         rng@0            ti,omap4-rng            E                       /           q           xfck         I           target-module@98000          ti,sysc-omap4 ti,sysc           E 	     	         	  Arev sysc            0           K                     q                  xfck                                       	       spi@0            ti,omap4-mcspi          E                      <                                              @        #      $      %      &      '      (      )      *         tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3       	  disabled            I           target-module@9a000          ti,sysc-omap4 ti,sysc           E 	     	         	  Arev sysc            0           K                     q                  xfck                                       	       spi@0            ti,omap4-mcspi          E                      =                                                       +      ,      -      .        tx0 rx0 tx1 rx1       	  disabled            I           target-module@9c000          ti,sysc-omap4 ti,sysc           E 	     	         	  Arev sysc            0           =                     K                     q   _               xfck                                       	       mmc@0            ti,dra7-sdhci           E                      N           okay                       q                           &default hs          4           >           H                  Q        Z           d           I           target-module@a2000          ti,sysc       	  disabled                                          
           target-module@a4000          ti,sysc       	  disabled                                          
@        
P          target-module@a5000          ti,sysc-omap2 ti,sysc           E 
P0    
P4    
P8           Arev sysc syss           0           K                     Y           q                  xfck                                       
P            I     des@0            ti,omap4-des            E                      M                 u      t        tx rx           q           xfck         I           target-module@a8000          ti,sysc       	  disabled                                          
   @       target-module@ad000          ti,sysc-omap4 ti,sysc           E 
     
         	  Arev sysc            0           =                     K                     q                  xfck                                       
       mmc@0            ti,dra7-sdhci           E                      Y         	  disabled            А         p     @          I           target-module@b2000          ti,sysc-omap2 ti,sysc           E                        Arev sysc syss           0           Y            F        q      `            xfck                                               1w@0             ti,omap3-1w         E                      5           I           target-module@b4000          ti,sysc-omap4 ti,sysc           E @     @         	  Arev sysc            0           =                     K                     q   _               xfck                                       @       mmc@0            ti,dra7-sdhci           E                      Q           okay            q         p                                          &default hs ddr_3_3v         4           d                      >                     Q        Z                         I           target-module@b8000          ti,sysc-omap4 ti,sysc           E               	  Arev sysc            0           K                     q                  xfck                                              spi@0            ti,omap4-mcspi          E                      V                                                                    tx0 rx0       	  disabled            I           target-module@ba000          ti,sysc-omap4 ti,sysc           E               	  Arev sysc            0           K                     q                  xfck                                              spi@0            ti,omap4-mcspi          E                      +                                                      F      G        tx0 rx0       	  disabled            I           target-module@d1000          ti,sysc-omap4 ti,sysc           E               	  Arev sysc            0           =                     K                     q                  xfck                                              mmc@0            ti,dra7-sdhci           E                      [         	  disabled            q         p     @          I           target-module@d5000          ti,sysc       	  disabled                                          P             segment@200000           simple-pm-bus                                     target-module@48210000           ti,sysc-omap4-simple ti,sysc                       q                   xfck                                      H!        mpu          ti,omap5-mpu             interconnect@48400000            ti,dra7-l4-per2 simple-pm-bus                      q   \                xfck       (  EH@     H@    H@    H@    H@            Aap la ia0 ia1 ia2                                  l      H@   @  E  E   @  E  E   @  F   F    @  HC` HC`  @  HC HC  @  HD HD  @  HE  HE   @  HE@ HE@  @          I     segment@0            simple-pm-bus                                 T                                @  @   @                                                            @  @      `  `                                   `  `     p  p                                                                                           0  0                                      @  @      `  `                                    @  @     P  P                                                           0  0     @  @     P  P     `  `     p  p                                                             E  E   @  E  E   @  F   F    @  HC` HC`  @  HC HC  @  HD HD  @  HE  HE   @  HE@ HE@  @     target-module@20000          ti,sysc-omap2 ti,sysc           E  P     T     X           Arev sysc syss           0           K                     Y           q   \              xfck                                               serial@0             ti,dra742-uart          E                                 bl       	  disabled            I           target-module@22000          ti,sysc-omap2 ti,sysc           E  P     T     X           Arev sysc syss           0           K                     Y           q   \              xfck                                               serial@0             ti,dra742-uart          E                                 bl       	  disabled            I           target-module@24000          ti,sysc-omap2 ti,sysc           E @P    @T    @X           Arev sysc syss           0           K                     Y           q   \              xfck                                       @       serial@0             ti,dra742-uart          E                                 bl       	  disabled            I           target-module@2c000          ti,sysc       	  disabled                                                    target-module@36000          ti,sysc       	  disabled                                          `          target-module@3a000          ti,sysc       	  disabled                                                    target-module@3c000          ti,sysc-omap4 ti,sysc           E             Arev         q                   xfck                                                 	  disabled            I     atl@0            ti,dra7-atl         E                                  q                  xfck       	  disabled            I           target-module@3e000          ti,sysc-omap4 ti,sysc           E               	  Arev sysc            0           K                  q   \               xfck                                              epwmss@0              ti,dra746-pwmss ti,am33xx-pwmss         E       0                               	  disabled                               I     pwm@100          ti,dra746-ecap ti,am3352-ecap                      E              q           xfck       	  disabled            I        pwm@200       "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      E              q            
  xtbclk fck         	  disabled            I              target-module@40000          ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           K                  q   \               xfck                                               epwmss@0              ti,dra746-pwmss ti,am33xx-pwmss         E       0                               	  disabled                               I     pwm@100          ti,dra746-ecap ti,am3352-ecap                      E              q           xfck       	  disabled            I        pwm@200       "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      E              q            
  xtbclk fck         	  disabled            I              target-module@42000          ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           K                  q   \               xfck                                               epwmss@0              ti,dra746-pwmss ti,am33xx-pwmss         E       0                               	  disabled                               I     pwm@100          ti,dra746-ecap ti,am3352-ecap                      E              q           xfck       	  disabled            I        pwm@200       "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      E              q            
  xtbclk fck         	  disabled            I              target-module@46000          ti,sysc       	  disabled                                          `          target-module@48000          ti,sysc       	  disabled                                                    target-module@4a000          ti,sysc       	  disabled                                                    target-module@4c000          ti,sysc       	  disabled                                                    target-module@50000          ti,sysc       	  disabled                                                     target-module@54000          ti,sysc       	  disabled                                          @          target-module@58000          ti,sysc       	  disabled                                                     target-module@5b000          ti,sysc       	  disabled                                                    target-module@5d000          ti,sysc       	  disabled                                                    target-module@60000          ti,sysc-dra7-mcasp ti,sysc          E                 	  Arev sysc            K                $  q                                       xfck ahclkx ahclkr                                               E  E   @     mcasp@0          ti,dra7-mcasp-audio         E        E             Ampu dat                h          g           tx rx                                     tx rx         $  q                                       xfck ahclkx ahclkr         	  disabled            I           target-module@64000          ti,sysc-dra7-mcasp ti,sysc          E @     @         	  Arev sysc            K                $  q   \  T       \  T      \  T           xfck ahclkx ahclkr                                         @     E  E   @     mcasp@0          ti,dra7-mcasp-audio         E        E             Ampu dat                                     tx rx                                     tx rx         $  q   \  T                 \  T           xfck ahclkx ahclkr         	  disabled            I           target-module@68000          ti,sysc-dra7-mcasp ti,sysc          E               	  Arev sysc            K                  q   \  \       \  \           xfck ahclkx                                             F   F    @     mcasp@0          ti,dra7-mcasp-audio         E        F              Ampu dat                                     tx rx                                     tx rx           q   \  \       \  \           xfck ahclkx          okay                           \  \              s                                                                             I           target-module@6c000          ti,sysc-dra7-mcasp ti,sysc          E               	  Arev sysc            K                  q   \         \             xfck ahclkx                                             HC` HC`  @     mcasp@0          ti,dra7-mcasp-audio         E        HC`            Ampu dat                                     tx rx                                     tx rx           q   \         \             xfck ahclkx        	  disabled            I           target-module@70000          ti,sysc-dra7-mcasp ti,sysc          E                 	  Arev sysc            K                  q   \  l       \  l           xfck ahclkx                                              HC HC  @     mcasp@0          ti,dra7-mcasp-audio         E        HC            Ampu dat                                     tx rx                                     tx rx           q   \  l       \  l           xfck ahclkx        	  disabled            I           target-module@74000          ti,sysc-dra7-mcasp ti,sysc          E @     @         	  Arev sysc            K                  q   \         \             xfck ahclkx                                        @     HD HD  @     mcasp@0          ti,dra7-mcasp-audio         E        HD            Ampu dat                                     tx rx                                     tx rx           q   \         \             xfck ahclkx        	  disabled            I           target-module@78000          ti,sysc-dra7-mcasp ti,sysc          E               	  Arev sysc            K                  q   \         \             xfck ahclkx                                             HE  HE   @     mcasp@0          ti,dra7-mcasp-audio         E        HE             Ampu dat                                     tx rx                                     tx rx           q   \         \             xfck ahclkx        	  disabled            I           target-module@7c000          ti,sysc-dra7-mcasp ti,sysc          E               	  Arev sysc            K                  q   \         \             xfck ahclkx                                             HE@ HE@  @     mcasp@0          ti,dra7-mcasp-audio         E        HE@            Ampu dat                                     tx rx                                     tx rx           q   \         \             xfck ahclkx        	  disabled            I           target-module@80000          ti,sysc-omap4 ti,sysc           E              Arev         q   \              xfck                                                can@0            ti,dra7-d_can           E                     X                             q         	  disabled            I           target-module@84000          ti,sysc-omap4-simple ti,sysc            E R     R    R           Arev sysc syss           0            =               K               Y           q                   xfck                                       @   @          Z   switch@0          #   ti,dra7-cpsw-switch ti,cpsw-switch          E      @                   @         q           xfck                                             okay          0        N         O         P         Q           rx_thresh rx tx misc            I     ethernet-ports                               port@1          E           port1                                                    "rgmii-rxid          +           I        port@2          E           port2                                                    "rgmii-rxid          +           I           mdio@1000            ti,cpsw-mdio ti,davinci_mdio            q           xfck                                   = B@        E              I     ethernet-phy@1          E           I         ethernet-phy@2          E           F   d        I            cpts            q                  xcpts                      interconnect@48800000            ti,dra7-l4-per3 simple-pm-bus                      q                   xfck       (  EH     H    H    H    H            Aap la ia0 ia1 ia2                                        H              I     segment@0            simple-pm-bus                                                                                                            0  0     @  @     P  P     `  `     p  p                                                                                                                                                                                                                                    0  0     @  @     P  P     `  `     p  p                                                                                      0  0     @  @     P  P     `  `     p  p                                 @  @     P  P                                            0  0                       `  `     p  p                        @   @      P   P              
   
                                                                                                  0   0       target-module@2000           ti,sysc-omap4 ti,sysc           E                   	  Arev sysc            0           K                  q                  xfck                                                mailbox@0            ti,omap4-mailbox            E             0        {         |         }         ~                                          	  disabled            I           target-module@4000           ti,sysc       	  disabled                                           @          target-module@a000           ti,sysc       	  disabled                                                     target-module@10000          ti,sysc       	  disabled                                                     target-module@16000          ti,sysc       	  disabled                                          `          target-module@1c000          ti,sysc       	  disabled                                                    target-module@1e000          ti,sysc       	  disabled                                                    target-module@20000          ti,sysc-omap4-timer ti,sysc         E                 	  Arev sysc            0           K                     q                  xfck                                               timer@0          ti,omap5430-timer           E               q                    xfck timer_sys_ck                   $           I            target-module@22000          ti,sysc-omap4-timer ti,sysc         E                 	  Arev sysc            0           K                     q                  xfck                                               timer@0          ti,omap5430-timer           E               q                    xfck timer_sys_ck                   %           I            target-module@24000          ti,sysc-omap4-timer ti,sysc         E @     @         	  Arev sysc            0           K                     q                  xfck                                       @       timer@0          ti,omap5430-timer           E               q                    xfck timer_sys_ck                   &           I            target-module@26000          ti,sysc-omap4-timer ti,sysc         E `     `         	  Arev sysc            0           K                     q                   xfck                                       `       timer@0          ti,omap5430-timer           E               q                     xfck timer_sys_ck                   '           I            target-module@28000          ti,sysc-omap4-timer ti,sysc         E               	  Arev sysc            0           K                     q                  xfck                                              timer@0          ti,omap5430-timer           E               q                    xfck timer_sys_ck                  S            P        I            target-module@2a000          ti,sysc-omap4-timer ti,sysc         E               	  Arev sysc            0           K                     q                  xfck                                              timer@0          ti,omap5430-timer           E               q                    xfck timer_sys_ck                  T            P        I           target-module@2c000          ti,sysc-omap4-timer ti,sysc         E               	  Arev sysc            0           K                     q                  xfck                                                    F         Z        I     timer@0          ti,omap5430-timer           E               q                    xfck timer_sys_ck                  U            P                                    I           target-module@2e000          ti,sysc-omap4-timer ti,sysc         E               	  Arev sysc            0           K                     q                 xfck                                                    F         Z        I     timer@0          ti,omap5430-timer           E               q                   xfck timer_sys_ck                  V            P                                   I           target-module@38000          ti,sysc-omap4-simple ti,sysc            E t    x         	  Arev sysc            K                     q      $            xfck                                                   I     rtc@0            ti,am3352-rtc           E                                           q   U        I           target-module@3a000          ti,sysc-omap4 ti,sysc           E               	  Arev sysc            0           K                  q      (            xfck                                              mailbox@0            ti,omap4-mailbox            E             0                                                                                 	  disabled            I           target-module@3c000          ti,sysc-omap4 ti,sysc           E               	  Arev sysc            0           K                  q      0            xfck                                              mailbox@0            ti,omap4-mailbox            E             0                                                                                 	  disabled            I           target-module@3e000          ti,sysc-omap4 ti,sysc           E               	  Arev sysc            0           K                  q      8            xfck                                              mailbox@0            ti,omap4-mailbox            E             0                                                                                 	  disabled            I           target-module@40000          ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           K                  q      @            xfck                                               mailbox@0            ti,omap4-mailbox            E             0                                                                                   okay            I      mbox-ipu1-ipc3x         ]                 h                 okay            I         mbox-dsp1-ipc3x         ]                 h                 okay            I               target-module@42000          ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           K                  q      H            xfck                                               mailbox@0            ti,omap4-mailbox            E             0                                                                                   okay            I      mbox-ipu2-ipc3x         ]                 h                 okay            I         mbox-dsp2-ipc3x         ]                 h                 okay            I               target-module@44000          ti,sysc-omap4 ti,sysc           E @     @         	  Arev sysc            0           K                  q      P            xfck                                       @       mailbox@0            ti,omap4-mailbox            E             0                                                                             	  disabled            I           target-module@46000          ti,sysc-omap4 ti,sysc           E `     `         	  Arev sysc            0           K                  q      X            xfck                                       `       mailbox@0            ti,omap4-mailbox            E             0                                                                             	  disabled            I           target-module@48000          ti,sysc       	  disabled                                                    target-module@4a000          ti,sysc       	  disabled                                                    target-module@4c000          ti,sysc       	  disabled                                                    target-module@4e000          ti,sysc       	  disabled                                                    target-module@50000          ti,sysc       	  disabled                                                     target-module@52000          ti,sysc       	  disabled                                                     target-module@54000          ti,sysc       	  disabled                                          @          target-module@56000          ti,sysc       	  disabled                                          `          target-module@58000          ti,sysc       	  disabled                                                    target-module@5a000          ti,sysc       	  disabled                                                    target-module@5c000          ti,sysc       	  disabled                                                    target-module@5e000          ti,sysc-omap4 ti,sysc           E               	  Arev sysc            0           K                  q      `            xfck                                              mailbox@0            ti,omap4-mailbox            E             0        	         
                                                            	  disabled            I           target-module@60000          ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           K                  q      h            xfck                                               mailbox@0            ti,omap4-mailbox            E             0                                                                             	  disabled            I           target-module@62000          ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           K                  q      p            xfck                                               mailbox@0            ti,omap4-mailbox            E             0                                                                             	  disabled            I           target-module@64000          ti,sysc-omap4 ti,sysc           E @     @         	  Arev sysc            0           K                  q      x            xfck                                       @       mailbox@0            ti,omap4-mailbox            E             0                                                                             	  disabled            I           target-module@80000          ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           =                     K                     q   _               xfck                                               omap_dwc3_1@0            ti,dwc3         E                      H                                    s                              I     usb@10000         
   snps,dwc3           E    p       $         G          G          H           peripheral host otg                       usb2-phy usb3-phy           }super-speed         host                              I              target-module@c0000          ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           =                     K                     q   _                xfck                                               omap_dwc3_2@0            ti,dwc3         E                      W                                    s                                         I     usb@10000         
   snps,dwc3           E    p       $         I          I          W           peripheral host otg                  	  usb2-phy            }high-speed          peripheral                                     I              target-module@100000             ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           =                     K                     q   _   (            xfck                                                  	  disabled            I     omap_dwc3_3@0            ti,dwc3         E                     X                                    s                            	  disabled            I     usb@10000         
   snps,dwc3           E    p       $         X          X         X           peripheral host otg         }high-speed          otg                           I              target-module@170000             ti,sysc-omap4 ti,sysc           E             Asysc            =                  K                  q                   xfck                                                  	  disabled          target-module@190000             ti,sysc-omap4 ti,sysc           E             Asysc            =                  K                  q                  xfck                                                  	  disabled          target-module@1b0000             ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            =                  K                  q                  xfck                                                  	  disabled          target-module@1d0010             ti,sysc-omap4 ti,sysc           E             Asysc            =               K                             q                  xfck                                               vpe@0            ti,dra7-vpe          E               W                  Avpe_top sc csc vpdma                  b           I           target-module@140000             ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            0           =                     K                     q   _   0            xfck                                                  	  disabled            I     omap_dwc3_4@0            ti,dwc3         E                     Z                                    s                  	  disabled            I     usb@10000         
   snps,dwc3           E    p       $        Y         Y         Z           peripheral host otg         }high-speed          otg         I                    target-module@51000000           ti,sysc-omap4 ti,sysc              h           h            rstctrl       $  q   e           e       	   e       
        xfck phy-clk phy-clk-div                                  Q   Q     0                     "        I     pcie@51000000           EQ       Q     L               Arc_dbics ti_conf config                                                              Qpci       0               0                0  0                             4           	           	                     
  pcie-phy0           	!   d           	4                     `  	G                                                                                            	U                 okay             ti,dra746-pcie-rc ti,dra7-pcie          K                 I     interrupt-controller                                   4           I            pcie_ep@51000000             EQ      (Q     LQ     (            &  Aep_dbics ti_conf ep_dbics2 addr_space                             	           	p           	                    
  pcie-phy0           	U                 	!   d         	  disabled          "   ti,dra746-pcie-ep ti,dra7-pcie-ep           I           target-module@51800000           ti,sysc-omap4 ti,sysc         $  q   e          e      	   e      
        xfck phy-clk phy-clk-div            h           h           rstctrl                                  Q  Q    0 0   0               "      	  disabled            I     pcie@51800000           EQ      Q    L0              Arc_dbics ti_conf config               c         d                                    Qpci       0             0 0               00 00                             4           	           	                    
  pcie-phy0           	4                     `  	G                                                                                            	U                  ti,dra746-pcie-rc ti,dra7-pcie          I     interrupt-controller                                   4           I               ocmcram@40300000          
   mmio-sram           E@0                 @0                                      I     sram-hs@0            ti,secure-ram           E                 ocmcram@40400000          	  disabled          
   mmio-sram           E@@                 @@                                      I        ocmcram@40500000          	  disabled          
   mmio-sram           E@P                 @P                                      I        bandgap@4a0021e0          0  EJ !   J #,   J #   ,J #   <J %d   J %t   P         ti,dra752-bandgap                  y           |           I         dsp_system@40d00000          syscon          E@             I         padconf@4844a000             ti,dra7-iodelay         EHD                                                I     mmc1_iodelay_ddr_rev11_conf         	    <             $      X  (          ,   7      0     x  4          8          <      <  @          D          H      <  L          P          T          X          \                I        mmc1_iodelay_ddr50_rev20_conf           	    4  J           $        (          ,          0        4          8         <         @          D          H        L          P          T          X          \                I        mmc1_iodelay_sdr104_rev11_conf          	     '     (          ,         4          8          @          D         L          P          X          \                I        mmc1_iodelay_sdr104_rev20_conf          	     X    (          ,          4          8         @          D          L          P          X          \                I        mmc2_iodelay_hs200_rev11_conf           	    m  X    ,          X             ,  X               X     <        <        X                X     x          X             5  X      <      d    X  h               I        mmc2_iodelay_hs200_rev20_conf           	                              I                 s        y         /              m                                                                 .      d        h   L            I        mmc2_iodelay_ddr_3_3v_rev11_conf         \  	         x                       	  h                            x                            x                              o                                                         "             x               x         x                          `          d          h               I         mmc2_iodelay_ddr_1_8v_rev11_conf         \  	                                                                <                            <                          h    o            x                                             "             <               x         y   <                       `          d          h               I        mmc3_iodelay_manual1_conf           	  x                                                                                                                                                                        I        mmc4_iodelay_ds_rev11_conf          	  @          H          L   `      P          T          p  F      t          x          |                              1                            L                                I        mmc4_iodelay_ds_rev20_conf          	  @          H          L  3      P          T          p        t          x          |  e                                                        C                                I        mmc4_iodelay_sdr12_hs_sdr25_rev11_conf          	  @          H  
[      L  $      P          T          p  y      t          x          |                              c                                                            I        mmc4_iodelay_sdr12_hs_sdr25_rev20_conf          	  @          H  {      L  *      P          T          p  u      t          x          |     @                                                   |   ,                            I           target-module@43300000           ti,sysc-omap4 ti,sysc           EC0     C0          	  Arev sysc            =                  K                  q   	   P            xfck                                      C0        dma@0            ti,edma3-tpcc           E             	  Aedma3_cc          $        i         h         g         '  edma3_ccint edma3_mperr edma3_ccerrint          9   @        .           	                     I            target-module@43400000           ti,sysc-omap4 ti,sysc           EC@     C@          	  Arev sysc            =                  K                  q   	   X            xfck                                      C@        dma@0            ti,edma3-tptc           E                     r           edma3_tcerrint          I            target-module@43500000           ti,sysc-omap4 ti,sysc           ECP     CP          	  Arev sysc            =                  K                  q   	   `            xfck                                      CP        dma@0            ti,edma3-tptc           E                     s           edma3_tcerrint          I            target-module@4e000000           ti,sysc-omap2 ti,sysc           EN      N           	  Arev sysc            K                      N                                  dmm@0            ti,omap5-dmm            E                      l            ipu@58820000             ti,dra7-ipu         EX             Al2ram           	           okay                                 q   A                	dra7-ipu1-fw.xem4           	              	           	              	           I        ipu@55020000             ti,dra7-ipu         EU             Al2ram           	           okay                                 q                   	dra7-ipu2-fw.xem4           	              	           	              	           I        dsp@40800000             ti,dra7-dsp         E@    @     @             Al2ram l1pram l1dram         	     \   
        	              okay                           q                   	dra7-dsp1-fw.xe66           	              	           	           	           I        target-module@40d01000           ti,sysc-omap2 ti,sysc           E@    @   @           Arev sysc syss           K                  0          q                   xfck                       rstctrl             @                                mmu@0            ti,dra7-dsp-iommu           E                                 	            
               I            target-module@40d02000           ti,sysc-omap2 ti,sysc           E@     @    @            Arev sysc syss           K                  0          q                   xfck                       rstctrl             @                                 mmu@0            ti,dra7-dsp-iommu           E                                 	            
              I            target-module@58882000           ti,sysc-omap2 ti,sysc           EX     X    X            Arev sysc syss           K                  0          q   A                xfck                       rstctrl                                      X        mmu@0            ti,dra7-iommu           E                                	             
        I            target-module@55082000           ti,sysc-omap2 ti,sysc           EU     U    U            Arev sysc syss           K                  0          q                   xfck                       rstctrl                                      U        mmu@0            ti,dra7-iommu           E                                	             
        I            regulator-abb-mpu@4ae07ddc        
   ti,abb-v3           Kabb_mpu                                    q           
2   2        
C         (  EJ}   J}   J`   J ;    JX         D  Asetup-address control-address int-address efuse-address ldo-address         
S           
l           
         H  
 ,                  @                 v                        I         regulator-abb-ivahd@4ae07e34          
   ti,abb-v3         
  Kabb_ivahd                                      q           
2   2        
C         (  EJ~4   J~$   J`   J %   J $p         D  Asetup-address control-address int-address efuse-address ldo-address         
S@           
l           
         H  
                   0                                         I         regulator-abb-dspeve@4ae07e30         
   ti,abb-v3           Kabb_dspeve                                     q           
2   2        
C         (  EJ~0   J~    J`   J %   J $l         D  Asetup-address control-address int-address efuse-address ldo-address         
S            
l           
         H  
                   0                                         I        regulator-abb-gpu@4ae07de4        
   ti,abb-v3           Kabb_gpu                                    q           
2   2        
C         (  EJ}   J}   J`   J ;   JT         D  Asetup-address control-address int-address efuse-address ldo-address         
S           
l           
         H  
                   v                                          I        target-module@4b300000           ti,sysc-omap4 ti,sysc           EK0     K0          	  Arev sysc            K                     q   \  ,            xfck                                      K0     \   \         spi@0            ti,dra7xxx-qspi         E       \              Aqspi_base qspi_mmap         
     X                                  q   \  ,           xfck                          W         	  disabled            I           target-module@50000000           ti,sysc-omap2 ti,sysc           EP      P     P             Arev sysc syss           K                  Y           q   	               xfck                                  P   P              @      gpmc@50000000            ti,am3352-gpmc          EP     |                                            rxtx            
           
                                             4            *        :         	  disabled            I           target-module@56000000           ti,sysc-omap4 ti,sysc           EV     V          	  Arev sysc            =                  K                     q                   xfck                                      V         gpu@0         !   ti,am5728-gpu img,powervr-sgx544            E                                  crossbar@4a002a48            ti,irq-crossbar         EJ *H  0                  &           4           
           
          
                                                
                 #            I         target-module@58000000           ti,sysc-omap2 ti,sysc           EX      X           	  Arev syss            Y         0  q                     	          
                  xfck hdmi_clk sys_clk tv_clk                                      X         dss@0            ti,dra7-dss         okay            4     8                                                  (  E         @T     C       T                (  Adss pll1_clkctrl pll1 pll2_clkctrl pll2       $  q                                      xfck video1_clk video2_clk           D           I     target-module@1000           ti,sysc-omap2 ti,sysc           E                        Arev sysc syss           K                  =                  0          Y           q                  xfck                                               dispc@0          ti,dra7-dispc           E                                 q                  xfck         V     4         target-module@40000          ti,sysc-omap4 ti,sysc           E                 	  Arev sysc            K                     0           q          	                  xfck dss_clk                                               encoder@0            ti,dra7-hdmi             E                                Awp pll phy core                `           okay            q          	          
        xfck sys_clk               L      	  audio_tx            a           I     port       endpoint            m           I                       target-module@59000000           ti,sysc-omap4 ti,sysc           EY              Arev         q                  xfck                                      Y         gpu@0            vivante,gc          E                      x           q                  xcore            I           target-module@4b500000           ti,sysc-omap2 ti,sysc           EKP    KP    KP            Arev sysc syss           0           K                     Y           q                   xfck                                      KP             I     aes@0            ti,omap4-aes            E                      P                 o          n            tx rx           q           xfck         I  	         target-module@4b700000           ti,sysc-omap2 ti,sysc           EKp    Kp    Kp            Arev sysc syss           0           K                     Y           q                  xfck                                      Kp             I  
   aes@0            ti,omap4-aes            E                      ;                 r          q            tx rx           q           xfck         I           target-module@4b101000           ti,sysc-omap3-sham ti,sysc          EK    K   K           Arev sysc syss           0           K                  Y           q      (            xfck                                      K            I     sham@0           ti,omap5-sham           E                      .                 w            rx          q           xfck         I           target-module@42701000           ti,sysc-omap3-sham ti,sysc          EBp    Bp   Bp           Arev sysc syss           0           K                  Y           q      X            xfck                                      Bp            I     sham@0           ti,omap5-sham           E                                                   rx          q           xfck         I           target-module@5a000000           ti,sysc-omap4 ti,sysc           EZ    Z         	  Arev sysc            =                  K                                           rstctrl         q                   xfck                                  Z   Z      [   [              I     iva       	   ti,ivahd             opp-supply@4a003b20          ti,omap5-opp-supply         EJ ;            } ,     @    v            `        I        dsp_system@41500000          syscon          EAP             I         target-module@41501000           ti,sysc-omap2 ti,sysc           EAP    AP   AP           Arev sysc syss           K                  0          q                   xfck                       rstctrl             AP                                mmu@0            ti,dra7-dsp-iommu           E                                 	            
               I            target-module@41502000           ti,sysc-omap2 ti,sysc           EAP     AP    AP            Arev sysc syss           K                  0          q                   xfck                       rstctrl             AP                                 mmu@0            ti,dra7-dsp-iommu           E                                 	            
              I            dsp@41000000             ti,dra7-dsp         EA     A`     Ap             Al2ram l1pram l1dram         	     `   
        	              okay                           q                   	dra7-dsp2-fw.xe66           	              	           	           	           I        target-module@4b226000           ti,sysc-pruss ti,sysc           EK"`    K"`         	  Arev sysc            0   0        =                  K                  q   \               xfck                                      K              I     pruss@0          ti,am5728-pruss         E                                                 I     memories@0          E                              Adram0 dram1 shrdram2            I        cfg@26000            ti,pruss-cfg syscon         E `                                           `             I     clocks                               iepclk-mux@30           E   0                    q              I              mii-rt@32000             ti,pruss-mii syscon         E      X        I        interrupt-controller@20000           ti,pruss-intc           E                        4         `                                                                                        X  host_intr0 host_intr1 host_intr2 host_intr3 host_intr4 host_intr5 host_intr6 host_intr7         I        pru@34000            ti,am5728-pru           E @   0        $            Airam control debug          	am57xx-pru1_0-fw            I        pru@38000            ti,am5728-pru           E    0  @     D            Airam control debug          	am57xx-pru1_1-fw            I        mdio@32400           ti,davinci_mdio                                   q           xfck         = B@        E $          	  disabled            I              target-module@4b2a6000           ti,sysc-pruss ti,sysc           EK*`    K*`         	  Arev sysc            0   0        =                  K                  q   \               xfck                                      K(             I     pruss@0          ti,am5728-pruss         E                                                 I     memories@0          E                              Adram0 dram1 shrdram2            I        cfg@26000            ti,pruss-cfg syscon         E `                                           `             I      clocks                               iepclk-mux@30           E   0                    q              I  !            mii-rt@32000             ti,pruss-mii syscon         E      X        I  "      interrupt-controller@20000           ti,pruss-intc           E                        4         `                                                                                        X  host_intr0 host_intr1 host_intr2 host_intr3 host_intr4 host_intr5 host_intr6 host_intr7         I  #      pru@34000            ti,am5728-pru           E @   0        $            Airam control debug          	am57xx-pru2_0-fw            I  $      pru@38000            ti,am5728-pru           E    0  @     D            Airam control debug          	am57xx-pru2_1-fw            I  %      mdio@32400           ti,davinci_mdio                                   q           xfck         = B@        E $          	  disabled            I  &               thermal-zones           I  '   cpu_thermal                                                           I  (   trips           I  )   cpu_alert            8                  Xpassive         I         cpu_crit             _                	  Xcritical            I  *      cpu_alert1            P                  Xactive          I            cooling-maps            I  +   map0                                map1                                      gpu_thermal                                                          I  ,   trips      gpu_crit             _                	  Xcritical            I  -            core_thermal                                                             I  .   trips      core_crit            _                	  Xcritical            I  /            dspeve_thermal                                                           I  0   trips      dspeve_crit          _                	  Xcritical            I  1            iva_thermal                                                          I  2   trips      iva_crit             _                	  Xcritical            I  3            board_thermal                                              I  4   trips           I  5   board_alert           @                  Xactive          I         board_crit           (                  	  Xcritical            I  6         cooling-maps            I  7   map0                                         pmu          arm,cortex-a15-pmu           &                                     memory@0            Qmemory          E                    fixedregulator-main_12v0             regulator-fixed       
  Kmain_12v0           Z          r                    *        I         fixedregulator-evm_5v0           regulator-fixed         Kevm_5v0         Z LK@        r LK@                             *        I  8      reserved-memory                                      ipu2-memory@95800000             shared-dma-pool         E                     !        okay            I         dsp1-memory@99000000             shared-dma-pool         E                       !        okay            I         ipu1-memory@9d000000             shared-dma-pool         E                       !        okay            I         dsp2-memory@9f000000             shared-dma-pool         E                       !        okay            I            fixedregulator-vdd_3v3           regulator-fixed         Kvdd_3v3                    Z 2Z        r 2Z        I         fixedregulator-aic_dvdd          regulator-fixed         Kaic_dvdd_fixed                     Z w@        r w@        I         fixedregulator-vtt           regulator-fixed       
  Kvtt_fixed                     Z 2Z        r 2Z                  *         *        w                  I  9      leds          
   gpio-leds      led0            beagle-x15:usr0         K      	          
  =heartbeat           Soff       led1            beagle-x15:usr1         K                  =cpu0            Soff       led2            beagle-x15:usr2         K                  =mmc0            Soff       led3            beagle-x15:usr3         K                  =disk-activity           Soff          gpio_fan          	   gpio-fan            K                 a          2                      I         connector            hdmi-connector          hdmi            Xa           I  :   port       endpoint            m          I              encoder          ti,tpd12s015          $  K      
                                I  ;   ports                                port@0          E       endpoint            m          I            port@1          E      endpoint            m          I                 sound0           simple-audio-card           tBeagleBoard-X15         Line Line Out Line Line In        :  Line Out LLOUT Line Out RLOUT MIC2L Line In MIC2R Line In           dsp_b                                        I  <   simple-audio-card,cpu           >        simple-audio-card,codec         >          q  	        I           __symbols__         H/interrupt-controller@48211000          L/interrupt-controller@48281000          V/cpus/cpu@0         [/opp-table          j/ocp            n/ocp/interconnect@4a000000        >  u/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0         I  y/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0          ]  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/pbias_regulator@e00          m  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/pbias_regulator@e00/pbias_mmc_omap5          Z  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/phy-gmii-sel@554         P  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks       h  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-dss-deshdcp-0@558       k  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-ehrpwm0-tbclk-20@558        k  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-ehrpwm1-tbclk-21@558        k  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-ehrpwm2-tbclk-22@558        b  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-sys-32k@6c4         J  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400         \  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1-default-pins       Z  "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1-sdr12-pins         W  2/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1-hs-pins        Z  ?/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1-sdr25-pins         Z  O/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1-sdr50-pins         Z  _/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1-ddr50-pins         [  o/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1-sdr104-pins        \  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2-default-pins       W  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2-hs-pins        c  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2-ddr-3-3v-rev11-pins        c  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2-ddr-1-8v-rev11-pins        ^  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2-ddr-rev20-pins         Z  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2-hs200-pins         \  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc4-default-pins       W  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc4-hs-pins        \  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3-default-pins       W  &/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3-hs-pins        Z  3/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3-sdr12-pins         Z  C/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3-sdr25-pins         Z  S/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3-sdr50-pins         Z  c/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc4-sdr12-pins         Z  s/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc4-sdr25-pins         L  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@1c04       L  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@1c24       M  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/dma-router@b78          M  /ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/dma-router@c78          F  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0         M  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks          ^  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-atl-clkin0         ^  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-atl-clkin1         ^  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-atl-clkin2         ^  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-atl-clkin3         ^  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-hdmi-clkin         ]  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-mlb-clkin          ^  !/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-mlbp-clkin         `  //ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-pciesref-acs       ^  C/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-ref-clkin0         ^  Q/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-ref-clkin1         ^  _/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-ref-clkin2         ^  m/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-ref-clkin3         X  {/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-rmii       `  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-sdvenc-clkin       f  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-secure-32k-clk-src         e  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-sys-clk32-crystal          d  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-sys-clk32-pseudo       a  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-12000000          a  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-13000000          a  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-16800000          a  	/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-19200000          a  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-20000000          a  +/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-26000000          a  </ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-27000000          a  M/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-38400000          ^  ^/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-sys-clkin2         a  i/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-usb-otg-clkin          `  z/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-clkin       c  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-m2-clkin        `  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-clkin       c  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-m2-clkin        W  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@1e0        _  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-abe-x2        g  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-abe-m2x2-8@1f0        [  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-abe@108        e  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-abe-m2-8@1f0          g  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-abe-m3x2-8@1f4        `  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@12c/clock@23       W  &/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@120        `  3/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-x2       i  C/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h12x2-8@13c          g  V/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-mpu-dpll-hs-clk-div        W  j/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@160        e  v/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-mpu-m2-8@170          `  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-mpu-dclk-div       g  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dsp-dpll-hs-clk-div        `  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@240/clock@23       W  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@234        e  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-dsp-m2-8@244          g  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-iva-dpll-hs-clk-div        `  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@1ac/clock@23       W  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@1a0        e  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-iva-m2-8@1b0          \  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-iva-dclk       `  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@2e4/clock@23       W  ,/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@2d8        e  8/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gpu-m2-8@2e8          f  G/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-m2-8@130         j  W/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-core-dpll-out-dclk-div         `  n/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@21c/clock@23       W  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@210        e  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-ddr-m2-8@220          `  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@2b4/clock@23       W  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@2a8        f  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-m2-8@2b8         c  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-dclk-div        c  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-dclk-div        a  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-hdmi-dclk-div          g  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-per-dpll-hs-clk-div        g  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-usb-dpll-hs-clk-div        g  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-eve-dpll-hs-clk-div        `  3/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@290/clock@23       W  D/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@284        e  P/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-eve-m2-8@294          `  _/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-eve-dclk-div       i  l/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h13x2-8@140          i  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h14x2-8@144          i  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h22x2-8@154          i  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h23x2-8@158          i  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h24x2-8@15c          _  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-ddr-x2        h  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-ddr-h11x2-8@228       _  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-dsp-x2        g  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-dsp-m3x2-8@248        `  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-x2       i  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-h11x2-8@2c0          i  //ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-h12x2-8@2c4          i  B/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-h13x2-8@2c8          h  U/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-m3x2-8@2bc       b  g/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-gmii-m-clk-div         a  v/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-hdmi-clk2-div          \  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-hdmi-div       _  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@100/clock@4        c  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-l4-root-clk-div        c  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-clk2-div        ^  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-div         c  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-clk2-div        ^  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-div         Y  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dummy          S  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clockdomains        P  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@300       Y  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@300/clock@20          P   /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@400       Y  (/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@400/clock@20          P  5/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@500       Y  </ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@500/clock@20          Y  I/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@500/clock@50          P  U/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@600       Y  ]/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@600/clock@20          P  j/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@700       Y  q/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@700/clock@20          P  }/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@760       X  /ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@760/clock@0       B  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0         I  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks          S  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@200        i  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-pcie-ref-m2ldo-8@210          o  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-apll-pcie-in-clk-mux-7@4ae06118        S  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@21c        n  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-optfclk-pciephy-div-8@4a00821c         c  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-apll-pcie-clkvcoldo        g  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-apll-pcie-clkvcoldo-div        \  1/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-apll-pcie-m2       \  A/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@14c/clock@23       S  R/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@140        a  ^/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-m2-8@150          e  m/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-96m-aon-dclk-div          \  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@18c/clock@23       S  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@180        a  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-usb-m2-8@190          f  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-pcie-ref-m2-8@210         [  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-x2        d  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-h11x2-8@158       d  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-h12x2-8@15c       d  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-h13x2-8@160       d  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-h14x2-8@164       c  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-m2x2-8@150        b  +/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-usb-clkdcoldo         Y  >/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-128m          ]  L/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-12m-fclk          X  Z/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-24m       ]  g/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-48m-fclk          ]  u/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-96m-fclk          ^  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-l3init-60m@104         ]  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-clkout2-8@6b0          g  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-l3init-960m-gfclk-8@6c0        o  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-usb-phy1-always-on-clk32k-8@640        o  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-usb-phy2-always-on-clk32k-8@688        o  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-usb-phy3-always-on-clk32k-8@698        i  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-gpu-core-gclk-mux-24@1220          h  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-gpu-hyd-gclk-mux-26@1220       j  "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-l3instr-ts-gclk-div-24@e50         e  6/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-vip1-gclk-mux-24@1020          e  D/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-vip2-gclk-mux-24@1028          e  R/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-vip3-gclk-mux-24@1030          O  `/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clockdomains        c  u/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clockdomains/clock-coreaon-clkdm        L  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@600       U  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@600/clock@20          L  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@700       U  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@700/clock@20          L  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@900       U  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@900/clock@20          L  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@a00       U  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@a00/clock@20          L  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@b00       U  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@b00/clock@20          L  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@c00       T  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@c00/clock@0       L  	/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@d00       U  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@d00/clock@20          L   /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@e00       U  +/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@e00/clock@20          L  ;/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@f00       U  B/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@f00/clock@20          M  N/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1000          V  U/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1000/clock@20         M  a/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1100          V  h/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1100/clock@20         M  t/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1200          V  {/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1200/clock@20         M  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1300          V  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1300/clock@20         V  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1300/clock@b0         V  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1300/clock@d0         M  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700          V  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700/clock@28         W  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700/clock@1a0        U  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700/clock@c          V  /ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700/clock@14         J  /ocp/interconnect@4a000000/segment@0/target-module@56000/dma-controller@0         L  /ocp/interconnect@4a000000/segment@0/target-module@80000/ocp2scp@0/phy@4000       L  /ocp/interconnect@4a000000/segment@0/target-module@80000/ocp2scp@0/phy@5000       L  /ocp/interconnect@4a000000/segment@0/target-module@80000/ocp2scp@0/phy@4400       P   /ocp/interconnect@4a000000/segment@0/target-module@90000/ocp2scp@0/pciephy@4000       P  */ocp/interconnect@4a000000/segment@0/target-module@90000/ocp2scp@0/pciephy@5000       L  4/ocp/interconnect@4a000000/segment@0/target-module@90000/ocp2scp@0/phy@6000       C  =/ocp/interconnect@4a000000/segment@0/target-module@f4000/mailbox@0        D  F/ocp/interconnect@4a000000/segment@0/target-module@f6000/spinlock@0       E  Q/ocp/interconnect@4a000000/segment@100000/target-module@40000/sata@0            V/ocp/interconnect@4ae00000        B  ^/ocp/interconnect@4ae00000/segment@0/target-module@4000/counter@0         >  i/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0         E  m/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks          Z  x/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-sys-clkin1@110         W  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock@118/clock@0        g  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-dpll-bypass-clk-mux@114        `  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-dpll-clk-mux@10c       W  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-24m@11c        T  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-aess@178       ]  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-giclk-div@174          ^  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-lp-clk-div@1d8         _  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-sys-clk-div@120        ]  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-adc-gfclk-mux@1dc          a  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-sys-clk1-dclk-div@1c8          a  %/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-sys-clk2-dclk-div@1cc          c  7/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-per-abe-x1-dclk-div@1bc        W  K/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock@18c/clock@0        X  X/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-gpu-dclk@1a0       a  a/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-emif-phy-dclk-div@190          b  s/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-gmac-250m-dclk-div@19c         U  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-gmac-main          d  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-l3init-480m-dclk-div@1ac       `  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-usb-otg-dclk-div@184       ]  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-sata-dclk-div@1c0          ^  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-pcie2-dclk-div@1b8         ]  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-pcie-dclk-div@1b4          \  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-emu-dclk-div@194       c  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-secure-32k-dclk-div@1c4        b  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-clkoutmux0-clk-mux@158         b  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-clkoutmux1-clk-mux@15c         b  ,/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-clkoutmux2-clk-mux@160         c  ?/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-custefuse-sys-gfclk-div        S  W/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-eve@180        a  _/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-hdmi-dpll-clk-mux@164          S  q/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-mlb@134        T  y/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-mlbp@130       e  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-per-abe-x1-gfclk2-div@138          a  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-timer-sys-clk-div@144          c  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-video1-dpll-clk-mux@168        c  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-video2-dpll-clk-mux@16c        `  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-wkupaon-iclk-mux@108       K  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clockdomains        I  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clock@1800          R  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clock@1800/clock@20         F  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@300         F  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@400         F   /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@500         F  (/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@628         F  4/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@700         F  =/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@f00         G  E/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1000        G  M/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1100        G  U/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1200        G  ]/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1300        G  h/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1400        G  r/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1600        G  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1724        G  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1b00        G  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1b40        G  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1b80        G  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1bc0        G  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1c00        G  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1c60        G  /ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1c80        C  /ocp/interconnect@4ae00000/segment@0/target-module@c000/scm_conf@0        @  /ocp/interconnect@4ae00000/segment@10000/target-module@0/gpio@0       B  /ocp/interconnect@4ae00000/segment@10000/target-module@4000/wdt@0         <  /ocp/interconnect@4ae00000/segment@10000/target-module@8000       D  /ocp/interconnect@4ae00000/segment@10000/target-module@8000/timer@0       A  /ocp/interconnect@4ae00000/segment@20000/target-module@0/timer@0          E  /ocp/interconnect@4ae00000/segment@20000/target-module@b000/serial@0          B  /ocp/interconnect@4ae00000/segment@30000/target-module@c000/can@0           /ocp/interconnect@48000000        B  /ocp/interconnect@48000000/segment@0/target-module@20000/serial@0         A  /ocp/interconnect@48000000/segment@0/target-module@32000/timer@0          9  /ocp/interconnect@48000000/segment@0/target-module@34000          A  */ocp/interconnect@48000000/segment@0/target-module@34000/timer@0          9  1/ocp/interconnect@48000000/segment@0/target-module@36000          A  ?/ocp/interconnect@48000000/segment@0/target-module@36000/timer@0          A  F/ocp/interconnect@48000000/segment@0/target-module@3e000/timer@0          9  M/ocp/interconnect@48000000/segment@0/target-module@51000          @  Z/ocp/interconnect@48000000/segment@0/target-module@51000/gpio@0       @  `/ocp/interconnect@48000000/segment@0/target-module@53000/gpio@0       9  f/ocp/interconnect@48000000/segment@0/target-module@55000          @  s/ocp/interconnect@48000000/segment@0/target-module@55000/gpio@0       9  y/ocp/interconnect@48000000/segment@0/target-module@57000          @  /ocp/interconnect@48000000/segment@0/target-module@57000/gpio@0       @  /ocp/interconnect@48000000/segment@0/target-module@59000/gpio@0       @  /ocp/interconnect@48000000/segment@0/target-module@5b000/gpio@0       @  /ocp/interconnect@48000000/segment@0/target-module@5d000/gpio@0       ?   X/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0        F  /ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0/rtc@6f         B  /ocp/interconnect@48000000/segment@0/target-module@66000/serial@0         B  /ocp/interconnect@48000000/segment@0/target-module@68000/serial@0         B  /ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0         B  /ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0         B  /ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0         ?   N/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0        L  /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58       m  /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/smps12          l  /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/smps3       m  /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/smps45          l  /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/smps6       l  /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/smps8       k   /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/ldo1        k   /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/ldo2        k   /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/ldo3        k   /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/ldo4        k   &/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/ldo9        l   //ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/ldoln       m   9/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/ldousb          m   D/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pmic/regulators/regen1          Z   K/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_rtc         a   Y/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_pwr_button          [   n/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_gpio        Z   }/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_usb         I   /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tmp102@48          P   /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tlv320aic3104@18       I   /ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/eeprom@50          ?   S/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0        ?   /ocp/interconnect@48000000/segment@0/target-module@78000/elm@0        ?   ]/ocp/interconnect@48000000/segment@0/target-module@7a000/i2c@0        ?   /ocp/interconnect@48000000/segment@0/target-module@7c000/i2c@0        A   /ocp/interconnect@48000000/segment@0/target-module@86000/timer@0          A   /ocp/interconnect@48000000/segment@0/target-module@88000/timer@0          ?   /ocp/interconnect@48000000/segment@0/target-module@90000/rng@0        ?   /ocp/interconnect@48000000/segment@0/target-module@98000/spi@0        ?   /ocp/interconnect@48000000/segment@0/target-module@9a000/spi@0        ?   /ocp/interconnect@48000000/segment@0/target-module@9c000/mmc@0        9   /ocp/interconnect@48000000/segment@0/target-module@a5000          ?   /ocp/interconnect@48000000/segment@0/target-module@a5000/des@0        ?   /ocp/interconnect@48000000/segment@0/target-module@ad000/mmc@0        >   /ocp/interconnect@48000000/segment@0/target-module@b2000/1w@0         ?   /ocp/interconnect@48000000/segment@0/target-module@b4000/mmc@0        ?   /ocp/interconnect@48000000/segment@0/target-module@b8000/spi@0        ?   /ocp/interconnect@48000000/segment@0/target-module@ba000/spi@0        ?  !/ocp/interconnect@48000000/segment@0/target-module@d1000/mmc@0          !/ocp/interconnect@48400000        B  !/ocp/interconnect@48400000/segment@0/target-module@20000/serial@0         B  !/ocp/interconnect@48400000/segment@0/target-module@22000/serial@0         B  !/ocp/interconnect@48400000/segment@0/target-module@24000/serial@0         9  !"/ocp/interconnect@48400000/segment@0/target-module@3c000          ?  !)/ocp/interconnect@48400000/segment@0/target-module@3c000/atl@0        B  !-/ocp/interconnect@48400000/segment@0/target-module@3e000/epwmss@0         J  !5/ocp/interconnect@48400000/segment@0/target-module@3e000/epwmss@0/pwm@100         J  !;/ocp/interconnect@48400000/segment@0/target-module@3e000/epwmss@0/pwm@200         B  !C/ocp/interconnect@48400000/segment@0/target-module@40000/epwmss@0         J  !K/ocp/interconnect@48400000/segment@0/target-module@40000/epwmss@0/pwm@100         J  !Q/ocp/interconnect@48400000/segment@0/target-module@40000/epwmss@0/pwm@200         B  !Y/ocp/interconnect@48400000/segment@0/target-module@42000/epwmss@0         J  !a/ocp/interconnect@48400000/segment@0/target-module@42000/epwmss@0/pwm@100         J  !g/ocp/interconnect@48400000/segment@0/target-module@42000/epwmss@0/pwm@200         A  !o/ocp/interconnect@48400000/segment@0/target-module@60000/mcasp@0          A  !v/ocp/interconnect@48400000/segment@0/target-module@64000/mcasp@0          A  !}/ocp/interconnect@48400000/segment@0/target-module@68000/mcasp@0          A  !/ocp/interconnect@48400000/segment@0/target-module@6c000/mcasp@0          A  !/ocp/interconnect@48400000/segment@0/target-module@70000/mcasp@0          A  !/ocp/interconnect@48400000/segment@0/target-module@74000/mcasp@0          A  !/ocp/interconnect@48400000/segment@0/target-module@78000/mcasp@0          A  !/ocp/interconnect@48400000/segment@0/target-module@7c000/mcasp@0          ?  !/ocp/interconnect@48400000/segment@0/target-module@80000/can@0        B  !/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0         X  !/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@1       X  !/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@2       L  !/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/mdio@1000       [  !/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/mdio@1000/ethernet-phy@1        [  /ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/mdio@1000/ethernet-phy@2          !/ocp/interconnect@48800000        B  !/ocp/interconnect@48800000/segment@0/target-module@2000/mailbox@0         A  !/ocp/interconnect@48800000/segment@0/target-module@20000/timer@0          A  !/ocp/interconnect@48800000/segment@0/target-module@22000/timer@0          A  !/ocp/interconnect@48800000/segment@0/target-module@24000/timer@0          A  "/ocp/interconnect@48800000/segment@0/target-module@26000/timer@0          A  "/ocp/interconnect@48800000/segment@0/target-module@28000/timer@0          A  "/ocp/interconnect@48800000/segment@0/target-module@2a000/timer@0          9  "/ocp/interconnect@48800000/segment@0/target-module@2c000          A  ",/ocp/interconnect@48800000/segment@0/target-module@2c000/timer@0          9  "4/ocp/interconnect@48800000/segment@0/target-module@2e000          A  "C/ocp/interconnect@48800000/segment@0/target-module@2e000/timer@0          9  "K/ocp/interconnect@48800000/segment@0/target-module@38000          ?  /ocp/interconnect@48800000/segment@0/target-module@38000/rtc@0        C  "U/ocp/interconnect@48800000/segment@0/target-module@3a000/mailbox@0        C  "^/ocp/interconnect@48800000/segment@0/target-module@3c000/mailbox@0        C  "g/ocp/interconnect@48800000/segment@0/target-module@3e000/mailbox@0        C  "p/ocp/interconnect@48800000/segment@0/target-module@40000/mailbox@0        S  "y/ocp/interconnect@48800000/segment@0/target-module@40000/mailbox@0/mbox-ipu1-ipc3x        S  "/ocp/interconnect@48800000/segment@0/target-module@40000/mailbox@0/mbox-dsp1-ipc3x        C  "/ocp/interconnect@48800000/segment@0/target-module@42000/mailbox@0        S  "/ocp/interconnect@48800000/segment@0/target-module@42000/mailbox@0/mbox-ipu2-ipc3x        S  "/ocp/interconnect@48800000/segment@0/target-module@42000/mailbox@0/mbox-dsp2-ipc3x        C  "/ocp/interconnect@48800000/segment@0/target-module@44000/mailbox@0        C  "/ocp/interconnect@48800000/segment@0/target-module@46000/mailbox@0        C  "/ocp/interconnect@48800000/segment@0/target-module@5e000/mailbox@0        C  "/ocp/interconnect@48800000/segment@0/target-module@60000/mailbox@0        C  "/ocp/interconnect@48800000/segment@0/target-module@62000/mailbox@0        C  "/ocp/interconnect@48800000/segment@0/target-module@64000/mailbox@0        G  "/ocp/interconnect@48800000/segment@0/target-module@80000/omap_dwc3_1@0        Q  #/ocp/interconnect@48800000/segment@0/target-module@80000/omap_dwc3_1@0/usb@10000          G  #/ocp/interconnect@48800000/segment@0/target-module@c0000/omap_dwc3_2@0        Q   /ocp/interconnect@48800000/segment@0/target-module@c0000/omap_dwc3_2@0/usb@10000          :  #/ocp/interconnect@48800000/segment@0/target-module@100000         H  # /ocp/interconnect@48800000/segment@0/target-module@100000/omap_dwc3_3@0       R  #,/ocp/interconnect@48800000/segment@0/target-module@100000/omap_dwc3_3@0/usb@10000         @  /ocp/interconnect@48800000/segment@0/target-module@1d0010/vpe@0       :  #1/ocp/interconnect@48800000/segment@0/target-module@140000         H  #9/ocp/interconnect@48800000/segment@0/target-module@140000/omap_dwc3_4@0       R  #E/ocp/interconnect@48800000/segment@0/target-module@140000/omap_dwc3_4@0/usb@10000           #J/ocp/target-module@51000000       *  #O/ocp/target-module@51000000/pcie@51000000         ?  #X/ocp/target-module@51000000/pcie@51000000/interrupt-controller        -  #c/ocp/target-module@51000000/pcie_ep@51000000            #l/ocp/target-module@51800000       *  #q/ocp/target-module@51800000/pcie@51800000         ?  #z/ocp/target-module@51800000/pcie@51800000/interrupt-controller          #/ocp/ocmcram@40300000           #/ocp/ocmcram@40400000           #/ocp/ocmcram@40500000           #/ocp/bandgap@4a0021e0           #/ocp/dsp_system@40d00000            #/ocp/padconf@4844a000         2  #/ocp/padconf@4844a000/mmc1_iodelay_ddr_rev11_conf         4  #/ocp/padconf@4844a000/mmc1_iodelay_ddr50_rev20_conf       5  #/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev11_conf          5  $/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev20_conf          4  $</ocp/padconf@4844a000/mmc2_iodelay_hs200_rev11_conf       4  $Z/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev20_conf       7  $x/ocp/padconf@4844a000/mmc2_iodelay_ddr_3_3v_rev11_conf        7  $/ocp/padconf@4844a000/mmc2_iodelay_ddr_1_8v_rev11_conf        0  $/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf       0  $/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf       1  $/ocp/padconf@4844a000/mmc4_iodelay_ds_rev11_conf          1  %/ocp/padconf@4844a000/mmc4_iodelay_ds_rev20_conf          =  %0/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev11_conf          =  %W/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev20_conf          "  %~/ocp/target-module@43300000/dma@0         "  %/ocp/target-module@43400000/dma@0         "  %/ocp/target-module@43500000/dma@0           %/ocp/ipu@58820000           %/ocp/ipu@55020000           /ocp/dsp@40800000         "  %/ocp/target-module@40d01000/mmu@0         "  %/ocp/target-module@40d02000/mmu@0         "  %/ocp/target-module@58882000/mmu@0         "  %/ocp/target-module@55082000/mmu@0            %/ocp/regulator-abb-mpu@4ae07ddc       "  %/ocp/regulator-abb-ivahd@4ae07e34         #  %/ocp/regulator-abb-dspeve@4ae07e30           %/ocp/regulator-abb-gpu@4ae07de4       "  %/ocp/target-module@4b300000/spi@0         *  %/ocp/target-module@50000000/gpmc@50000000           %/ocp/crossbar@4a002a48        "  Q/ocp/target-module@58000000/dss@0         @  &/ocp/target-module@58000000/dss@0/target-module@40000/encoder@0       N  &
/ocp/target-module@58000000/dss@0/target-module@40000/encoder@0/port/endpoint         "  &/ocp/target-module@59000000/gpu@0           &/ocp/target-module@4b500000       "  &$/ocp/target-module@4b500000/aes@0           &)/ocp/target-module@4b700000       "  &5/ocp/target-module@4b700000/aes@0           &:/ocp/target-module@4b101000       #  &G/ocp/target-module@4b101000/sham@0          &M/ocp/target-module@42701000       #  &Z/ocp/target-module@42701000/sham@0          &`/ocp/target-module@5a000000         &n/ocp/opp-supply@4a003b20            &}/ocp/dsp_system@41500000          "  &/ocp/target-module@41501000/mmu@0         "  &/ocp/target-module@41502000/mmu@0           /ocp/dsp@41000000           &/ocp/target-module@4b226000       $  &/ocp/target-module@4b226000/pruss@0       /  &/ocp/target-module@4b226000/pruss@0/memories@0        .  &/ocp/target-module@4b226000/pruss@0/cfg@26000         C  &/ocp/target-module@4b226000/pruss@0/cfg@26000/clocks/iepclk-mux@30        1  &/ocp/target-module@4b226000/pruss@0/mii-rt@32000          ?  &/ocp/target-module@4b226000/pruss@0/interrupt-controller@20000        .  &/ocp/target-module@4b226000/pruss@0/pru@34000         .  &/ocp/target-module@4b226000/pruss@0/pru@38000         /  &/ocp/target-module@4b226000/pruss@0/mdio@32400          '
/ocp/target-module@4b2a6000       $  '/ocp/target-module@4b2a6000/pruss@0       /  '/ocp/target-module@4b2a6000/pruss@0/memories@0        .  '&/ocp/target-module@4b2a6000/pruss@0/cfg@26000         C  '1/ocp/target-module@4b2a6000/pruss@0/cfg@26000/clocks/iepclk-mux@30        1  'C/ocp/target-module@4b2a6000/pruss@0/mii-rt@32000          ?  'Q/ocp/target-module@4b2a6000/pruss@0/interrupt-controller@20000        .  ']/ocp/target-module@4b2a6000/pruss@0/pru@34000         .  'd/ocp/target-module@4b2a6000/pruss@0/pru@38000         /  'k/ocp/target-module@4b2a6000/pruss@0/mdio@32400          'w/thermal-zones          '/thermal-zones/cpu_thermal        !  '/thermal-zones/cpu_thermal/trips          +  '/thermal-zones/cpu_thermal/trips/cpu_alert        *  '/thermal-zones/cpu_thermal/trips/cpu_crit         ,  '/thermal-zones/cpu_thermal/trips/cpu_alert1       (  '/thermal-zones/cpu_thermal/cooling-maps         '/thermal-zones/gpu_thermal        *  '/thermal-zones/gpu_thermal/trips/gpu_crit           '/thermal-zones/core_thermal       ,  '/thermal-zones/core_thermal/trips/core_crit         '/thermal-zones/dspeve_thermal         0  (/thermal-zones/dspeve_thermal/trips/dspeve_crit         (/thermal-zones/iva_thermal        *  (/thermal-zones/iva_thermal/trips/iva_crit           ('/thermal-zones/board_thermal          #  (5/thermal-zones/board_thermal/trips        /  (A/thermal-zones/board_thermal/trips/board_alert        .  (N/thermal-zones/board_thermal/trips/board_crit         *  (Y/thermal-zones/board_thermal/cooling-maps           (l/fixedregulator-main_12v0           (v/fixedregulator-evm_5v0       &  (~/reserved-memory/ipu2-memory@95800000         &  (/reserved-memory/dsp1-memory@99000000         &  (/reserved-memory/ipu1-memory@9d000000         &  (/reserved-memory/dsp2-memory@9f000000           (/fixedregulator-vdd_3v3         (/fixedregulator-aic_dvdd            (/fixedregulator-vtt       
  (/gpio_fan           (/connector          (/connector/port/endpoint          	  )/encoder            )/encoder/ports/port@0/endpoint          )/encoder/ports/port@1/endpoint          )+/sound0          )2/sound0/simple-audio-card,codec          	#address-cells #size-cells compatible interrupt-parent model stdout-path i2c0 i2c1 i2c2 i2c3 i2c4 serial0 serial1 serial2 serial3 serial4 serial5 serial6 serial7 serial8 serial9 ethernet0 ethernet1 d_can0 d_can1 spi0 rproc0 rproc1 rproc2 rproc3 rtc0 rtc1 rtc2 display0 status interrupts interrupt-controller #interrupt-cells reg phandle device_type operating-points-v2 clocks clock-names clock-latency #cooling-cells vbb-supply vdd-supply voltage-tolerance syscon opp-shared opp-hz opp-microvolt opp-supported-hw opp-suspend power-domains ranges dma-ranges interrupts-extended reg-names regulator-name regulator-min-microvolt regulator-max-microvolt #phy-cells #clock-cells clock-output-names ti,bit-shift #pinctrl-cells pinctrl-single,register-width pinctrl-single,function-mask pinctrl-single,pins #syscon-cells #dma-cells dma-requests ti,dma-safe-map dma-masters clock-frequency clock-mult clock-div ti,max-div ti,autoidle-shift ti,index-starts-at-one ti,invert-autoidle-bit ti,index-power-of-two assigned-clocks assigned-clock-rates assigned-clock-parents ti,dividers ti,sysc-mask ti,sysc-midle ti,sysc-sidle ti,syss-mask dma-channels syscon-phy-power phy-supply syscon-pcs syscon-pllreset #mbox-cells ti,mbox-num-users ti,mbox-num-fifos #hwlock-cells phys phy-names ports-implemented #power-domain-cells #reset-cells gpio-controller #gpio-cells ti,no-reset-on-init ti,no-idle ti,timer-alwon ti,timer-secure syscon-raminit dmas dma-names ti,no-idle-on-init interrupt-names vcc-supply wakeup-source ti,system-power-controller ti,palmas-override-powerhold regulator-always-on regulator-boot-on ti,palmas-long-press-seconds ti,enable-vbus-detection vbus-gpio #thermal-sensor-cells #sound-dai-cells adc-settle-ms AVDD-supply IOVDD-supply DRVDD-supply DVDD-supply ti,spi-num-cs pbias-supply max-frequency mmc-ddr-1_8v mmc-ddr-3_3v pinctrl-names pinctrl-0 bus-width cd-gpios no-1-8-v pinctrl-1 vmmc-supply sdhci-caps-mask mmc-hs200-1_8v vqmmc-supply non-removable pinctrl-2 ti,provided-clocks #pwm-cells op-mode tdm-slots serial-dir tx-num-evt rx-num-evt label mac-address phy-handle phy-mode ti,dual-emac-pvid bus_freq max-speed ti,timer-pwm ti,mbox-tx ti,mbox-rx utmi-mode maximum-speed dr_mode snps,dis_u3_susphy_quirk snps,dis_u2_susphy_quirk extcon snps,dis_metastability_quirk resets reset-names bus-range num-lanes linux,pci-domain ti,syscon-lane-sel interrupt-map-mask interrupt-map ti,syscon-unaligned-access num-ib-windows num-ob-windows pinctrl-pin-array ti,tptcs iommus firmware-name mboxes ti,timers ti,watchdog-timers memory-region ti,bootreg #iommu-cells ti,syscon-mmuconfig ti,iommu-bus-err-back ti,settling-time ti,clock-cycles ti,tranxdone-status-mask ti,ldovbb-override-mask ti,ldovbb-vset-mask ti,abb_info syscon-chipselects gpmc,num-cs gpmc,num-waitpins ti,max-irqs ti,max-crossbar-sources ti,reg-size ti,irqs-reserved ti,irqs-skip ti,irqs-safe-map syscon-pll-ctrl vdda_video-supply syscon-pol vdda-supply remote-endpoint ti,efuse-settings ti,absolute-max-voltage-uv polling-delay-passive polling-delay thermal-sensors coefficients temperature hysteresis trip cooling-device vin-supply reusable enable-active-high linux,default-trigger default-state gpio-fan,speed-map simple-audio-card,name simple-audio-card,widgets simple-audio-card,routing simple-audio-card,format simple-audio-card,bitclock-master simple-audio-card,frame-master simple-audio-card,bitclock-inversion sound-dai gic wakeupgen cpu0 cpu0_opp_table ocp l4_cfg scm scm_conf pbias_regulator pbias_mmc_reg phy_gmii_sel scm_conf_clocks dss_deshdcp_clk ehrpwm0_tbclk ehrpwm1_tbclk ehrpwm2_tbclk sys_32k_ck dra7_pmx_core mmc1_pins_default mmc1_pins_sdr12 mmc1_pins_hs mmc1_pins_sdr25 mmc1_pins_sdr50 mmc1_pins_ddr50 mmc1_pins_sdr104 mmc2_pins_default mmc2_pins_hs mmc2_pins_ddr_3_3v_rev11 mmc2_pins_ddr_1_8v_rev11 mmc2_pins_ddr_rev20 mmc2_pins_hs200 mmc4_pins_default mmc4_pins_hs mmc3_pins_default mmc3_pins_hs mmc3_pins_sdr12 mmc3_pins_sdr25 mmc3_pins_sdr50 mmc4_pins_sdr12 mmc4_pins_sdr25 scm_conf1 scm_conf_pcie sdma_xbar edma_xbar cm_core_aon cm_core_aon_clocks atl_clkin0_ck atl_clkin1_ck atl_clkin2_ck atl_clkin3_ck hdmi_clkin_ck mlb_clkin_ck mlbp_clkin_ck pciesref_acs_clk_ck ref_clkin0_ck ref_clkin1_ck ref_clkin2_ck ref_clkin3_ck rmii_clk_ck sdvenc_clkin_ck secure_32k_clk_src_ck sys_clk32_crystal_ck sys_clk32_pseudo_ck virt_12000000_ck virt_13000000_ck virt_16800000_ck virt_19200000_ck virt_20000000_ck virt_26000000_ck virt_27000000_ck virt_38400000_ck sys_clkin2 usb_otg_clkin_ck video1_clkin_ck video1_m2_clkin_ck video2_clkin_ck video2_m2_clkin_ck dpll_abe_ck dpll_abe_x2_ck dpll_abe_m2x2_ck abe_clk dpll_abe_m2_ck dpll_abe_m3x2_ck dpll_core_byp_mux dpll_core_ck dpll_core_x2_ck dpll_core_h12x2_ck mpu_dpll_hs_clk_div dpll_mpu_ck dpll_mpu_m2_ck mpu_dclk_div dsp_dpll_hs_clk_div dpll_dsp_byp_mux dpll_dsp_ck dpll_dsp_m2_ck iva_dpll_hs_clk_div dpll_iva_byp_mux dpll_iva_ck dpll_iva_m2_ck iva_dclk dpll_gpu_byp_mux dpll_gpu_ck dpll_gpu_m2_ck dpll_core_m2_ck core_dpll_out_dclk_div dpll_ddr_byp_mux dpll_ddr_ck dpll_ddr_m2_ck dpll_gmac_byp_mux dpll_gmac_ck dpll_gmac_m2_ck video2_dclk_div video1_dclk_div hdmi_dclk_div per_dpll_hs_clk_div usb_dpll_hs_clk_div eve_dpll_hs_clk_div dpll_eve_byp_mux dpll_eve_ck dpll_eve_m2_ck eve_dclk_div dpll_core_h13x2_ck dpll_core_h14x2_ck dpll_core_h22x2_ck dpll_core_h23x2_ck dpll_core_h24x2_ck dpll_ddr_x2_ck dpll_ddr_h11x2_ck dpll_dsp_x2_ck dpll_dsp_m3x2_ck dpll_gmac_x2_ck dpll_gmac_h11x2_ck dpll_gmac_h12x2_ck dpll_gmac_h13x2_ck dpll_gmac_m3x2_ck gmii_m_clk_div hdmi_clk2_div hdmi_div_clk l3_iclk_div l4_root_clk_div video1_clk2_div video1_div_clk video2_clk2_div video2_div_clk dummy_ck cm_core_aon_clockdomains mpu_cm mpu_clkctrl dsp1_cm dsp1_clkctrl ipu_cm ipu1_clkctrl ipu_clkctrl dsp2_cm dsp2_clkctrl rtc_cm rtc_clkctrl vpe_cm vpe_clkctrl cm_core cm_core_clocks dpll_pcie_ref_ck dpll_pcie_ref_m2ldo_ck apll_pcie_in_clk_mux apll_pcie_ck optfclk_pciephy_div apll_pcie_clkvcoldo apll_pcie_clkvcoldo_div apll_pcie_m2_ck dpll_per_byp_mux dpll_per_ck dpll_per_m2_ck func_96m_aon_dclk_div dpll_usb_byp_mux dpll_usb_ck dpll_usb_m2_ck dpll_pcie_ref_m2_ck dpll_per_x2_ck dpll_per_h11x2_ck dpll_per_h12x2_ck dpll_per_h13x2_ck dpll_per_h14x2_ck dpll_per_m2x2_ck dpll_usb_clkdcoldo func_128m_clk func_12m_fclk func_24m_clk func_48m_fclk func_96m_fclk l3init_60m_fclk clkout2_clk l3init_960m_gfclk usb_phy1_always_on_clk32k usb_phy2_always_on_clk32k usb_phy3_always_on_clk32k gpu_core_gclk_mux gpu_hyd_gclk_mux l3instr_ts_gclk_div vip1_gclk_mux vip2_gclk_mux vip3_gclk_mux cm_core_clockdomains coreaon_clkdm coreaon_cm coreaon_clkctrl l3main1_cm l3main1_clkctrl ipu2_cm ipu2_clkctrl dma_cm dma_clkctrl emif_cm emif_clkctrl atl_cm atl_clkctrl l4cfg_cm l4cfg_clkctrl l3instr_cm l3instr_clkctrl iva_cm iva_clkctrl cam_cm cam_clkctrl dss_cm dss_clkctrl gpu_cm gpu_clkctrl l3init_cm l3init_clkctrl pcie_clkctrl gmac_clkctrl l4per_cm l4per_clkctrl l4sec_clkctrl l4per2_clkctrl l4per3_clkctrl sdma usb2_phy1 usb2_phy2 usb3_phy1 pcie1_phy pcie2_phy sata_phy mailbox1 hwspinlock sata l4_wkup counter32k prm prm_clocks sys_clkin1 abe_dpll_sys_clk_mux abe_dpll_bypass_clk_mux abe_dpll_clk_mux abe_24m_fclk aess_fclk abe_giclk_div abe_lp_clk_div abe_sys_clk_div adc_gfclk_mux sys_clk1_dclk_div sys_clk2_dclk_div per_abe_x1_dclk_div dsp_gclk_div gpu_dclk emif_phy_dclk_div gmac_250m_dclk_div gmac_main_clk l3init_480m_dclk_div usb_otg_dclk_div sata_dclk_div pcie2_dclk_div pcie_dclk_div emu_dclk_div secure_32k_dclk_div clkoutmux0_clk_mux clkoutmux1_clk_mux clkoutmux2_clk_mux custefuse_sys_gfclk_div eve_clk hdmi_dpll_clk_mux mlb_clk mlbp_clk per_abe_x1_gfclk2_div timer_sys_clk_div video1_dpll_clk_mux video2_dpll_clk_mux wkupaon_iclk_mux prm_clockdomains wkupaon_cm wkupaon_clkctrl prm_mpu prm_dsp1 prm_ipu prm_coreaon prm_core prm_iva prm_cam prm_dss prm_gpu prm_l3init prm_l4per prm_custefuse prm_wkupaon prm_dsp2 prm_eve1 prm_eve2 prm_eve3 prm_eve4 prm_rtc prm_vpe scm_wkup gpio1 wdt2 timer1_target timer1 timer12 uart10 dcan1 l4_per1 uart3 timer2 timer3_target timer3 timer4_target timer4 timer9 gpio7_target gpio7 gpio8 gpio2_target gpio2 gpio3_target gpio3 gpio4 gpio5 gpio6 mcp_rtc uart5 uart6 uart1 uart2 uart4 tps659038 smps12_reg smps3_reg smps45_reg smps6_reg smps8_reg ldo1_reg ldo2_reg ldo3_reg ldo4_reg ldo9_reg ldoln_reg ldousb_reg regen1 tps659038_rtc tps659038_pwr_button tps659038_gpio extcon_usb2 tmp102 tlv320aic3104 eeprom elm i2c5 timer10 timer11 rng mcspi1 mcspi2 mmc1 des_target des mmc3 hdqw1w mmc2 mcspi3 mcspi4 mmc4 l4_per2 uart7 uart8 uart9 atl_tm atl epwmss0 ecap0 ehrpwm0 epwmss1 ecap1 ehrpwm1 epwmss2 ecap2 ehrpwm2 mcasp1 mcasp2 mcasp3 mcasp4 mcasp5 mcasp6 mcasp7 mcasp8 dcan2 mac_sw cpsw_port1 cpsw_port2 davinci_mdio_sw phy0 l4_per3 mailbox13 timer5 timer6 timer7 timer8 timer13 timer14 timer15_target timer15 timer16_target timer16 rtctarget mailbox2 mailbox3 mailbox4 mailbox5 mbox_ipu1_ipc3x mbox_dsp1_ipc3x mailbox6 mbox_ipu2_ipc3x mbox_dsp2_ipc3x mailbox7 mailbox8 mailbox9 mailbox10 mailbox11 mailbox12 omap_dwc3_1 usb1 omap_dwc3_2 usb3_tm omap_dwc3_3 usb3 usb4_tm omap_dwc3_4 usb4 axi0 pcie1_rc pcie1_intc pcie1_ep axi1 pcie2_rc pcie2_intc ocmcram1 ocmcram2 ocmcram3 bandgap dsp1_system dra7_iodelay_core mmc1_iodelay_ddr_rev11_conf mmc1_iodelay_ddr_rev20_conf mmc1_iodelay_sdr104_rev11_conf mmc1_iodelay_sdr104_rev20_conf mmc2_iodelay_hs200_rev11_conf mmc2_iodelay_hs200_rev20_conf mmc2_iodelay_ddr_3_3v_rev11_conf mmc2_iodelay_ddr_1_8v_rev11_conf mmc3_iodelay_manual1_rev11_conf mmc3_iodelay_manual1_rev20_conf mmc4_iodelay_ds_rev11_conf mmc4_iodelay_ds_rev20_conf mmc4_iodelay_sdr12_hs_sdr25_rev11_conf mmc4_iodelay_sdr12_hs_sdr25_rev20_conf edma edma_tptc0 edma_tptc1 ipu1 ipu2 mmu0_dsp1 mmu1_dsp1 mmu_ipu1 mmu_ipu2 abb_mpu abb_ivahd abb_dspeve abb_gpu qspi gpmc crossbar_mpu hdmi hdmi_out bb2d aes1_target aes1 aes2_target aes2 sham1_target sham1 sham2_target sham2 iva_hd_target opp_supply_mpu dsp2_system mmu0_dsp2 mmu1_dsp2 pruss1_tm pruss1 pruss1_mem pruss1_cfg pruss1_iepclk_mux pruss1_mii_rt pruss1_intc pru1_0 pru1_1 pruss1_mdio pruss2_tm pruss2 pruss2_mem pruss2_cfg pruss2_iepclk_mux pruss2_mii_rt pruss2_intc pru2_0 pru2_1 pruss2_mdio thermal_zones cpu_thermal cpu_trips cpu_alert0 cpu_crit cpu_alert1 cpu_cooling_maps gpu_thermal gpu_crit core_thermal core_crit dspeve_thermal dspeve_crit iva_thermal iva_crit board_thermal board_trips board_alert0 board_crit board_cooling_maps main_12v0 evm_5v0 ipu2_memory_region dsp1_memory_region ipu1_memory_region dsp2_memory_region vdd_3v3 aic_dvdd vtt_fixed gpio_fan hdmi0 hdmi_connector_in tpd12s015 tpd12s015_in tpd12s015_out sound0 sound0_master 