    8    (            
2 x                             )    isee,omap3-igep0030 ti,omap3630 ti,omap3                                     +         *   7IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)      chosen           =/ocp@68000000/serial@49020000         aliases          I/ocp@68000000/i2c@48070000           N/ocp@68000000/i2c@48072000           S/ocp@68000000/i2c@48060000           X/ocp@68000000/mmc@4809c000           ]/ocp@68000000/mmc@480b4000           b/ocp@68000000/mmc@480ad000           g/ocp@68000000/serial@4806a000            o/ocp@68000000/serial@4806c000            w/ocp@68000000/serial@49020000            /ocp@68000000/serial@49042000         cpus                         +       cpu@0             arm,cortex-a8            cpu                                   cpu                                                                   pmu@54000000              arm,cortex-a8-pmu            T                           debugss       soc           ti,omap-infra      mpu           ti,omap3-mpu             mpu       iva       
    ti,iva2.2            iva    dsp           ti,omap3-c64                ocp@68000000              ti,omap3-l3-smx simple-bus           h                  	   
                     +                     l3_main    l4@48000000           ti,omap3-l4-core simple-bus                      +               H         scm@2000              ti,omap3-scm simple-bus                                       +                          pinmux@30              ti,omap3-padconf pinctrl-single             0  8                     +            
                       *        ?           ]          zdefault               gpmc-pins                                  uart1-pins            R     L                      uart3-pins            n     p                      mcbsp2-pins                                                 mmc1-pins         0                                            mmc2-pins         0    (    *    ,    .    0    2                    i2c1-pins                                       i2c3-pins                                       twl4030-pins                A                  hsusb2-pins       0                                            uart2-pins             <    >     @     B                    lbee1usjyc-pins           6     8     :                        scm_conf@270              syscon simple-bus              p  0                     +                 p  0               pbias_regulator@2b0           ti,pbias-omap3 ti,pbias-omap                                pbias_mmc_omap2430          pbias_mmc_omap2430           w@         -                     clocks                       +       clock@68          
    ti,clksel               h                                +       clock-mcbsp5-mux-fck@4                                    ti,composite-mux-clock          mcbsp5_mux_fck                                   clock-mcbsp3-mux-fck@0                                     ti,composite-mux-clock          mcbsp3_mux_fck              	                     clock-mcbsp4-mux-fck@2                                    ti,composite-mux-clock          mcbsp4_mux_fck              	                        mcbsp5_fck                        ti,composite-clock              
                    clock@4       
    ti,clksel                                               +       clock-mcbsp1-mux-fck@2                                    ti,composite-mux-clock          mcbsp1_mux_fck                                   clock-mcbsp2-mux-fck@6                                    ti,composite-mux-clock          mcbsp2_mux_fck              	                        mcbsp1_fck                        ti,composite-clock                                   mcbsp2_fck                        ti,composite-clock                                   mcbsp3_fck                        ti,composite-clock                                   mcbsp4_fck                        ti,composite-clock                                         clockdomains          pinmux@a00             ti,omap3-padconf pinctrl-single            
    \                     +            
                       *        ?           ]     twl4030-vpins-pins                                                                 target-module@480a6000            ti,sysc-omap2 ti,sysc            H
`D   H
`H   H
`L           rev sysc syss                      #                  1                        ick                      +               H
`        aes1@0            ti,omap3-aes                    P                     >      	      
        Ctx rx            target-module@480c5000            ti,sysc-omap2 ti,sysc            HPD   HPH   HPL           rev sysc syss                      #                  1                        ick                      +               HP        aes2@0            ti,omap3-aes                    P                     >      A      B        Ctx rx            prm@48306000              ti,omap3-prm             H0`   @                clocks                       +       virt_16_8m_ck                         fixed-clock         M Y                   osc_sys_ck@d40                        ti,mux-clock                                          @                  sys_ck@1270                       ti,divider-clock                        ]           j              p         u            "      sys_clkout1@d70                       ti,gate-clock                          p        ]         dpll3_x2_ck                       fixed-factor-clock                                          dpll3_m2x2_ck                         fixed-factor-clock                                                !      dpll4_x2_ck                       fixed-factor-clock                                           corex2_fck                        fixed-factor-clock              !                                  #      wkup_l4_ick                       fixed-factor-clock              "                                  b      corex2_d3_fck                         fixed-factor-clock              #                                        corex2_d5_fck                         fixed-factor-clock              #                                           clockdomains             cm@48004000           ti,omap3-cm          H @   @    clocks                       +       dummy_apb_pclk                        fixed-clock         M          omap_32k_fck                          fixed-clock         M               H      virt_12m_ck                       fixed-clock         M                    virt_13m_ck                       fixed-clock         M ]@                  virt_19200000_ck                          fixed-clock         M$                   virt_26000000_ck                          fixed-clock         M                  virt_38_4m_ck                         fixed-clock         MI                   dpll4_ck@d00                          ti,omap3-dpll-per-j-type-clock              "   "                 D  0                   dpll4_m2_ck@d48                       ti,divider-clock                         j   ?           H         u            $      dpll4_m2x2_mul_ck                         fixed-factor-clock              $                                  %      dpll4_m2x2_ck@d00                         ti,hsdiv-gate-clock             %        ]                                    &      omap_96m_alwon_fck                        fixed-factor-clock              &                                  2      dpll3_ck@d00                          ti,omap3-dpll-core-clock                "   "                 @  0                  clock@1140        
    ti,clksel              @                                +       clock-dpll3-m3@16                                     ti,divider-clock            dpll3_m3_ck                     j            u            ,      clock-dpll4-m6@24                                     ti,divider-clock            dpll4_m6_ck                      j   ?         u            >      clock-emu-src-mux@0                                    ti,mux-clock            emu_src_mux_ck              "   '   (   )            v      clock-pclk-fck@8                                      ti,divider-clock          	  pclk_fck                *        j            u      clock-pclkx2-fck@6                                    ti,divider-clock            pclkx2_fck              *        j            u      clock-atclk-fck@4                                     ti,divider-clock          
  atclk_fck               *        j            u      clock-traceclk-src-fck@2                                      ti,mux-clock            traceclk_src_fck                "   '   (   )            +      clock-traceclk-fck@11                                     ti,divider-clock            traceclk_fck                +        j            u         dpll3_m3x2_mul_ck                         fixed-factor-clock              ,                                  -      dpll3_m3x2_ck@d00                         ti,hsdiv-gate-clock             -        ]                                    .      emu_core_alwon_ck                         fixed-factor-clock              .                                  '      sys_altclk                        fixed-clock         M                5      mcbsp_clks                        fixed-clock         M                      core_ck                       fixed-factor-clock                                                /      dpll1_fck@940                         ti,divider-clock                /        ]           j              	@         u            0      dpll1_ck@904                          ti,omap3-dpll-clock             "   0           	  	$  	@  	4                  dpll1_x2_ck                       fixed-factor-clock                                                1      dpll1_x2m2_ck@944                         ti,divider-clock                1        j              	D         u            E      cm_96m_fck                        fixed-factor-clock              2                                  3      clock@d40         
    ti,clksel              @                                +       clock-dpll3-m2@27                                     ti,divider-clock            dpll3_m2_ck                     j            u                  clock-omap-96m-fck@6                                      ti,mux-clock            omap_96m_fck                3   "            Y      clock-omap-54m-fck@5                                      ti,mux-clock            omap_54m_fck                4   5            A      clock-omap-48m-fck@3                                      ti,mux-clock            omap_48m_fck                6   5            9         clock@e40         
    ti,clksel              @                                +       clock-dpll4-m3@8                                      ti,divider-clock            dpll4_m3_ck                      j             u            7      clock-dpll4-m4@0                                       ti,divider-clock            dpll4_m4_ck                      j            u            :         dpll4_m3x2_mul_ck                         fixed-factor-clock              7                                  8      dpll4_m3x2_ck@d00                         ti,hsdiv-gate-clock             8        ]                                    4      cm_96m_d2_fck                         fixed-factor-clock              3                                  6      omap_12m_fck                          fixed-factor-clock              9                                  Z      dpll4_m4x2_mul_ck                         ti,fixed-factor-clock               :                                           ;      dpll4_m4x2_ck@d00                         ti,gate-clock               ;        ]                                             ^      dpll4_m5_ck@f40                       ti,divider-clock                         j   ?           @         u            <      dpll4_m5x2_mul_ck                         ti,fixed-factor-clock               <                                           =      dpll4_m5x2_ck@d00                         ti,hsdiv-gate-clock             =        ]                                             z      dpll4_m6x2_mul_ck                         fixed-factor-clock              >                                  ?      dpll4_m6x2_ck@d00                         ti,hsdiv-gate-clock             ?        ]                                    @      emu_per_alwon_ck                          fixed-factor-clock              @                                  (      clock@d70         
    ti,clksel              p                                +       clock-clkout2-src-gate@7                                       ti,composite-no-wait-gate-clock         clkout2_src_gate_ck             /            C      clock-clkout2-src-mux@0                                    ti,composite-mux-clock          clkout2_src_mux_ck              /   "   3   A            D      clock-sys-clkout2@3                                   ti,divider-clock            sys_clkout2             B        j   @                  clkout2_src_ck                        ti,composite-clock              C   D            B      mpu_ck                        fixed-factor-clock              E                                  F      arm_fck@924                       ti,divider-clock                F           	$        j         emu_mpu_alwon_ck                          fixed-factor-clock              F                                  )      clock@a40         
    ti,clksel              
@                                +       clock-l3-ick@0                                     ti,divider-clock            l3_ick              /        j            u            G      clock-l4-ick@2                                    ti,divider-clock            l4_ick              G        j            u            I      clock-gpt10-mux-fck@6                                     ti,composite-mux-clock          gpt10_mux_fck               H   "            V      clock-gpt11-mux-fck@7                                     ti,composite-mux-clock          gpt11_mux_fck               H   "            X      clock-ssi-ssr-div-fck-3430es2@8                                   ti,composite-divider-clock          ssi_ssr_div_fck_3430es2             #      $                                                     clock@c40         
    ti,clksel              @                                +       clock-rm-ick@1                                    ti,divider-clock            rm_ick              I        j            u      clock-gpt1-mux-fck@0                                       ti,composite-mux-clock          gpt1_mux_fck                H   "            a      clock-usim-mux-fck@3                                      ti,composite-mux-clock          usim_mux_fck          (      "   J   K   L   M   N   O   P   Q   R         u                     clock@a00         
    ti,clksel              
                                 +       clock-gpt10-gate-fck@11                                   ti,composite-gate-clock         gpt10_gate_fck              "            U      clock-gpt11-gate-fck@12                                   ti,composite-gate-clock         gpt11_gate_fck              "            W      clock-mmchs2-fck@25                                   ti,wait-gate-clock          mmchs2_fck                                clock-mmchs1-fck@24                                   ti,wait-gate-clock          mmchs1_fck                                clock-i2c3-fck@17                                     ti,wait-gate-clock        	  i2c3_fck                                  clock-i2c2-fck@16                                     ti,wait-gate-clock        	  i2c2_fck                                  clock-i2c1-fck@15                                     ti,wait-gate-clock        	  i2c1_fck                                  clock-mcbsp5-gate-fck@10                
                      ti,composite-gate-clock         mcbsp5_gate_fck                         
      clock-mcbsp1-gate-fck@9             	                      ti,composite-gate-clock         mcbsp1_gate_fck                               clock-mcspi4-fck@21                                   ti,wait-gate-clock          mcspi4_fck              S                  clock-mcspi3-fck@20                                   ti,wait-gate-clock          mcspi3_fck              S                  clock-mcspi2-fck@19                                   ti,wait-gate-clock          mcspi2_fck              S                  clock-mcspi1-fck@18                                   ti,wait-gate-clock          mcspi1_fck              S                  clock-uart2-fck@14                                    ti,wait-gate-clock        
  uart2_fck               S                  clock-uart1-fck@13                                    ti,wait-gate-clock        
  uart1_fck               S                  clock-hdq-fck@22                                      ti,wait-gate-clock          hdq_fck             T                  clock-modem-fck@31                                    ti,omap3-interface-clock          
  modem_fck               "                  clock-mspro-fck@23                                    ti,wait-gate-clock        
  mspro_fck                     clock-ssi-ssr-gate-fck-3430es2@0                                        ti,composite-no-wait-gate-clock         ssi_ssr_gate_fck_3430es2                #            ~      clock-mmchs3-fck@30                                   ti,wait-gate-clock          mmchs3_fck                                   gpt10_fck                         ti,composite-clock              U   V      gpt11_fck                         ti,composite-clock              W   X      core_96m_fck                          fixed-factor-clock              Y                                        core_48m_fck                          fixed-factor-clock              9                                  S      core_12m_fck                          fixed-factor-clock              Z                                  T      core_l3_ick                       fixed-factor-clock              G                                  [      clock@a10         
    ti,clksel              
                                +       clock-sdrc-ick@1                                      ti,wait-gate-clock        	  sdrc_ick                [                  clock-mmchs2-ick@25                                   ti,omap3-interface-clock            mmchs2_ick              \                  clock-mmchs1-ick@24                                   ti,omap3-interface-clock            mmchs1_ick              \                  clock-hdq-ick@22                                      ti,omap3-interface-clock            hdq_ick             \                  clock-mcspi4-ick@21                                   ti,omap3-interface-clock            mcspi4_ick              \                  clock-mcspi3-ick@20                                   ti,omap3-interface-clock            mcspi3_ick              \                  clock-mcspi2-ick@19                                   ti,omap3-interface-clock            mcspi2_ick              \                  clock-mcspi1-ick@18                                   ti,omap3-interface-clock            mcspi1_ick              \                  clock-i2c3-ick@17                                     ti,omap3-interface-clock          	  i2c3_ick                \                  clock-i2c2-ick@16                                     ti,omap3-interface-clock          	  i2c2_ick                \                  clock-i2c1-ick@15                                     ti,omap3-interface-clock          	  i2c1_ick                \                  clock-uart2-ick@14                                    ti,omap3-interface-clock          
  uart2_ick               \                  clock-uart1-ick@13                                    ti,omap3-interface-clock          
  uart1_ick               \                  clock-gpt11-ick@12                                    ti,omap3-interface-clock          
  gpt11_ick               \                  clock-gpt10-ick@11                                    ti,omap3-interface-clock          
  gpt10_ick               \                  clock-mcbsp5-ick@10             
                      ti,omap3-interface-clock            mcbsp5_ick              \                  clock-mcbsp1-ick@9              	                      ti,omap3-interface-clock            mcbsp1_ick              \                  clock-omapctrl-ick@6                                      ti,omap3-interface-clock            omapctrl_ick                \                  clock-aes2-ick@28                                     ti,omap3-interface-clock          	  aes2_ick                \                  clock-sha12-ick@27                                    ti,omap3-interface-clock          
  sha12_ick               \                  clock-icr-ick@29                                      ti,omap3-interface-clock            icr_ick             \      clock-des2-ick@26                                     ti,omap3-interface-clock          	  des2_ick                \      clock-mspro-ick@23                                    ti,omap3-interface-clock          
  mspro_ick               \      clock-mailboxes-ick@7                                     ti,omap3-interface-clock            mailboxes_ick               \      clock-sad2d-ick@3                                     ti,omap3-interface-clock          
  sad2d_ick               G                  clock-hsotgusb-ick-3430es2@4                                  "    ti,omap3-hsotgusb-interface-clock           hsotgusb_ick_3430es2                [                  clock-ssi-ick-3430es2@0                                    ti,omap3-ssi-interface-clock            ssi_ick_3430es2             ]           
      clock-mmchs3-ick@30                                   ti,omap3-interface-clock            mmchs3_ick              \                     gpmc_fck                          fixed-factor-clock              [                            core_l4_ick                       fixed-factor-clock              I                                  \      clock@e00         
    ti,clksel                                               +       clock-dss-tv-fck                          ti,gate-clock           dss_tv_fck              A        ]                     clock-dss-96m-fck                         ti,gate-clock           dss_96m_fck             Y        ]                     clock-dss2-alwon-fck                          ti,gate-clock           dss2_alwon_fck              "        ]                     clock-dss1-alwon-fck-3430es2@0                                     ti,dss-gate-clock           dss1_alwon_fck_3430es2              ^                              dummy_ck                          fixed-clock         M          clock@c00         
    ti,clksel                                               +       clock-gpt1-gate-fck@0                                      ti,composite-gate-clock         gpt1_gate_fck               "            `      clock-gpio1-dbck@3                                    ti,gate-clock           gpio1_dbck              _                  clock-wdt2-fck@5                                      ti,wait-gate-clock        	  wdt2_fck                _                  clock-sr1-fck@6                                   ti,wait-gate-clock          sr1_fck             "                 clock-sr2-fck@7                                   ti,wait-gate-clock          sr2_fck             "                 clock-usim-gate-fck@9               	                      ti,composite-gate-clock         usim_gate_fck               Y                     gpt1_fck                          ti,composite-clock              `   a                 wkup_32k_fck                          fixed-factor-clock              H                                  _      clock@c10         
    ti,clksel                                              +       clock-wdt2-ick@5                                      ti,omap3-interface-clock          	  wdt2_ick                b                  clock-wdt1-ick@4                                      ti,omap3-interface-clock          	  wdt1_ick                b                  clock-gpio1-ick@3                                     ti,omap3-interface-clock          
  gpio1_ick               b                  clock-omap-32ksync-ick@2                                      ti,omap3-interface-clock            omap_32ksync_ick                b                  clock-gpt12-ick@1                                     ti,omap3-interface-clock          
  gpt12_ick               b                  clock-gpt1-ick@0                                       ti,omap3-interface-clock          	  gpt1_ick                b                  clock-usim-ick@9                	                      ti,omap3-interface-clock          	  usim_ick                b                     per_96m_fck                       fixed-factor-clock              2                                  	      per_48m_fck                       fixed-factor-clock              9                                  c      clock@1000        
    ti,clksel                                               +       clock-uart3-fck@11                                    ti,wait-gate-clock        
  uart3_fck               c                  clock-gpt2-gate-fck@3                                     ti,composite-gate-clock         gpt2_gate_fck               "            e      clock-gpt3-gate-fck@4                                     ti,composite-gate-clock         gpt3_gate_fck               "            g      clock-gpt4-gate-fck@5                                     ti,composite-gate-clock         gpt4_gate_fck               "            i      clock-gpt5-gate-fck@6                                     ti,composite-gate-clock         gpt5_gate_fck               "            k      clock-gpt6-gate-fck@7                                     ti,composite-gate-clock         gpt6_gate_fck               "            m      clock-gpt7-gate-fck@8                                     ti,composite-gate-clock         gpt7_gate_fck               "            o      clock-gpt8-gate-fck@9               	                      ti,composite-gate-clock         gpt8_gate_fck               "            q      clock-gpt9-gate-fck@10              
                      ti,composite-gate-clock         gpt9_gate_fck               "            s      clock-gpio6-dbck@17                                   ti,gate-clock           gpio6_dbck              d                  clock-gpio5-dbck@16                                   ti,gate-clock           gpio5_dbck              d                  clock-gpio4-dbck@15                                   ti,gate-clock           gpio4_dbck              d                  clock-gpio3-dbck@14                                   ti,gate-clock           gpio3_dbck              d                  clock-gpio2-dbck@13                                   ti,gate-clock           gpio2_dbck              d                  clock-wdt3-fck@12                                     ti,wait-gate-clock        	  wdt3_fck                d                  clock-mcbsp2-gate-fck@0                                    ti,composite-gate-clock         mcbsp2_gate_fck                               clock-mcbsp3-gate-fck@1                                   ti,composite-gate-clock         mcbsp3_gate_fck                               clock-mcbsp4-gate-fck@2                                   ti,composite-gate-clock         mcbsp4_gate_fck                               clock-uart4-fck@18                                    ti,wait-gate-clock        
  uart4_fck               c                     clock@1040        
    ti,clksel              @                                +       clock-gpt2-mux-fck@0                                       ti,composite-mux-clock          gpt2_mux_fck                H   "            f      clock-gpt3-mux-fck@1                                      ti,composite-mux-clock          gpt3_mux_fck                H   "            h      clock-gpt4-mux-fck@2                                      ti,composite-mux-clock          gpt4_mux_fck                H   "            j      clock-gpt5-mux-fck@3                                      ti,composite-mux-clock          gpt5_mux_fck                H   "            l      clock-gpt6-mux-fck@4                                      ti,composite-mux-clock          gpt6_mux_fck                H   "            n      clock-gpt7-mux-fck@5                                      ti,composite-mux-clock          gpt7_mux_fck                H   "            p      clock-gpt8-mux-fck@6                                      ti,composite-mux-clock          gpt8_mux_fck                H   "            r      clock-gpt9-mux-fck@7                                      ti,composite-mux-clock          gpt9_mux_fck                H   "            t         gpt2_fck                          ti,composite-clock              e   f                 gpt3_fck                          ti,composite-clock              g   h      gpt4_fck                          ti,composite-clock              i   j      gpt5_fck                          ti,composite-clock              k   l      gpt6_fck                          ti,composite-clock              m   n      gpt7_fck                          ti,composite-clock              o   p      gpt8_fck                          ti,composite-clock              q   r      gpt9_fck                          ti,composite-clock              s   t      per_32k_alwon_fck                         fixed-factor-clock              H                                  d      per_l4_ick                        fixed-factor-clock              I                                  u      clock@1010        
    ti,clksel                                              +       clock-gpio6-ick@17                                    ti,omap3-interface-clock          
  gpio6_ick               u                  clock-gpio5-ick@16                                    ti,omap3-interface-clock          
  gpio5_ick               u                  clock-gpio4-ick@15                                    ti,omap3-interface-clock          
  gpio4_ick               u                  clock-gpio3-ick@14                                    ti,omap3-interface-clock          
  gpio3_ick               u                  clock-gpio2-ick@13                                    ti,omap3-interface-clock          
  gpio2_ick               u                  clock-wdt3-ick@12                                     ti,omap3-interface-clock          	  wdt3_ick                u                  clock-uart3-ick@11                                    ti,omap3-interface-clock          
  uart3_ick               u                  clock-uart4-ick@18                                    ti,omap3-interface-clock          
  uart4_ick               u                  clock-gpt9-ick@10               
                      ti,omap3-interface-clock          	  gpt9_ick                u                  clock-gpt8-ick@9                	                      ti,omap3-interface-clock          	  gpt8_ick                u                  clock-gpt7-ick@8                                      ti,omap3-interface-clock          	  gpt7_ick                u                  clock-gpt6-ick@7                                      ti,omap3-interface-clock          	  gpt6_ick                u                  clock-gpt5-ick@6                                      ti,omap3-interface-clock          	  gpt5_ick                u                  clock-gpt4-ick@5                                      ti,omap3-interface-clock          	  gpt4_ick                u                  clock-gpt3-ick@4                                      ti,omap3-interface-clock          	  gpt3_ick                u                  clock-gpt2-ick@3                                      ti,omap3-interface-clock          	  gpt2_ick                u                  clock-mcbsp2-ick@0                                     ti,omap3-interface-clock            mcbsp2_ick              u                  clock-mcbsp3-ick@1                                    ti,omap3-interface-clock            mcbsp3_ick              u                  clock-mcbsp4-ick@2                                    ti,omap3-interface-clock            mcbsp4_ick              u                     emu_src_ck                        ti,clkdm-gate-clock             v            *      secure_32k_fck                        fixed-clock         M               w      gpt12_fck                         fixed-factor-clock              w                                       wdt1_fck                          fixed-factor-clock              w                            security_l4_ick2                          fixed-factor-clock              I                                  x      clock@a14         
    ti,clksel              
                                +       clock-aes1-ick@3                                      ti,omap3-interface-clock          	  aes1_ick                x                  clock-rng-ick@2                                   ti,omap3-interface-clock            rng_ick             x                  clock-sha11-ick@1                                     ti,omap3-interface-clock          
  sha11_ick               x      clock-des1-ick@0                                       ti,omap3-interface-clock          	  des1_ick                x      clock-pka-ick@4                                   ti,omap3-interface-clock            pka_ick             y         clock@f00         
    ti,clksel                                               +       clock-cam-mclk@0                                       ti,gate-clock         	  cam_mclk                z               clock-csi2-96m-fck@1                                      ti,gate-clock           csi2_96m_fck                                     cam_ick@f10                   !    ti,omap3-no-wait-interface-clock                I                   ]                      security_l3_ick                       fixed-factor-clock              G                                  y      ssi_l4_ick                        fixed-factor-clock              I                                  ]      sr_l4_ick                         fixed-factor-clock              I                            dpll2_fck@40                          ti,divider-clock                /        ]           j               @         u            {      dpll2_ck@4                        ti,omap3-dpll-clock             "   {               $   @   4                           !            |      dpll2_m2_ck@44                        ti,divider-clock                |        j               D         u            }      iva2_ck@0                         ti,wait-gate-clock              }                     ]                      clock@a18         
    ti,clksel              
                               5             +       clock-mad2d-ick@3                                     ti,omap3-interface-clock          
  mad2d_ick               G                  clock-usbtll-ick@2                                    ti,omap3-interface-clock            usbtll_ick              \                     ssi_ssr_fck_3430es2                       ti,composite-clock              ~                     ssi_sst_fck_3430es2                       fixed-factor-clock                                               	      sys_d2_ck                         fixed-factor-clock              "                                  J      omap_96m_d2_fck                       fixed-factor-clock              Y                                  K      omap_96m_d4_fck                       fixed-factor-clock              Y                                  L      omap_96m_d8_fck                       fixed-factor-clock              Y                                  M      omap_96m_d10_fck                          fixed-factor-clock              Y                      
            N      dpll5_m2_d4_ck                        fixed-factor-clock                                                O      dpll5_m2_d8_ck                        fixed-factor-clock                                                P      dpll5_m2_d16_ck                       fixed-factor-clock                                                Q      dpll5_m2_d20_ck                       fixed-factor-clock                                                R      usim_fck                          ti,composite-clock                       dpll5_ck@d04                          ti,omap3-dpll-clock             "   "             $  L  4                                    dpll5_m2_ck@d50                       ti,divider-clock                        j              P         u                  sgx_gate_fck@b00                          ti,composite-gate-clock             /        ]                                 core_d3_ck                        fixed-factor-clock              /                                        core_d4_ck                        fixed-factor-clock              /                                        core_d6_ck                        fixed-factor-clock              /                                        omap_192m_alwon_fck                       fixed-factor-clock              &                                        core_d2_ck                        fixed-factor-clock              /                                        sgx_mux_fck@b40                       ti,composite-mux-clock                        3                       @                  sgx_fck                       ti,composite-clock                                  sgx_ick@b10                       ti,wait-gate-clock              G                   ]                      cpefuse_fck@a08                       ti,gate-clock               "           
        ]                      ts_fck@a08                        ti,gate-clock               H           
        ]                     usbtll_fck@a08                        ti,wait-gate-clock                         
        ]                     dss_ick_3430es2@e10                       ti,omap3-dss-interface-clock                I                   ]                      usbhost_120m_fck@1400                         ti,gate-clock                                   ]                     usbhost_48m_fck@1400                          ti,dss-gate-clock               9                    ]                      usbhost_ick@1410                          ti,omap3-dss-interface-clock                I                   ]                         clockdomains       core_l3_clkdm             ti,clockdomain                       dpll3_clkdm           ti,clockdomain                    dpll1_clkdm           ti,clockdomain                    per_clkdm             ti,clockdomain        l                                                                                          emu_clkdm             ti,clockdomain              *      dpll4_clkdm           ti,clockdomain                     wkup_clkdm            ti,clockdomain        $                                    dss_clkdm             ti,clockdomain                                core_l4_clkdm             ti,clockdomain                                                                                                                                cam_clkdm             ti,clockdomain                       iva2_clkdm            ti,clockdomain                    dpll2_clkdm           ti,clockdomain              |      d2d_clkdm             ti,clockdomain                          dpll5_clkdm           ti,clockdomain                    sgx_clkdm             ti,clockdomain                    usbhost_clkdm             ti,clockdomain                                target-module@48320000            ti,sysc-omap2 ti,sysc            H2     H2          	  rev sysc            #                   _            fck ick                      +               H2        counter@0             ti,omap-counter32k                            interrupt-controller@48200000             ti,omap3-intc            *                    H                        target-module@48056000            ti,sysc-omap2 ti,sysc            H`    H`,   H`(           rev sysc syss             #        B                  #                  1               [         ick                      +               H`       dma-controller@0              ti,omap3630-sdma ti,omap-sdma                                                P           [            h   `                     gpio@48310000             ti,omap3-gpio            H1                          gpio1            u                             *                            gpio@49050000             ti,omap3-gpio            I                          gpio2                                *                            gpio@49052000             ti,omap3-gpio            I                          gpio3                                *                 gpio@49054000             ti,omap3-gpio            I@                          gpio4                                *                 gpio@49056000             ti,omap3-gpio            I`                !         gpio5                                *                            gpio@49058000             ti,omap3-gpio            I                "         gpio6                                *                 serial@4806a000           ti,omap3-uart            H                   H        >      1      2        Ctx rx            uart1           Ml         zdefault                  serial@4806c000           ti,omap3-uart            H                  I        >      3      4        Ctx rx            uart2           Ml         zdefault                  serial@49020000           ti,omap3-uart            I                   J        >      5      6        Ctx rx            uart3           Ml         zdefault                  i2c@48070000              ti,omap3-i2c             H                 8                     +             i2c1            zdefault                    M '@   twl@48              H                                  ti,twl4030           *                   zdefault                  audio             ti,twl4030-audio       codec            rtc           ti,twl4030-rtc                    bci           ti,twl4030-bci              	                                    vac       watchdog              ti,twl4030-wdt        regulator-vaux1           ti,twl4030-vaux1          regulator-vaux2           ti,twl4030-vaux2          regulator-vaux3           ti,twl4030-vaux3          regulator-vaux4           ti,twl4030-vaux4          regulator-vdd1            ti,twl4030-vdd1          	'                regulator-vdac            ti,twl4030-vdac          w@         w@      regulator-vio             ti,twl4030-vio        regulator-vintana1            ti,twl4030-vintana1       regulator-vintana2            ti,twl4030-vintana2       regulator-vintdig             ti,twl4030-vintdig        regulator-vmmc1           ti,twl4030-vmmc1             :         0                  regulator-vmmc2           ti,twl4030-vmmc2             :         0      regulator-vusb1v5             ti,twl4030-vusb1v5                    regulator-vusb1v8             ti,twl4030-vusb1v8                    regulator-vusb3v1             ti,twl4030-vusb3v1                    regulator-vpll1           ti,twl4030-vpll1          regulator-vpll2           ti,twl4030-vpll2             w@         w@      regulator-vsim            ti,twl4030-vsim          w@         -                  gpio              ti,twl4030-gpio                              *                                      twl4030-usb           ti,twl4030-usb              
                                 
                      !                     pwm           ti,twl4030-pwm          ,         pwmled            ti,twl4030-pwmled           ,         pwrbutton             ti,twl4030-pwrbutton                      keypad            ti,twl4030-keypad                       7           G         madc              ti,twl4030-madc                     Z                           i2c@48072000              ti,omap3-i2c             H                 9                     +             i2c2          i2c@48060000              ti,omap3-i2c             H                 =                     +             i2c3            zdefault                  mailbox@48094000              ti,omap3-mailbox             mailbox          H	@                        l           x                 mbox-dsp                                                    spi@48098000              ti,omap2-mcspi           H	                A                     +             mcspi1                   @  >      #      $      %      &      '      (      )      *         Ctx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3       spi@4809a000              ti,omap2-mcspi           H	                B                     +             mcspi2                      >      +      ,      -      .        Ctx0 rx0 tx1 rx1       spi@480b8000              ti,omap2-mcspi           H                [                     +             mcspi3                      >                                Ctx0 rx0 tx1 rx1       spi@480ba000              ti,omap2-mcspi           H                0                     +             mcspi4                     >      F      G        Ctx0 rx0       1w@480b2000           ti,omap3-1w          H                 :         hdq1w         mmc@4809c000              ti,omap3-hsmmc           H	                S         mmc1                     >      =      >        Ctx rx                      zdefault                                                                      mmc@480b4000              ti,omap3-hsmmc           H@                V         mmc2            >      /      0        Ctx rx           zdefault                                  	                             mmc@480ad000              ti,omap3-hsmmc           H
                ^         mmc3            >      M      N        Ctx rx         	  "disabled          mmu@480bd400            )              ti,omap2-iommu           H                         mmu_isp         6                    mmu@5d000000            )              ti,omap2-iommu           ]                           mmu_iva       	  "disabled          wdt@48314000              ti,omap3-wdt             H1@          
   wd_timer2         mcbsp@48074000            ti,omap3-mcbsp           H@            mpu                ;   <        Fcommon tx rx            V            mcbsp1          >                     Ctx rx                        fck       	  "disabled          target-module@480a0000            ti,sysc-omap2 ti,sysc            H
 <   H
 @   H
 D           rev sysc syss                      #               1                        ick                      +               H
         rng@0             ti,omap2-rng                                 4         mcbsp@49022000            ti,omap3-mcbsp           I     I            mpu sidetone                   >   ?           Fcommon tx rx sidetone           V            mcbsp2 mcbsp2_sidetone          >      !      "        Ctx rx                           fck ick         "okay            zdefault                             mcbsp@49024000            ti,omap3-mcbsp           I@    I            mpu sidetone                   Y   Z           Fcommon tx rx sidetone           V            mcbsp3 mcbsp3_sidetone          >                    Ctx rx                           fck ick       	  "disabled          mcbsp@49026000            ti,omap3-mcbsp           I`            mpu                6   7        Fcommon tx rx            V            mcbsp4          >                    Ctx rx                        fck         e          	  "disabled          mcbsp@48096000            ti,omap3-mcbsp           H	`            mpu                Q   R        Fcommon tx rx            V            mcbsp5          >                    Ctx rx                       fck       	  "disabled          sham@480c3000             ti,omap3-sham            sham             H0    d            1        >      E        Crx        target-module@48318000            ti,sysc-omap2-timer ti,sysc          H1    H1   H1           rev sysc syss             '        #                  1                          fck ick                      +               H1             v            timer@0           ti,omap3430-timer                                       fck             %                              H         target-module@49032000            ti,sysc-omap2-timer ti,sysc          I     I    I            rev sysc syss             '        #                  1                          fck ick                      +               I        timer@0           ti,omap3430-timer                               &         timer@49034000            ti,omap3430-timer            I@                '         timer3        timer@49036000            ti,omap3430-timer            I`                (         timer4        timer@49038000            ti,omap3430-timer            I                )         timer5                 timer@4903a000            ti,omap3430-timer            I                *         timer6                 timer@4903c000            ti,omap3430-timer            I                +         timer7                 timer@4903e000            ti,omap3430-timer            I                ,         timer8                          timer@49040000            ti,omap3430-timer            I                 -         timer9                 timer@48086000            ti,omap3430-timer            H`                .         timer10                timer@48088000            ti,omap3430-timer            H                /         timer11                target-module@48304000            ti,sysc-omap2-timer ti,sysc          H0@    H0@   H0@           rev sysc syss             '        #                  1                          fck ick                      +               H0@       timer@0           ti,omap3430-timer                               _                           usbhstll@48062000             ti,usbhs-tll             H                 N         usb_tll_hs        usbhshost@48064000            ti,usbhs-host            H@             usb_host_hs                      +                  	  ehci-phy       ohci@48064400             ti,ohci-omap3            HD                L                ehci@48064800             ti,ehci-omap             HH                M                       gpmc@6e000000             ti,omap3430-gpmc             gpmc             n                         >              Crxtx                       )                        +            *                                       zdefault                           0                    nand@0,0              ti,omap2-nand                                                                  ;micron,mt29c4g96maz         J           Y           kbch8            {                           ,           ,                      "           ,           (           6           @            R        1   R        B   (        T                         +           "okay          onenand@0,0           ti,omap2-onenand                                 l         {                                              Y                                     `           `                                                        `                       `            r        1   r           Z                               -            G            _           T           B   Z        {  .                     +         	  "disabled             target-module@480ab000            ti,sysc-omap2 ti,sysc            H
    H
   H
           rev sysc syss                      B                  #                  1            fck                      +               H
                   usb@0             ti,omap3-musb                               \   ]        Fmc dma          v                                                               	  usb2-phy                          2         dss@48050000              ti,omap3-dss             H           	  "disabled          	   dss_core                         fck                      +               dispc@48050400            ti,omap3-dispc           H                      
   dss_dispc                        fck       encoder@4804fc00              ti,omap3-dsi             H    H    @H             proto phy pll                     	  "disabled          	   dss_dsi1                            fck sys_clk                      +          encoder@48050800              ti,omap3-rfbi            H          	  "disabled          	   dss_rfbi                            fck ick       encoder@48050c00              ti,omap3-venc            H          	  "disabled          	   dss_venc                            fck tv_dac_clk           ssi-controller@48058000           ti,omap3-ssi             ssi         "okay             H    H            sys gdd             G        Fgdd_mpu                      +                          	  
          ssi_ssr_fck ssi_sst_fck ssi_ick    ssi-port@4805a000             ti,omap3-ssi-port            H    H            tx rx               C   D      ssi-port@4805b000             ti,omap3-ssi-port            H    H            tx rx               E   F         serial@49042000           ti,omap3-uart            I                 P        >      Q      R        Ctx rx            uart4           Ml       regulator-abb-mpu         
    ti,abb-v1           abb_mpu_iva                       +             H0r   H0h           base-address int-address                           "                            `   s                     O                     7                                                          pinmux@480025a0            ti,omap3-padconf pinctrl-single          H %   \                     +            
                       *        ?           ]          zdefault              hsusb2-core2-pins         0     P      R      T     V     X     Z                   leds-core2-pins            @                       isp@480bc000              ti,omap3-isp             H   H                                               	                 ports                        +             bandgap@48002524             H %$             ti,omap36xx-bandgap         	                     target-module@480cb000            ti,sysc-omap3630-sr ti,sysc          smartreflex_core             H8           sysc                       #                              fck                      +               H       smartreflex@0             ti,omap3-smartreflex-core                                        target-module@480c9000            ti,sysc-omap3630-sr ti,sysc          smartreflex_mpu_iva          H8           sysc                       #                              fck                      +               H       smartreflex@480c9000              ti,omap3-smartreflex-mpu-iva                                         target-module@50000000            ti,sysc-omap4 ti,sysc            P     P          	  rev sysc            B                  #                                 fck ick                      +               P         gpu@0         #    ti,omap3630-gpu img,powervr-sgx530                                          opp-table             operating-points-v2-ti-cpu                            opp-50-300000000            	(             	/ s s s s s s        	=            	N      opp-100-600000000           	(    #F         	/ O O O O O O        	=         opp-130-800000000           	(    /         	/ 7 7 7 7 7 7        	=         opp-1000000000          	(    ;         	/              	=            	Z         opp-supply            ti,omap-opp-supply          	e       thermal-zones      cpu-thermal         	           	          	      N         	     trips      cpu_alert           	 8        	           passive                  cpu_crit            	 _        	        	   critical             cooling-maps       map0            	          	                 memory@80000000          memory                        sound             ti,omap-twl4030         	igep2           	        regulator-vdd33           regulator-fixed         vdd33            	      gpio_leds         
    gpio-leds           zdefault              user0           
omap3:red:user0                          
off       user1           
omap3:green:user1                            
off       user2           
omap3:red:user1                         
off       boot            
omap3:green:boot                             
on           hsusb2-phy-pins           usb-nop-xceiv           
&                !                     fixedregulator-mmcsdio            regulator-fixed         vmmcsdio_fixed           2Z         2Z                  mmc2_pwrseq           mmc-pwrseq-simple           
&             
                        	compatible interrupt-parent #address-cells #size-cells model stdout-path i2c0 i2c1 i2c2 mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 device_type reg clocks clock-names clock-latency operating-points-v2 vbb-supply #cooling-cells phandle interrupts ti,hwmods ranges #pinctrl-cells #interrupt-cells interrupt-controller pinctrl-single,register-width pinctrl-single,function-mask pinctrl-names pinctrl-0 pinctrl-single,pins syscon regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells clock-output-names reg-names ti,sysc-mask ti,sysc-sidle ti,syss-mask dmas dma-names clock-frequency ti,bit-shift ti,max-div ti,index-starts-at-one clock-mult clock-div ti,set-bit-to-disable ti,clock-mult ti,clock-div ti,set-rate-parent ti,index-power-of-two ti,dividers ti,low-power-stop ti,lock ti,low-power-bypass #ssize-cells ti,sysc-midle #dma-cells dma-channels dma-requests ti,gpio-always-on gpio-controller #gpio-cells interrupts-extended bci3v1-supply io-channels io-channel-names ti,use-leds usb1v5-supply usb1v8-supply usb3v1-supply usb_mode #phy-cells #pwm-cells keypad,num-rows keypad,num-columns #io-channel-cells #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,spi-num-cs ti,dual-volt pbias-supply vmmc-supply vmmc_aux-supply bus-width cd-gpios mmc-pwrseq non-removable status #iommu-cells ti,#tlb-entries interrupt-names ti,buffer-size #sound-dai-cells ti,no-reset-on-init ti,no-idle ti,timer-alwon assigned-clocks assigned-clock-parents ti,timer-dsp ti,timer-pwm ti,timer-secure port2-mode remote-wakeup-connected phys gpmc,num-cs gpmc,num-waitpins linux,mtd-name nand-bus-width gpmc,device-width ti,nand-ecc-opt gpmc,sync-clk-ps gpmc,cs-on-ns gpmc,cs-rd-off-ns gpmc,cs-wr-off-ns gpmc,adv-on-ns gpmc,adv-rd-off-ns gpmc,adv-wr-off-ns gpmc,we-off-ns gpmc,oe-off-ns gpmc,access-ns gpmc,rd-cycle-ns gpmc,wr-cycle-ns gpmc,wr-access-ns gpmc,wr-data-mux-bus-ns gpmc,sync-read gpmc,sync-write gpmc,burst-length gpmc,burst-wrap gpmc,burst-read gpmc,burst-write gpmc,mux-add-data gpmc,oe-on-ns gpmc,we-on-ns gpmc,page-burst-access-ns gpmc,bus-turnaround-ns gpmc,cycle2cycle-delay-ns gpmc,wait-monitoring-ns gpmc,clk-activation-ns multipoint num-eps ram-bits interface-type usb-phy phy-names power ti,tranxdone-status-mask ti,settling-time ti,clock-cycles ti,abb_info iommus ti,phy-type #thermal-sensor-cells opp-hz opp-microvolt opp-supported-hw opp-suspend turbo-mode ti,absolute-max-voltage-uv polling-delay-passive polling-delay coefficients thermal-sensors temperature hysteresis trip cooling-device ti,model ti,mcbsp regulator-always-on label default-state reset-gpios 