  eI   8  ]   (              ]p                                                      #   itead,sonoff-ihost rockchip,rv1109           &            7Sonoff iHost 2G    aliases          =/i2c@ff3f0000            B/i2c@ff400000            G/i2c@ff520000            L/serial@ff560000             T/serial@ff410000             \/serial@ff570000             d/serial@ff580000             l/serial@ff590000             t/serial@ff5a0000             |/ethernet@ffc40000           /mmc@ffc50000            /mmc@ffc70000            /mmc@ffc60000         cpus                                 cpu@f00          cpu          arm,cortex-a7                        psci                                                 cpu@f01          cpu          arm,cortex-a7                       psci                                                    arm-pmu          arm,cortex-a7-pmu                   {          |                        psci             arm,psci-1.0             smc       timer            arm,armv7-timer       0                                 
           n6       display_subsystem            rockchip,display-subsystem                    oscillator           fixed-clock          n6         xin24m                          (      syscon@fe000000       &   rockchip,rv1126-grf syscon simple-mfd                              '      syscon@fe020000       )   rockchip,rv1126-pmugrf syscon simple-mfd                                 io-domains        &   rockchip,rv1126-pmu-io-voltage-domain           !okay            (           6           D   	        R   
        `           n           |   	           	                    qos@fe860000             rockchip,rv1126-qos syscon                                   qos@fe860080             rockchip,rv1126-qos syscon                                  qos@fe860200             rockchip,rv1126-qos syscon                                  qos@fe86c000             rockchip,rv1126-qos syscon                                  qos@fe8a0000             rockchip,rv1126-qos syscon                                   qos@fe8a0080             rockchip,rv1126-qos syscon                                  qos@fe8a0100             rockchip,rv1126-qos syscon                                  qos@fe8a0180             rockchip,rv1126-qos syscon                                 interrupt-controller@feff0000            arm,gic-400                                                       @     `                    	                    power-management@ff3e0000         &   rockchip,rv1126-pmu syscon simple-mfd            >        power-controller          !   rockchip,rv1126-power-controller                                                     D   power-domain@15                   8               r            u                  v                                   power-domain@16                                  o                             power-domain@10             
      P                     Z                                         [                                            i2c@ff3f0000          (   rockchip,rv1126-i2c rockchip,rk3399-i2c          ?                                                        !      	  i2c pclk             default                                              !okay                 pmic@20          rockchip,rk809                        &               	                      rk808-clkout1 rk808-clkout2          default                              9        G           S           _           k           w                                                           b   regulators     DCDC_REG1           vdd_npu_vepu                                          	         ~        /  q   regulator-state-mem          D         DCDC_REG2           vdd_arm                                                p        /  q               regulator-state-mem          D         DCDC_REG3           vcc_ddr                                 regulator-state-mem          ]         DCDC_REG4           vcc3v3_sys                                        2Z         2Z               regulator-state-mem          ]        u 2Z         DCDC_REG5         
  vcc_buck5                              !         !               regulator-state-mem          ]        u !         LDO_REG1            vcc_0v8                            5          5    regulator-state-mem          D         LDO_REG2            vcc1v8_pmu                             w@         w@               regulator-state-mem          ]        u w@         LDO_REG3            vcc0v8_pmu                             5          5    regulator-state-mem          ]        u 5          LDO_REG4            vcc_1v8                            w@         w@            	   regulator-state-mem          ]        u w@         LDO_REG5          
  vcc_dovdd                              w@         w@               regulator-state-mem          D         LDO_REG6          	  vcc_dvdd             O         O   regulator-state-mem          D         LDO_REG7          	  vcc_avdd             *         *   regulator-state-mem          D         LDO_REG8          	  vccio_sd                               w@         2Z            
   regulator-state-mem          D         LDO_REG9          
  vcc3v3_sd                              2Z         2Z               regulator-state-mem          D         SWITCH_REG1         vcc_5v0       SWITCH_REG2         vcc_3v3                               I               i2c@ff400000          (   rockchip,rv1126-i2c rockchip,rk3399-i2c          @                                                        "      	  i2c pclk             default                                              !okay                 rtc@51           nxp,pcf8563             Q                     &                          xin32k           serial@ff410000       &   rockchip,rv1126-uart snps,dw-apb-uart            A                                 n6                               baudclk apb_pclk                                tx rx            default                                        	  !disabled          pwm@ff430000          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          C           	  pwm pclk                         #         default                             	  !disabled          pwm@ff430010          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          C          	  pwm pclk                         #         default                              	  !disabled          pwm@ff430020          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          C           	  pwm pclk                         #         default            !                 	  !disabled          pwm@ff430030          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          C 0         	  pwm pclk                         #         default            "                 	  !disabled          pwm@ff440000          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          D           	  pwm pclk                         $         default            #                 	  !disabled          pwm@ff440010          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          D          	  pwm pclk                         $         default            $                 	  !disabled          pwm@ff440020          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          D           	  pwm pclk                         $         default            %                 	  !disabled          pwm@ff440030          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          D 0         	  pwm pclk                         $         default            &                 	  !disabled          clock-controller@ff480000            rockchip,rv1126-pmucru           H                '                                        clock-controller@ff490000            rockchip,rv1126-cru          I                 (        xin24m             '                                        dma-controller@ff4e0000          arm,pl330 arm,primecell          N    @                                                                       	  apb_pclk                      i2c@ff520000          (   rockchip,rv1126-i2c rockchip,rk3399-i2c          R                                       "            	  i2c pclk             default            )                                           	  !disabled          pwm@ff550000          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          U           	  pwm pclk                   '                *         default                  	  !disabled          pwm@ff550010          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          U          	  pwm pclk                   '                +         default                  	  !disabled          pwm@ff550020          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          U           	  pwm pclk                   '                ,         default                  	  !disabled          pwm@ff550030          (   rockchip,rv1126-pwm rockchip,rk3328-pwm          U 0         	  pwm pclk                   '                -         default                  	  !disabled          serial@ff560000       &   rockchip,rv1126-uart snps,dw-apb-uart            V                                 n6                              baudclk apb_pclk                                tx rx            default            .   /   0                              !okay                bluetooth            realtek,rtl8723ds-bt               1                  1                   1               0          default            2   3   4         serial@ff570000       &   rockchip,rv1126-uart snps,dw-apb-uart            W                                 n6                              baudclk apb_pclk                  	              tx rx            default            5                              !okay          serial@ff580000       &   rockchip,rv1126-uart snps,dw-apb-uart            X                                 n6                              baudclk apb_pclk                        
        tx rx            default            6                              !okay          serial@ff590000       &   rockchip,rv1126-uart snps,dw-apb-uart            Y                                 n6                              baudclk apb_pclk                                tx rx            default            7                              !okay          serial@ff5a0000       &   rockchip,rv1126-uart snps,dw-apb-uart            Z                                 n6                               baudclk apb_pclk                                tx rx            default            8                            	  !disabled          adc@ff5e0000          .   rockchip,rv1126-saradc rockchip,rk3399-saradc            ^                     (           :                  ,     
        saradc apb_pclk         L      ;        Ssaradc-apb          !okay            _   	      timer@ff660000        ,   rockchip,rv1126-timer rockchip,rk3288-timer          f                                             -        pclk timer        i2s@ff800000             rockchip,rv1126-i2s-tdm                               .                  =      A              mclk_tx mclk_rx hclk                                tx rx            default       (     9   :   ;   <   =   >   ?   @   A   B        L      c      d      
  Stx-m rx-m              '        k          	  !disabled          vop@ffb00000             rockchip,rv1126-vop               
                    ;           aclk_vop dclk_vop hclk_vop                                     Saxi ahb dclk            L                          |   C           D   
      	  !disabled       port                                             endpoint@0                     endpoint@1                          iommu@ffb00f00           rockchip,iommu                               ;           aclk iface                                              D   
      	  !disabled                C      ethernet@ffc40000         &   rockchip,rv1126-gmac snps,dwmac-4.20a                @                 _          `           macirq eth_wake_irq            '      @         ~                                               T  stmmaceth mac_clk_rx mac_clk_tx clk_mac_ref aclk_mac pclk_mac clk_mac_speed ptp_ref         L            
  Sstmmaceth                                E           F           G        !okay                  }      ~                    |      }              %            :output          G   H        Rrmii            [   I         default            J   K   L   M   mdio             snps,dwmac-mdio                              ethernet-phy@0           ethernet-phy-ieee802.3-c22                        default            N         f        w  P          '           O                  H         stmmac-axi-config                                                                      E      rx-queues-config                           F   queue0           tx-queues-config                           G   queue0              mmc@ffc50000          0   rockchip,rv1126-dw-mshc rockchip,rk3288-dw-mshc              @                 N                         r      s      t        biu ciu ciu-drive ciu-sample                                   D           !okay                                 0         ?         default            P   Q   R   S        M   Z        k   I        w   	      mmc@ffc60000          0   rockchip,rv1126-dw-mshc rockchip,rk3288-dw-mshc              @                 L                         l      m      n        biu ciu ciu-drive ciu-sample                                !okay                                                     default            T   U   V   W        M   Z                                   w   
      mmc@ffc70000          0   rockchip,rv1126-dw-mshc rockchip,rk3288-dw-mshc              @                 M                         o      p      q        biu ciu ciu-drive ciu-sample                                  D           !okay                                                     X         ?         default            Y   Z   [        M   Z                 k           w   	      spi@ffc90000             rockchip,sfc                 @                 P                 v        %Ĵ         clk_sfc hclk_sfc                   v                 D         	  !disabled          pinctrl          rockchip,rv1126-pinctrl            '        
                                        gpio@ff460000            rockchip,gpio-bank           F                     "                  &                       .                                         gpio@ff620000            rockchip,gpio-bank           b                     #                       (                 .                                   1      gpio@ff630000            rockchip,gpio-bank           c                     $                       )                 .                                   O      gpio@ff640000            rockchip,gpio-bank           d                     %                       *                 .                             gpio@ff650000            rockchip,gpio-bank           e                     &                 	      +                 .                             pcfg-pull-up             :            _      pcfg-pull-down           G            ^      pcfg-pull-none           V            \      pcfg-pull-none-drv-level-3           V        c               a      pcfg-pull-up-drv-level-2             :        c               ]      pcfg-pull-none-drv-level-0-smt           V        c             r            `      clk_out_ethernet          emmc       emmc-rstnout                        \            S      emmc-bus8                        ]             ]             ]             ]             ]             ]             ]             ]            P      emmc-clk                         ]            R      emmc-cmd                         ]            Q         fspi          i2c0       i2c0-xfer                         `             `                     i2c2       i2c2-xfer                         `             `                     i2c3       i2c3m0-xfer                      \            \            )         i2s0       i2s0m0-lrck-tx                      \            <      i2s0m0-lrck-rx                      \            =      i2s0m0-mclk                     \            ;      i2s0m0-sclk-rx                      \            :      i2s0m0-sclk-tx                      \            9      i2s0m0-sdi0                     \            >      i2s0m0-sdo0                     \            ?      i2s0m0-sdo1-sdi3                        \            @      i2s0m0-sdo2-sdi2                         \            A      i2s0m0-sdo3-sdi1                        \            B      i2s0m1-lrck-tx                      \      i2s0m1-lrck-rx                
      \      i2s0m1-mclk                     \      i2s0m1-sclk-rx                	      \      i2s0m1-sclk-tx                      \      i2s0m1-sdi0                     \      i2s0m1-sdo0                     \      i2s0m1-sdo1-sdi3                        \      i2s0m1-sdo2-sdi2                        \      i2s0m1-sdo3-sdi1                        \         pwm0       pwm0m0-pins                      \                     pwm1       pwm1m0-pins                      \                      pwm2       pwm2m0-pins                      \            !         pwm3       pwm3m0-pins                      \            "         pwm4       pwm4m0-pins                      \            #         pwm5       pwm5m0-pins                      \            $         pwm6       pwm6m0-pins                
      \            %         pwm7       pwm7m0-pins                	      \            &         pwm8       pwm8m0-pins                     \            *         pwm9       pwm9m0-pins                     \            +         pwm10      pwm10m0-pins                        \            ,         pwm11      pwm11m0-pins                        \            -         rgmii      rgmiim1-miim                         \            \            J      rgmiim1-rxer                        \            K      rgmiim1-bus2          `              \            \            \            a            a            a            L      rgmiim1-mclkinout                       \            M         sdmmc0     sdmmc0-bus4       @              ]            ]            ]            ]            V      sdmmc0-clk                      ]            T      sdmmc0-cmd                	      ]            U      sdmmc0-det                       \            W         sdmmc1     sdmmc1-bus4       @              ]            ]            ]            ]            [      sdmmc1-clk                
      ]            Y      sdmmc1-cmd                      ]            Z         uart0      uart0-xfer                       _            _            .      uart0-ctsn                      \            /      uart0-rtsn                      \            0         uart1      uart1m0-xfer                          _             _                     uart2      uart2m1-xfer                         _            _            5         uart3      uart3m2-xfer                         _             _            6         uart4      uart4m2-xfer                         _            _            7         uart5      uart5m0-xfer                         _            _            8         ethernet       eth-phy-rst                      ^            N         bt     bt-enable                        \            2      bt-wake-dev                      \            3      bt-wake-host                         \            4         pmic       pmic-int-l                 	       _                     wifi       wifi-enable-h                        \            c            chosen          serial2:1500000n8         regulator-vcc5v0-sys             regulator-fixed         vcc5v0_sys                             LK@         LK@                  pwrseq-sdio          mmc-pwrseq-simple               b         
  ext_clock            default            c           1                  X         	#address-cells #size-cells compatible interrupt-parent model i2c0 i2c2 i2c3 serial0 serial1 serial2 serial3 serial4 serial5 ethernet0 mmc0 mmc1 mmc2 device_type reg enable-method clocks cpu-supply phandle interrupts interrupt-affinity clock-frequency ports clock-output-names #clock-cells status pmuio0-supply pmuio1-supply vccio1-supply vccio2-supply vccio3-supply vccio4-supply vccio5-supply vccio6-supply vccio7-supply interrupt-controller #interrupt-cells #power-domain-cells pm_qos rockchip,grf clock-names pinctrl-names pinctrl-0 rockchip,system-power-controller wakeup-source vcc1-supply vcc2-supply vcc3-supply vcc4-supply vcc5-supply vcc6-supply vcc7-supply vcc8-supply vcc9-supply regulator-name regulator-always-on regulator-boot-on regulator-initial-mode regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-off-in-suspend regulator-on-in-suspend regulator-suspend-microvolt dmas dma-names reg-shift reg-io-width #pwm-cells #reset-cells #dma-cells arm,pl330-periph-burst uart-has-rtscts device-wake-gpios enable-gpios host-wake-gpios max-speed #io-channel-cells resets reset-names vref-supply #sound-dai-cells iommus power-domains #iommu-cells interrupt-names snps,mixed-burst snps,tso snps,axi-config snps,mtl-rx-config snps,mtl-tx-config assigned-clocks assigned-clock-parents assigned-clock-rates clock_in_out phy-handle phy-mode phy-supply reset-active-low reset-assert-us reset-deassert-us reset-gpios snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,tx-queues-to-use fifo-depth max-frequency bus-width cap-mmc-highspeed mmc-hs200-1_8v non-removable rockchip,default-sample-phase vmmc-supply vqmmc-supply cap-sd-highspeed card-detect-delay sd-uhs-sdr12 sd-uhs-sdr25 sd-uhs-sdr104 cap-sdio-irq keep-power-in-suspend mmc-pwrseq sd-uhs-sdr50 rockchip,pmu ranges gpio-controller #gpio-cells bias-pull-up bias-pull-down bias-disable drive-strength input-schmitt-enable rockchip,pins stdout-path 