Ðþí  Kí   H  G   (            Ñ  FÔ                                                                        Novetech Chameleon96          7   !novtech,chameleon96 altr,socfpga-cyclone5 altr,socfpga     aliases          ,/soc/serial@ffc02000             4/soc/serial@ffc03000             </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000          cpus                                       Xaltr,socfpga-smp       cpu@0            !arm,cortex-a9            fcpu          r             v            ‡         cpu@1            !arm,cortex-a9            fcpu          r            v            ‡            pmu@ff111000             !arm,cortex-a9-pmu                                °          ±            «               rÿ    ÿ0          interrupt-controller@fffed000            !arm,cortex-a9-gic            ¾             Ï         rÿþÐ    ÿþÁ             ‡         soc                                   !simple-bus           fsoc                       ä   amba             !simple-bus                                     ä   pdma@ffe01000            !arm,pl330 arm,primecell          rÿà          `           h          i          j          k          l          m          n          o            ë            ö         	   ýapb_pclk            	      <        dma          ‡   4         base_fpga_region             !fpga-region                                           can@ffc00000             !bosch,d_can          rÿÀ           0           ƒ          „          …          †            ö           	      7      	  %disabled          can@ffc01000             !bosch,d_can          rÿÀ          0           ‡          ˆ          ‰          Š            ö   	        	      8      	  %disabled          clkmgr@ffd04000          !altr,clk-mgr             rÿÐ@       clocks                               osc1            ,             !fixed-clock         9}x@         ‡   
      osc2            ,             !fixed-clock          ‡         f2s_periph_ref_clk          ,             !fixed-clock          ‡         f2s_sdram_ref_clk           ,             !fixed-clock          ‡         main_pll@40                                   ,             !altr,socfpga-pll-clock           ö   
         r   @         ‡      mpuclk@48           ,             !altr,socfpga-perip-clk           ö           I   à       	         r   H         ‡         mainclk@4c          ,             !altr,socfpga-perip-clk           ö           I   ä       	         r   L         ‡         dbg_base_clk@50         ,             !altr,socfpga-perip-clk           ö      
        I   è       	         r   P         ‡         main_qspi_clk@54            ,             !altr,socfpga-perip-clk           ö            r   T         ‡         main_nand_sdmmc_clk@58          ,             !altr,socfpga-perip-clk           ö            r   X         ‡         cfg_h2f_usr0_clk@5c         ,             !altr,socfpga-perip-clk           ö            r   \         ‡            periph_pll@80                                     ,             !altr,socfpga-pll-clock           ö   
               r   €         ‡      emac0_clk@88            ,             !altr,socfpga-perip-clk           ö            r   ˆ         ‡         emac1_clk@8c            ,             !altr,socfpga-perip-clk           ö            r   Œ         ‡         per_qsi_clk@90          ,             !altr,socfpga-perip-clk           ö            r            ‡          per_nand_mmc_clk@94         ,             !altr,socfpga-perip-clk           ö            r   ”         ‡         per_base_clk@98         ,             !altr,socfpga-perip-clk           ö            r   ˜         ‡         h2f_usr1_clk@9c         ,             !altr,socfpga-perip-clk           ö            r   œ         ‡            sdram_pll@c0                                      ,             !altr,socfpga-pll-clock           ö   
               r   À         ‡      ddr_dqs_clk@c8          ,             !altr,socfpga-perip-clk           ö            r   È         ‡   !      ddr_2x_dqs_clk@cc           ,             !altr,socfpga-perip-clk           ö            r   Ì         ‡   "      ddr_dq_clk@d0           ,             !altr,socfpga-perip-clk           ö            r   Ð         ‡   #      h2f_usr2_clk@d4         ,             !altr,socfpga-perip-clk           ö            r   Ô         ‡   $         mpu_periph_clk          ,             !altr,socfpga-perip-clk           ö           Q            ‡   3      mpu_l2_ram_clk          ,             !altr,socfpga-perip-clk           ö           Q         l4_main_clk         ,             !altr,socfpga-gate-clk            ö           _   `             ‡         l3_main_clk         ,             !altr,socfpga-perip-clk           ö           Q         l3_mp_clk           ,             !altr,socfpga-gate-clk            ö           I   d               _   `            ‡         l3_sp_clk           ,             !altr,socfpga-gate-clk            ö           I   d            l4_mp_clk           ,             !altr,socfpga-gate-clk            ö              I   d              _   `            ‡   )      l4_sp_clk           ,             !altr,socfpga-gate-clk            ö              I   d              _   `            ‡   *      dbg_at_clk          ,             !altr,socfpga-gate-clk            ö           I   h               _   `            ‡         dbg_clk         ,             !altr,socfpga-gate-clk            ö           I   h              _   `         dbg_trace_clk           ,             !altr,socfpga-gate-clk            ö           I   l               _   `         dbg_timer_clk           ,             !altr,socfpga-gate-clk            ö           _   `         cfg_clk         ,             !altr,socfpga-gate-clk            ö           _   `         h2f_user0_clk           ,             !altr,socfpga-gate-clk            ö           _   `   	      emac_0_clk          ,             !altr,socfpga-gate-clk            ö           _                 ‡   &      emac_1_clk          ,             !altr,socfpga-gate-clk            ö           _                ‡   (      usb_mp_clk          ,             !altr,socfpga-gate-clk            ö           _               I   ¤                ‡   5      spi_m_clk           ,             !altr,socfpga-gate-clk            ö           _               I   ¤               ‡   2      can0_clk            ,             !altr,socfpga-gate-clk            ö           _               I   ¤               ‡         can1_clk            ,             !altr,socfpga-gate-clk            ö           _               I   ¤   	            ‡   	      gpio_db_clk         ,             !altr,socfpga-gate-clk            ö           _               I   ¨             h2f_user1_clk           ,             !altr,socfpga-gate-clk            ö           _             sdmmc_clk           ,             !altr,socfpga-gate-clk            ö                 _                ‡         sdmmc_clk_divided           ,             !altr,socfpga-gate-clk            ö           _               Q            ‡   ,      nand_x_clk          ,             !altr,socfpga-gate-clk            ö                 _       	         ‡         nand_ecc_clk            ,             !altr,socfpga-gate-clk            ö           _       	         ‡   /      nand_clk            ,             !altr,socfpga-gate-clk            ö           _       
        Q            ‡   .      qspi_clk            ,             !altr,socfpga-gate-clk            ö                  _                ‡   0      ddr_dqs_clk_gate            ,             !altr,socfpga-gate-clk            ö   !        _   Ø          ddr_2x_dqs_clk_gate         ,             !altr,socfpga-gate-clk            ö   "        _   Ø         ddr_dq_clk_gate         ,             !altr,socfpga-gate-clk            ö   #        _   Ø         h2f_user2_clk           ,             !altr,socfpga-gate-clk            ö   $        _   Ø               fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           rÿ@             	      a         ö         	  %disabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             rÿP             	      `         ö         	  %disabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             rÿ`             	      b         ö         	  %disabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           rÿÂP€         	  %disabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            rÿp`    ÿ¹                      ¯            ‡         stmmac-axi-config           h           x           ˆ                                    ‡   '      ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         ’   %   `             rÿp                       s           ¥macirq          µ                 ö   &      
   ýstmmaceth           	             
  stmmaceth           Á           Ü   €        ø                         '      	  %disabled          ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         ’   %   `            rÿp                       x           ¥macirq          µ                 ö   (      
   ýstmmaceth           	      !      
  stmmaceth           Á           Ü   €        ø                         '      	  %disabled          gpio@ff708000                                      !snps,dw-apb-gpio             rÿp€             ö   )        	      9        %okay       gpio-controller@0            !snps,dw-apb-gpio-port            $        4           @            r              Ï         ¾                    ¤            ‡   7         gpio@ff709000                                      !snps,dw-apb-gpio             rÿp             ö   )        	      :        %okay       gpio-controller@0            !snps,dw-apb-gpio-port            $        4           @            r              Ï         ¾                    ¥            ‡   8         gpio@ff70a000                                      !snps,dw-apb-gpio             rÿp              ö   )        	      ;      	  %disabled       gpio-controller@0            !snps,dw-apb-gpio-port            $        4           @            r              Ï         ¾                    ¦            i2c@ffc04000                                       !snps,designware-i2c          rÿÀ@            	      ,         ö   *                 ž           %okay            NLS-I2C0       i2c@ffc05000                                       !snps,designware-i2c          rÿÀP            	      -         ö   *                 Ÿ           %okay            NLS-I2C1       i2c@ffc06000                                       !snps,designware-i2c          rÿÀ`            	      .         ö   *                             %okay          i2c@ffc07000                                       !snps,designware-i2c          rÿÀp            	      /         ö   *                 ¡           %okay            NHS-I2C2       eccmgr           !altr,socfpga-ecc-manager                                       ä   l2-ecc@ffd08140          !altr,socfpga-l2-ecc          rÿÐ@                    $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           rÿÐD           T   +                 ²          ³            cache-controller@fffef000            !arm,pl310-cache          rÿþð                     &            Y        g           s                 ƒ                 ”           ¢            ±        Å           Ù            ò                                   ‡         l3regs@ff800000          !altr,l3regs syscon           rÿ€           mmc@ff704000             !altr,socfpga-dw-mshc             rÿp@                     ‹           û                                      ö   )   ,         ýbiu ciu         	      6        ’   %             %okay             1        ;            E         W        h       ‡        x   -        „   -      nand-controller@ff900000                                       !altr,socfpga-denali-nand             rÿ     ÿ¸             ‘nand_data denali_reg                                 ö   .      /         ýnand nand_x ecc         	      $      	  %disabled          sram@ffff0000         
   !mmio-sram            rÿÿ              ‡   +      spi@ff705000          !   !intel,socfpga-qspi cdns,qspi-nor                                       rÿpP    ÿ                       —           ›   €        «           »             ö   0        	      %      	  %disabled          rstmgr@ffd05000         Ð            !altr,rst-mgr             rÿÐP            Ý            ‡         snoop-control-unit@fffec000          !arm,cortex-a9-scu            rÿþÀ          sdr@ffc25000             !altr,sdr-ctl syscon          rÿÂP            	      =         ‡   1      sdramedac            !altr,sdram-edac         ð   1                 '         spi@fff00000             !snps,dw-apb-ssi                                    rÿð                      š                        ö   2        	      2        spi         %okay            NHS-SPI1       spi@fff01000             !snps,dw-apb-ssi                                    rÿð                     ›                        ö   2        	      3        spi         %okay            NLS-SPI0       sysmgr@ffd08000          !altr,sys-mgr syscon          rÿÐ€   @         ÿÐ€Ä         ‡   %      timer@fffec600           !arm,cortex-a9-twd-timer          rÿþÆ                               ö   3      timer0@ffc08000          !snps,dw-apb-timer                    §            rÿÀ€             ö   *         ýtimer           	      *        timer         timer1@ffc09000          !snps,dw-apb-timer                    ¨            rÿÀ             ö   *         ýtimer           	      +        timer         timer2@ffd00000          !snps,dw-apb-timer                    ©            rÿÐ              ö   
         ýtimer           	      (        timer         timer3@ffd01000          !snps,dw-apb-timer                    ª            rÿÐ             ö   
         ýtimer           	      )        timer         serial@ffc02000          !snps,dw-apb-uart             rÿÀ                      ¢                      !            ö   *        .   4      4           3tx rx           	      0      	  NLS-UART1            %okay          serial@ffc03000          !snps,dw-apb-uart             rÿÀ0                     £                      !            ö   *        .   4      4           3tx rx           	      1      	  NLS-UART0            %okay          usbphy          =             !usb-nop-xceiv           %okay             ‡   6      usb@ffb00000          
   !snps,dwc2            rÿ°    ÿÿ                 }            ö   5         ýotg         	      "        dwc2            H   6      	  Musb2-phy          	  %disabled          usb@ffb40000          
   !snps,dwc2            rÿ´    ÿÿ                 €            ö   5         ýotg         	      #        dwc2            H   6      	  Musb2-phy            %okay          watchdog@ffd02000            !snps,dw-wdt          rÿÐ                      «            ö   
        	      &        %okay          watchdog@ffd03000            !snps,dw-wdt          rÿÐ0                     ¬            ö   
        	      '      	  %disabled             chosen          Wearlyprintk         `serial0:115200n8          memory@0             fmemory           r              regulator            !regulator-fixed         l3.3V            { 2Z         “ 2Z          ‡   -      leds          
   !gpio-leds      user_led1           Ngreen:user1         H   7            
  «heartbeat         user_led2           Ngreen:user2         H   7              «mmc0          user_led3           Ngreen:user3         H   7              «none          user_led4           Ngreen:user4         H   8               Á        «none                	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate snps,wr_osr_lmt snps,rd_osr_lmt snps,blen altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth snps,axi-config gpio-controller #gpio-cells snps,nr-gpios label iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed clk-phase-sd-hs vmmc-supply vqmmc-supply reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names bootargs stdout-path regulator-name regulator-min-microvolt regulator-max-microvolt linux,default-trigger panic-indicator 