Šžķ  JĪ   H  Eä   (            ź  E                                                                        Aries/DENX MCV EVK        /   !denx,mcvevk altr,socfpga-cyclone5 altr,socfpga     aliases          ,/soc/serial@ffc02000             4/soc/serial@ffc03000             </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000             X/soc/ethernet@ff700000           b/soc/i2c@ffc04000/stmpe811@41         cpus                                       maltr,socfpga-smp       cpu@0            !arm,cortex-a9            {cpu                                            cpu@1            !arm,cortex-a9            {cpu                                              pmu@ff111000             !arm,cortex-a9-pmu            ¤            µ       °          ±            Ą               ’    ’0          interrupt-controller@fffed000            !arm,cortex-a9-gic            Ó             ä         ’žŠ    ’žĮ                      soc                                   !simple-bus           {soc          ¤             ł   amba             !simple-bus                                     ł   pdma@ffe01000            !arm,pl330 arm,primecell          ’ą          `   µ       h          i          j          k          l          m          n          o                                	  apb_pclk                  <        %dma             4         base_fpga_region             !fpga-region         1                                  can@ffc00000             !bosch,d_can          ’Ą           0   µ                                                                 7        :okay          can@ffc01000             !bosch,d_can          ’Ą          0   µ                                                   	              8        :okay          clkmgr@ffd04000          !altr,clk-mgr             ’Š@       clocks                               osc1            A             !fixed-clock         N}x@            
      osc2            A             !fixed-clock                   f2s_periph_ref_clk          A             !fixed-clock                   f2s_sdram_ref_clk           A             !fixed-clock                   main_pll@40                                   A             !altr,socfpga-pll-clock             
            @               mpuclk@48           A             !altr,socfpga-perip-clk                     ^   ą       	            H                  mainclk@4c          A             !altr,socfpga-perip-clk                     ^   ä       	            L                  dbg_base_clk@50         A             !altr,socfpga-perip-clk                
        ^   č       	            P                  main_qspi_clk@54            A             !altr,socfpga-perip-clk                         T                  main_nand_sdmmc_clk@58          A             !altr,socfpga-perip-clk                         X                  cfg_h2f_usr0_clk@5c         A             !altr,socfpga-perip-clk                         \                     periph_pll@80                                     A             !altr,socfpga-pll-clock             
                                 emac0_clk@88            A             !altr,socfpga-perip-clk                                           emac1_clk@8c            A             !altr,socfpga-perip-clk                                           per_qsi_clk@90          A             !altr,socfpga-perip-clk                                            per_nand_mmc_clk@94         A             !altr,socfpga-perip-clk                                           per_base_clk@98         A             !altr,socfpga-perip-clk                                           h2f_usr1_clk@9c         A             !altr,socfpga-perip-clk                                              sdram_pll@c0                                      A             !altr,socfpga-pll-clock             
                  Ą               ddr_dqs_clk@c8          A             !altr,socfpga-perip-clk                         Č            !      ddr_2x_dqs_clk@cc           A             !altr,socfpga-perip-clk                         Ģ            "      ddr_dq_clk@d0           A             !altr,socfpga-perip-clk                         Š            #      h2f_usr2_clk@d4         A             !altr,socfpga-perip-clk                         Ō            $         mpu_periph_clk          A             !altr,socfpga-perip-clk                     f               3      mpu_l2_ram_clk          A             !altr,socfpga-perip-clk                     f         l4_main_clk         A             !altr,socfpga-gate-clk                      t   `                      l3_main_clk         A             !altr,socfpga-perip-clk                     f         l3_mp_clk           A             !altr,socfpga-gate-clk                      ^   d               t   `                     l3_sp_clk           A             !altr,socfpga-gate-clk                      ^   d            l4_mp_clk           A             !altr,socfpga-gate-clk                         ^   d              t   `               )      l4_sp_clk           A             !altr,socfpga-gate-clk                         ^   d              t   `               *      dbg_at_clk          A             !altr,socfpga-gate-clk                      ^   h               t   `                     dbg_clk         A             !altr,socfpga-gate-clk                      ^   h              t   `         dbg_trace_clk           A             !altr,socfpga-gate-clk                      ^   l               t   `         dbg_timer_clk           A             !altr,socfpga-gate-clk                      t   `         cfg_clk         A             !altr,socfpga-gate-clk                      t   `         h2f_user0_clk           A             !altr,socfpga-gate-clk                      t   `   	      emac_0_clk          A             !altr,socfpga-gate-clk                      t                    &      emac_1_clk          A             !altr,socfpga-gate-clk                      t                   (      usb_mp_clk          A             !altr,socfpga-gate-clk                      t               ^   ¤                   5      spi_m_clk           A             !altr,socfpga-gate-clk                      t               ^   ¤                  2      can0_clk            A             !altr,socfpga-gate-clk                      t               ^   ¤                        can1_clk            A             !altr,socfpga-gate-clk                      t               ^   ¤   	               	      gpio_db_clk         A             !altr,socfpga-gate-clk                      t               ^   Ø             h2f_user1_clk           A             !altr,socfpga-gate-clk                      t             sdmmc_clk           A             !altr,socfpga-gate-clk                            t                         sdmmc_clk_divided           A             !altr,socfpga-gate-clk                      t               f               -      nand_x_clk          A             !altr,socfpga-gate-clk                            t       	                  nand_ecc_clk            A             !altr,socfpga-gate-clk                      t       	            /      nand_clk            A             !altr,socfpga-gate-clk                      t       
        f               .      qspi_clk            A             !altr,socfpga-gate-clk                             t                   0      ddr_dqs_clk_gate            A             !altr,socfpga-gate-clk              !        t   Ų          ddr_2x_dqs_clk_gate         A             !altr,socfpga-gate-clk              "        t   Ų         ddr_dq_clk_gate         A             !altr,socfpga-gate-clk              #        t   Ų         h2f_user2_clk           A             !altr,socfpga-gate-clk              $        t   Ų               fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           ’@                   a                 	  :disabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             ’P                   `                 	  :disabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             ’`                   b                 	  :disabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           ’ĀP         	  :disabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            ’p`    ’¹              µ       Æ                     stmmac-axi-config           }                                                             '      ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         §   %   `             ’p               µ       s           ŗmacirq          Ź                   &      
  stmmaceth                        
  %stmmaceth           Ö           ń                                 )   '        :okay            9rgmii         ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         §   %   `            ’p               µ       x           ŗmacirq          Ź                   (      
  stmmaceth                 !      
  %stmmaceth           Ö           ń                                 )   '      	  :disabled          gpio@ff708000                                      !snps,dw-apb-gpio             ’p               )              9        :okay       gpio-controller@0            !snps,dw-apb-gpio-port            B        R           ^                          ä         Ó            µ       ¤            gpio@ff709000                                      !snps,dw-apb-gpio             ’p               )              :        :okay       gpio-controller@0            !snps,dw-apb-gpio-port            B        R           ^                          ä         Ó            µ       „               +         gpio@ff70a000                                      !snps,dw-apb-gpio             ’p                )              ;        :okay       gpio-controller@0            !snps,dw-apb-gpio-port            B        R           ^                          ä         Ó            µ       ¦            i2c@ffc04000                                       !snps,designware-i2c          ’Ą@                  ,           *         µ                  :okay            N     stmpe811@41          !st,stmpe811                                       A        l            o           v   +         stmpe_touchscreen            !st,stmpe-ts                                           ¤           °           ¼           Ļ           Ū           é               i2c@ffc05000                                       !snps,designware-i2c          ’ĄP                  -           *         µ                	  :disabled          i2c@ffc06000                                       !snps,designware-i2c          ’Ą`                  .           *         µ                 	  :disabled          i2c@ffc07000                                       !snps,designware-i2c          ’Ąp                  /           *         µ       ”         	  :disabled          eccmgr           !altr,socfpga-ecc-manager                                       ł   l2-ecc@ffd08140          !altr,socfpga-l2-ecc          ’Š@            µ       $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           ’ŠD           ō   ,         µ       ²          ³            cache-controller@fffef000            !arm,pl310-cache          ’žš             µ       &            ł                                    #                 4           B            Q        e           y                       «            ½                     l3regs@ff800000          !altr,l3regs syscon           ’           mmc@ff704000             !altr,socfpga-dw-mshc             ’p@             µ                                                          )   -        biu ciu               6        §   %             :okay             Ń        Ū            å         ÷                     nand-controller@ff900000                                       !altr,socfpga-denali-nand             ’     ’ø             nand_data denali_reg             µ                     .      /        nand nand_x ecc               $      	  :disabled          sram@ffff0000         
   !mmio-sram            ’’                 ,      spi@ff705000          !   !intel,socfpga-qspi cdns,qspi-nor                                       ’pP    ’               µ                  "           2           B               0              %      	  :disabled          rstmgr@ffd05000         W            !altr,rst-mgr             ’ŠP            d                     snoop-control-unit@fffec000          !arm,cortex-a9-scu            ’žĄ          sdr@ffc25000             !altr,sdr-ctl syscon          ’ĀP                  =            1      sdramedac            !altr,sdram-edac         w   1         µ       '         spi@fff00000             !snps,dw-apb-ssi                                    ’š              µ                                2              2        %spi       	  :disabled          spi@fff01000             !snps,dw-apb-ssi                                    ’š             µ                                2              3        %spi       	  :disabled          sysmgr@ffd08000          !altr,sys-mgr syscon          ’Š   @         ’ŠÄ            %      timer@fffec600           !arm,cortex-a9-twd-timer          ’žĘ             µ                   3      timer0@ffc08000          !snps,dw-apb-timer            µ       §            ’Ą               *        timer                 *        %timer         timer1@ffc09000          !snps,dw-apb-timer            µ       Ø            ’Ą               *        timer                 +        %timer         timer2@ffd00000          !snps,dw-apb-timer            µ       ©            ’Š                
        timer                 (        %timer         timer3@ffd01000          !snps,dw-apb-timer            µ       Ŗ            ’Š               
        timer                 )        %timer         serial@ffc02000          !snps,dw-apb-uart             ’Ą              µ       ¢                      Ø              *        µ   4      4           ŗtx rx                 0        :okay          serial@ffc03000          !snps,dw-apb-uart             ’Ą0             µ       £                      Ø              *        µ   4      4           ŗtx rx                 1      usbphy          Ä             !usb-nop-xceiv           :okay                6      usb@ffb00000          
   !snps,dwc2            ’°    ’’         µ       }              5        otg               "        %dwc2            Ļ   6      	  Ōusb2-phy          	  :disabled          usb@ffb40000          
   !snps,dwc2            ’“    ’’         µ                     5        otg               #        %dwc2            Ļ   6      	  Ōusb2-phy            :okay          watchdog@ffd02000            !snps,dw-wdt          ’Š              µ       «              
              &        :okay          watchdog@ffd03000            !snps,dw-wdt          ’Š0             µ       ¬              
              '      	  :disabled             memory@0             {memory               @         chosen          Žserial0:115200n8             	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 ethernet0 stmpe-i2c0 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate snps,wr_osr_lmt snps,rd_osr_lmt snps,blen altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth snps,axi-config phy-mode gpio-controller #gpio-cells snps,nr-gpios id blocks irq-gpio ts,sample-time ts,mod-12b ts,ref-sel ts,adc-freq ts,ave-ctrl ts,touch-det-delay ts,settling ts,fraction-z ts,i-drive iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed clk-phase-sd-hs reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names stdout-path 