  H   8  DX   (            :  D                                                          Altera SOCFPGA VT            !altr,socfpga-vt altr,socfpga       aliases          ,/soc/serial@ffc02000             4/soc/serial@ffc03000             </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000          cpus                                       Xaltr,socfpga-smp       cpu@0            !arm,cortex-a9            fcpu          r             v                     cpu@1            !arm,cortex-a9            fcpu          r            v                        pmu@ff111000             !arm,cortex-a9-pmu                                                                    r    0          interrupt-controller@fffed000            !arm,cortex-a9-gic                                  r                          soc                                   !simple-bus           fsoc                          amba             !simple-bus                                        pdma@ffe01000            !arm,pl330 arm,primecell          r          `          h          i          j          k          l          m          n          o                                 	   apb_pclk            	      <        dma             3         base_fpga_region             !fpga-region                                           can@ffc00000             !bosch,d_can          r           0                                                               	      7      	  %disabled          can@ffc01000             !bosch,d_can          r          0                                                       	        	      8      	  %disabled          clkmgr@ffd04000          !altr,clk-mgr             r@       clocks                               osc1            ,             !fixed-clock         9             
      osc2            ,             !fixed-clock                   f2s_periph_ref_clk          ,             !fixed-clock                   f2s_sdram_ref_clk           ,             !fixed-clock                   main_pll@40                                   ,             !altr,socfpga-pll-clock              
         r   @               mpuclk@48           ,             !altr,socfpga-perip-clk                      I          	         r   H                  mainclk@4c          ,             !altr,socfpga-perip-clk                      I          	         r   L                  dbg_base_clk@50         ,             !altr,socfpga-perip-clk                 
        I          	         r   P                  main_qspi_clk@54            ,             !altr,socfpga-perip-clk                       r   T                  main_nand_sdmmc_clk@58          ,             !altr,socfpga-perip-clk                       r   X                  cfg_h2f_usr0_clk@5c         ,             !altr,socfpga-perip-clk                       r   \                     periph_pll@80                                     ,             !altr,socfpga-pll-clock              
               r                  emac0_clk@88            ,             !altr,socfpga-perip-clk                       r                     emac1_clk@8c            ,             !altr,socfpga-perip-clk                       r                     per_qsi_clk@90          ,             !altr,socfpga-perip-clk                       r                      per_nand_mmc_clk@94         ,             !altr,socfpga-perip-clk                       r                     per_base_clk@98         ,             !altr,socfpga-perip-clk                       r                     h2f_usr1_clk@9c         ,             !altr,socfpga-perip-clk                       r                        sdram_pll@c0                                      ,             !altr,socfpga-pll-clock              
               r                  ddr_dqs_clk@c8          ,             !altr,socfpga-perip-clk                       r               !      ddr_2x_dqs_clk@cc           ,             !altr,socfpga-perip-clk                       r               "      ddr_dq_clk@d0           ,             !altr,socfpga-perip-clk                       r               #      h2f_usr2_clk@d4         ,             !altr,socfpga-perip-clk                       r               $         mpu_periph_clk          ,             !altr,socfpga-perip-clk                      Q               2      mpu_l2_ram_clk          ,             !altr,socfpga-perip-clk                      Q         l4_main_clk         ,             !altr,socfpga-gate-clk                       _   `                      l3_main_clk         ,             !altr,socfpga-perip-clk                      Q         l3_mp_clk           ,             !altr,socfpga-gate-clk                       I   d               _   `                     l3_sp_clk           ,             !altr,socfpga-gate-clk                       I   d            l4_mp_clk           ,             !altr,socfpga-gate-clk                          I   d              _   `               )      l4_sp_clk           ,             !altr,socfpga-gate-clk                          I   d              _   `               *      dbg_at_clk          ,             !altr,socfpga-gate-clk                       I   h               _   `                     dbg_clk         ,             !altr,socfpga-gate-clk                       I   h              _   `         dbg_trace_clk           ,             !altr,socfpga-gate-clk                       I   l               _   `         dbg_timer_clk           ,             !altr,socfpga-gate-clk                       _   `         cfg_clk         ,             !altr,socfpga-gate-clk                       _   `         h2f_user0_clk           ,             !altr,socfpga-gate-clk                       _   `   	      emac_0_clk          ,             !altr,socfpga-gate-clk                       _                   &      emac_1_clk          ,             !altr,socfpga-gate-clk                       _                  (      usb_mp_clk          ,             !altr,socfpga-gate-clk                       _              I                      4      spi_m_clk           ,             !altr,socfpga-gate-clk                       _              I                     1      can0_clk            ,             !altr,socfpga-gate-clk                       _              I                           can1_clk            ,             !altr,socfpga-gate-clk                       _              I      	               	      gpio_db_clk         ,             !altr,socfpga-gate-clk                       _              I                h2f_user1_clk           ,             !altr,socfpga-gate-clk                       _            sdmmc_clk           ,             !altr,socfpga-gate-clk                             _                        sdmmc_clk_divided           ,             !altr,socfpga-gate-clk                       _              Q               ,      nand_x_clk          ,             !altr,socfpga-gate-clk                             _      	                  nand_ecc_clk            ,             !altr,socfpga-gate-clk                       _      	            .      nand_clk            ,             !altr,socfpga-gate-clk                       _      
        Q               -      qspi_clk            ,             !altr,socfpga-gate-clk                              _                  /      ddr_dqs_clk_gate            ,             !altr,socfpga-gate-clk               !        _             ddr_2x_dqs_clk_gate         ,             !altr,socfpga-gate-clk               "        _            ddr_dq_clk_gate         ,             !altr,socfpga-gate-clk               #        _            h2f_user2_clk           ,             !altr,socfpga-gate-clk               $        _                  fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           r@             	      a                  	  %disabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             rP             	      `                  	  %disabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             r`             	      b                  	  %disabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           rP         	  %disabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            rp`                                              stmmac-axi-config           h           x                                                  '      ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac            %   `             rp                      s           macirq                              &      
   stmmaceth           	             
  stmmaceth                                                          '        %okay            $gmii          ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac            %   `            rp                      x           macirq                              (      
   stmmaceth           	      !      
  stmmaceth                                                          '      	  %disabled          gpio@ff708000                                      !snps,dw-apb-gpio             rp                )        	      9      	  %disabled       gpio-controller@0            !snps,dw-apb-gpio-port            -        =           I            r                                                      gpio@ff709000                                      !snps,dw-apb-gpio             rp                )        	      :      	  %disabled       gpio-controller@0            !snps,dw-apb-gpio-port            -        =           I            r                                                      gpio@ff70a000                                      !snps,dw-apb-gpio             rp                )        	      ;      	  %disabled       gpio-controller@0            !snps,dw-apb-gpio-port            -        =           I            r                                                      i2c@ffc04000                                       !snps,designware-i2c          r@            	      ,            *                         	  %disabled          i2c@ffc05000                                       !snps,designware-i2c          rP            	      -            *                         	  %disabled          i2c@ffc06000                                       !snps,designware-i2c          r`            	      .            *                         	  %disabled          i2c@ffc07000                                       !snps,designware-i2c          rp            	      /            *                         	  %disabled          eccmgr           !altr,socfpga-ecc-manager                                          l2-ecc@ffd08140          !altr,socfpga-l2-ecc          rЁ@                   $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           rЁD           W   +                                      cache-controller@fffef000            !arm,pl310-cache          r                    &            \        j           v                                                                                                                                     l3regs@ff800000          !altr,l3regs syscon           r           mmc@ff704000             !altr,socfpga-dw-mshc             rp@                                                                        )   ,         biu ciu         	      6           %           	  %disabled             4        >            H         Z      nand-controller@ff900000                                       !altr,socfpga-denali-nand             r                  knand_data denali_reg                                   -      .         nand nand_x ecc         	      $      	  %disabled          sram@ffff0000         
   !mmio-sram            r                 +      spi@ff705000          !   !intel,socfpga-qspi cdns,qspi-nor                                       rpP                                    u                                      /        	      %      	  %disabled          rstmgr@ffd05000                     !altr,rst-mgr             rP                                 snoop-control-unit@fffec000          !arm,cortex-a9-scu            r          sdr@ffc25000             !altr,sdr-ctl syscon          rP            	      =            0      sdramedac            !altr,sdram-edac            0                '         spi@fff00000             !snps,dw-apb-ssi                                    r                                               1        	      2        spi       	  %disabled          spi@fff01000             !snps,dw-apb-ssi                                    r                                              1        	      3        spi       	  %disabled          sysmgr@ffd08000          !altr,sys-mgr syscon          rЀ   @         Ѐ            %      timer@fffec600           !arm,cortex-a9-twd-timer          r                                 2      timer0@ffc08000          !snps,dw-apb-timer                               r                *         timer           	      *        timer           9 j      timer1@ffc09000          !snps,dw-apb-timer                               r                *         timer           	      +        timer           9 j      timer2@ffd00000          !snps,dw-apb-timer                               r                 
         timer           	      (        timer           9 j      timer3@ffd01000          !snps,dw-apb-timer                               r                
         timer           	      )        timer           9 j      serial@ffc02000          !snps,dw-apb-uart             r                                                          *           3      3           tx rx           	      0        9 p       serial@ffc03000          !snps,dw-apb-uart             r0                                                         *           3      3           tx rx           	      1        9 p       usbphy                       !usb-nop-xceiv           %okay                5      usb@ffb00000          
   !snps,dwc2            r                    }               4         otg         	      "        dwc2            "   5      	  'usb2-phy          	  %disabled          usb@ffb40000          
   !snps,dwc2            r                                   4         otg         	      #        dwc2            "   5      	  'usb2-phy          	  %disabled          watchdog@ffd02000            !snps,dw-wdt          r                                    
        	      &      	  %disabled          watchdog@ffd03000            !snps,dw-wdt          r0                                   
        	      '      	  %disabled             chosen          1console=ttyS0,57600       memory@0             fmemory           r    @            	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate snps,wr_osr_lmt snps,rd_osr_lmt snps,blen altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth snps,axi-config phy-mode gpio-controller #gpio-cells snps,nr-gpios iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names bootargs 