8<( google,veyron-mickey-rev8google,veyron-mickey-rev7google,veyron-mickey-rev6google,veyron-mickey-rev5google,veyron-mickey-rev4google,veyron-mickey-rev3google,veyron-mickey-rev2google,veyron-mickey-rev1google,veyron-mickey-rev0google,veyron-mickeygoogle,veyronrockchip,rk3288&7Google Mickeyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbopp-table-0operating-points-v2jbopp-126000000u| opp-216000000u | opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ|opp-1608000000u_"| opp-1704000000ue|popp-1800000000ukI|\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр 5Drvbiuciuciu-driveciu-sample  @'reset 3disabledmmc@ff0d0000rockchip,rk3288-dw-mshcр 5Eswbiuciuciu-driveciu-sample ! @'reset3okay:DUbx default mmc@ff0e0000rockchip,rk3288-dw-mshcр 5Ftxbiuciuciu-driveciu-sample "@'reset 3disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр 5Guybiuciuciu-driveciu-sample #@'reset3okay: '2xdefault saradc@ff100000rockchip,saradc $A5I[saradcapb_pclkW 'saradc-apb 3disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclkS  Xtxrx ,default 3disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclkS Xtxrx -default 3disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclkSXtxrx .default !"#3okayb flash@0jedec,spi-norui2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault$3okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault% 3disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault& 3disabled2,i2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault' 3disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkSXtxrxdefault ()*3okaybluetoothdefault +,-brcm,bcm43540-bt . . .-$serial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkSXtxrxdefault/3okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault03okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkSXtxrxdefault1 3disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkS  Xtxrxdefault2 3disableddma-controller@ff250000arm,pl330arm,primecell%@;Fa5 apb_pclkbthermal-zonesreserve-thermalx3cpu-thermalxd3tripscpu_crit_ criticalcpu_alert_almost_warmpassivecpu_alert_warmpassiveb4cpu_alert_almost_hot8passiveb6cpu_alert_hot@Ppassiveb7cpu_alert_hotterH passiveb8cpu_alert_very_hotLpassiveb9cooling-mapscpu_warm_limit_cpu40cpu_warm_limit_gpu4 5cpu_almost_hot_limit_cpu60cpu_hot_limit_cpu70cpu_hotter_limit_cpu80cpu_very_hot_limit_cpu90cpu_very_hot_limit_gpu9 5gpu-thermalxd3tripsgpu_crit_ criticalgpu_alert_warmish`passiveb:gpu_alert_warmpassiveb;gpu_alert_hotterH passiveb<gpu_alert_very_very_hotOpassiveb=cooling-mapsgpu_warmish_limit_gpu: 5gpu_warm_limit_cpu;0gpu_hotter_limit_gpu< 5gpu_very_very_hot_limit_gpu= 5tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk 'tsadc-apbinitdefaultsleep>?>@H3okay%<b3ethernet@ff290000rockchip,rk3288-gmac)Wmacirqeth_wake_irq@85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 'stmmaceth 3disabledusb@ff500000 generic-ehciP 5gAlusb 3disabledvusb@ff520000 generic-ohciR )5gAlusb 3disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghostgB lusb2-phy 3disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otghost@@ gC lusb2-phy3okayzCusb@ff5c0000 generic-ehci\ 5 3disableddma-controller@ff600000arm,pl330arm,primecell`@;Fa5 apb_pclk 3disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5LdefaultD3okay2dpmic@1brockchip,rk808xin32kwifibt_32kin&Edefault FGH:HT`lxIJ JbregulatorsDCDC_REG1vdd_arm q qb regulator-state-mem.DCDC_REG2vdd_gpu 5qb{regulator-state-mem.DCDC_REG3 vcc135_ddrregulator-state-memGDCDC_REG4vcc_18w@w@bregulator-state-memG_w@LDO_REG3vdd_10B@B@regulator-state-memG_B@LDO_REG7 vdd10_lcdB@B@{SWITCH_REG1 vcc33_lcdb^regulator-state-mem.LDO_REG8w@w@ vcc18_lcd{i2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultK 3disabled2 pwm@ff680000rockchip,rk3288-pwmhdefaultL5_ 3disabledpwm@ff680010rockchip,rk3288-pwmhdefaultM5_3okaybpwm@ff680020rockchip,rk3288-pwmh defaultN5_ 3disabledpwm@ff680030rockchip,rk3288-pwmh0defaultO5_ 3disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerh bbpower-domain@9 5chgfdehilkj$PQRSTUVWXpower-domain@11 5opYZpower-domain@12 5[power-domain@13 5\]reboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5 xin24m@Hjk$ #gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb@edp-phyrockchip,rk3288-dp-phy5h24m 3disabledbrio-domains"rockchip,rk3288-io-voltage-domain3okay*I4?MI]Ik^wusbphyrockchip,rk3288-usb-phy3okayusb-phy@320 5]phyclk 'phy-resetbCusb-phy@33445^phyclk 'phy-resetbAusb-phy@348H5_phyclk 'phy-resetbBwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O3okaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif5T mclkhclkS_Xtx 6default`@ 3disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 55Ri2s_clki2s_hclkS__Xtxrxdefaulta3okaybcrypto@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk 'crypto-rstiommu@ff900800rockchip,iommu@ 5 aclkiface 3disablediommu@ff914000rockchip,iommu @P 5 aclkiface 3disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclkb ilm 'coreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopb def 'axiahbdclkc3okayportb endpoint@0 dbwendpoint@1 ebsendpoint@2 fbmendpoint@3 gbpiommu@ff930300rockchip,iommu 5 aclkifaceb 3okaybcvop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopb  'axiahbdclkh 3disabledportb endpoint@0 ibxendpoint@1 jbtendpoint@2 kbnendpoint@3 lbqiommu@ff940300rockchip,iommu 5 aclkifaceb  3disabledbhmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclkb @ 3disabledportsportendpoint@0 mbfendpoint@1 nbklvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcob @ 3disabledportsport@0endpoint@0 pbgendpoint@1 qbldp@ff970000rockchip,rk3288-dp@ b5icdppclkgrldpo'dp@ 3disabledportsport@0endpoint@0 sbeendpoint@1 tbjhdmi@ff980000rockchip,rk3288-dw-hdmi@ g5hmniahbisfrcecb 3okaydefaultunwedgeuvbportsportendpoint@0 wbdendpoint@1 xbivideo-codec@ff9a0000rockchip,rk3288-vpu   Wvepuvdpu5 aclkhclkyb iommu@ff9a0800rockchip,iommu 5 aclkifaceb byiommu@ff9c0440rockchip,iommu @@@ o5 aclkiface 3disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ Wjobmmugpu5zb 3okay {b5opp-table-1operating-points-v2bzopp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000rockchip,rk3288-qossyscon b\qos@ffaa0080rockchip,rk3288-qossyscon b]qos@ffad0000rockchip,rk3288-qossyscon bQqos@ffad0100rockchip,rk3288-qossyscon bRqos@ffad0180rockchip,rk3288-qossyscon bSqos@ffad0400rockchip,rk3288-qossyscon bTqos@ffad0480rockchip,rk3288-qossyscon bUqos@ffad0500rockchip,rk3288-qossyscon bPqos@ffad0800rockchip,rk3288-qossyscon bVqos@ffad0880rockchip,rk3288-qossyscon bWqos@ffad0900rockchip,rk3288-qossyscon bXqos@ffae0000rockchip,rk3288-qossyscon b[qos@ffaf0000rockchip,rk3288-qossyscon bYqos@ffaf0080rockchip,rk3288-qossyscon bZdma-controller@ffb20000arm,pl330arm,primecell@;Fa5 apb_pclkb_efuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400 " 7@ @ `   bpinctrlrockchip,rk3288-pinctrl@default |}~gpio@ff750000rockchip,gpio-banku Q5@ H X " 7| dPMIC_SLEEP_APPMIC_INT_LPOWER_BUTTON_LRECOVERY_SW_LOT_RESETAP_WARM_RESET_HI2C0_SDA_PMICI2C0_SCL_PMICnFALUTbEgpio@ff780000rockchip,gpio-bankx R5A H X " 7gpio@ff790000rockchip,gpio-banky S5B H X " 70 dCONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_Lbgpio@ff7a0000rockchip,gpio-bankz T5C H X " 7 dFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank{ U5D H X " 7 dUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEb.gpio@ff7c0000rockchip,gpio-bank| V5E H X " 7gpio@ff7d0000rockchip,gpio-bank} W5F H X " 7gpio@ff7e0000rockchip,gpio-bank~ X5G H X " 7 dPWM_LOGTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LCPU_NMIDVSOKHDMI_WAKEPOWER_HDMI_ONDVS1DVS2HDMI_CECI2C5_SDA_HDMII2C5_SCL_HDMIUART2_RXDUART2_TXDbJgpio@ff7f0000rockchip,gpio-bank Y5H H X " 7^ dRAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 thdmi-cec-c7 thdmi-ddc tbuhdmi-ddc-unwedge tbvpower-hdmi-on t bpcfg-output-low bpcfg-pull-up bpcfg-pull-down bpcfg-pull-none bpcfg-pull-none-12ma  bsuspendglobal-pwroff tb~ddrio-pwroff tb}ddr0-retention tb|ddr1-retention tedpedp-hpd t i2c0i2c0-xfer tbDi2c1i2c1-xfer tb$i2c2i2c2-xfer t  bKi2c3i2c3-xfer tb%i2c4i2c4-xfer tb&i2c5i2c5-xfer tb'i2s0i2s0-bus` tbalcdclcdc-ctl@ tbosdmmcsdmmc-clk tsdmmc-cmd tsdmmc-cd tsdmmc-bus1 tsdmmc-bus4@ tsdio0sdio0-bus1 tsdio0-bus4@ tbsdio0-cmd tbsdio0-clk tbsdio0-cd tsdio0-wp tsdio0-pwr tsdio0-bkpwr tsdio0-int twifienable-h tbbt-enable-l tb,bt-host-wake tbt-host-wake-l tb+bt-dev-wake-sleep tbt-dev-wake-awake tbt-dev-wake tb-sdio1sdio1-bus1 tsdio1-bus4@ tsdio1-cd tsdio1-wp tsdio1-bkpwr tsdio1-int tsdio1-cmd tsdio1-clk tsdio1-pwr t emmcemmc-clk tbemmc-cmd tbemmc-pwr t emmc-bus1 temmc-bus4@ temmc-bus8 tbemmc-reset t bspi0spi0-clk t bspi0-cs0 t bspi0-tx tbspi0-rx tbspi0-cs1 tspi1spi1-clk t bspi1-cs0 t bspi1-rx tbspi1-tx tbspi2spi2-cs1 tspi2-clk tb spi2-cs0 tb#spi2-rx tb"spi2-tx t b!uart0uart0-xfer tb(uart0-cts tb)uart0-rts tb*uart1uart1-xfer t b/uart1-cts t uart1-rts t uart2uart2-xfer tb0uart3uart3-xfer tb1uart3-cts t uart3-rts t uart4uart4-xfer tb2uart4-cts t uart4-rts t tsadcotp-pin t b>otp-out t b?pwm0pwm0-pin tbLpwm1pwm1-pin tbMpwm2pwm2-pin tbNpwm3pwm3-pin tbOgmacrgmii-pins t rmii-pins tspdifspdif-tx t b`pcfg-pull-none-drv-8ma  bpcfg-pull-up-drv-8ma  pcfg-output-high bbuttonspwr-key-l tbpmicpmic-int-l tbFdvs-1 t bGdvs-2 tbHrebootap-warm-reset-h t brecovery-switchrec-mode-l t tpmtpm-int-h twrite-protectfw-wp-ap tchosen serial2:115200n8memorymemorypower-button gpio-keysdefaultpower Power E t d:gpio-restart gpio-restart E default emmc-pwrseqmmc-pwrseq-emmcdefault bsdio-pwrseqmmc-pwrseq-simple5 ext_clockdefault .b vcc-5vregulator-fixedvcc_5vLK@LK@ bvcc33-sysregulator-fixed vcc33_sys2Z2Zbvcc50-hdmiregulator-fixed vcc50_hdmi   3J defaultvdd-logicpwm-regulator vdd_logic 8 = H{ \~pvcc33_ioregulator-fixed vcc33_io bIsound!rockchip,rockchip-audio-max98090 oVEYRON-HDMI ~  #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-params#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,hdmi-codecrockchip,i2s-controller