  J   H  E   (              E                                                                        EBV SOCrates          0   !ebv,socrates altr,socfpga-cyclone5 altr,socfpga    aliases          ,/soc/serial0@ffc02000            4/soc/serial1@ffc03000            </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000             X/soc/ethernet@ff702000        cpus                                       baltr,socfpga-smp       cpu@0            !arm,cortex-a9            pcpu          |                                  cpu@1            !arm,cortex-a9            pcpu          |                                    pmu@ff111000             !arm,cortex-a9-pmu                                                                    |    0          interrupt-controller@fffed000            !arm,cortex-a9-gic                                  |                          soc                                   !simple-bus           psoc                          amba             !simple-bus                                        pdma@ffe01000            !arm,pl330 arm,primecell          |          `          h          i          j          k          l          m          n          o                                 	  apb_pclk                  <        dma             2         base_fpga_region             !fpga-region         &                                  can@ffc00000             !bosch,d_can          |           0                                                                     7      	  /disabled          can@ffc01000             !bosch,d_can          |          0                                                       	              8      	  /disabled          clkmgr@ffd04000          !altr,clk-mgr             |@       clocks                               osc1            6             !fixed-clock         C}x@            
      osc2            6             !fixed-clock                   f2s_periph_ref_clk          6             !fixed-clock                   f2s_sdram_ref_clk           6             !fixed-clock                   main_pll@40                                   6             !altr,socfpga-pll-clock              
         |   @               mpuclk@48           6             !altr,socfpga-perip-clk                      S          	         |   H                  mainclk@4c          6             !altr,socfpga-perip-clk                      S          	         |   L                  dbg_base_clk@50         6             !altr,socfpga-perip-clk                 
        S          	         |   P                  main_qspi_clk@54            6             !altr,socfpga-perip-clk                       |   T                  main_nand_sdmmc_clk@58          6             !altr,socfpga-perip-clk                       |   X                  cfg_h2f_usr0_clk@5c         6             !altr,socfpga-perip-clk                       |   \                     periph_pll@80                                     6             !altr,socfpga-pll-clock              
               |                  emac0_clk@88            6             !altr,socfpga-perip-clk                       |                     emac1_clk@8c            6             !altr,socfpga-perip-clk                       |                     per_qsi_clk@90          6             !altr,socfpga-perip-clk                       |                      per_nand_mmc_clk@94         6             !altr,socfpga-perip-clk                       |                     per_base_clk@98         6             !altr,socfpga-perip-clk                       |                     h2f_usr1_clk@9c         6             !altr,socfpga-perip-clk                       |                        sdram_pll@c0                                      6             !altr,socfpga-pll-clock              
               |                  ddr_dqs_clk@c8          6             !altr,socfpga-perip-clk                       |               !      ddr_2x_dqs_clk@cc           6             !altr,socfpga-perip-clk                       |               "      ddr_dq_clk@d0           6             !altr,socfpga-perip-clk                       |               #      h2f_usr2_clk@d4         6             !altr,socfpga-perip-clk                       |               $         mpu_periph_clk          6             !altr,socfpga-perip-clk                      [               1      mpu_l2_ram_clk          6             !altr,socfpga-perip-clk                      [         l4_main_clk         6             !altr,socfpga-gate-clk                       i   `                      l3_main_clk         6             !altr,socfpga-perip-clk                      [         l3_mp_clk           6             !altr,socfpga-gate-clk                       S   d               i   `                     l3_sp_clk           6             !altr,socfpga-gate-clk                       S   d            l4_mp_clk           6             !altr,socfpga-gate-clk                          S   d              i   `               (      l4_sp_clk           6             !altr,socfpga-gate-clk                          S   d              i   `               )      dbg_at_clk          6             !altr,socfpga-gate-clk                       S   h               i   `                     dbg_clk         6             !altr,socfpga-gate-clk                       S   h              i   `         dbg_trace_clk           6             !altr,socfpga-gate-clk                       S   l               i   `         dbg_timer_clk           6             !altr,socfpga-gate-clk                       i   `         cfg_clk         6             !altr,socfpga-gate-clk                       i   `         h2f_user0_clk           6             !altr,socfpga-gate-clk                       i   `   	      emac_0_clk          6             !altr,socfpga-gate-clk                       i                   &      emac_1_clk          6             !altr,socfpga-gate-clk                       i                  '      usb_mp_clk          6             !altr,socfpga-gate-clk                       i              S                      3      spi_m_clk           6             !altr,socfpga-gate-clk                       i              S                     0      can0_clk            6             !altr,socfpga-gate-clk                       i              S                           can1_clk            6             !altr,socfpga-gate-clk                       i              S      	               	      gpio_db_clk         6             !altr,socfpga-gate-clk                       i              S                h2f_user1_clk           6             !altr,socfpga-gate-clk                       i            sdmmc_clk           6             !altr,socfpga-gate-clk                             i              r                         sdmmc_clk_divided           6             !altr,socfpga-gate-clk                       i              [               +      nand_x_clk          6             !altr,socfpga-gate-clk                             i      	                  nand_ecc_clk            6             !altr,socfpga-gate-clk                       i      	            -      nand_clk            6             !altr,socfpga-gate-clk                       i      
        [               ,      qspi_clk            6             !altr,socfpga-gate-clk                              i                  .      ddr_dqs_clk_gate            6             !altr,socfpga-gate-clk               !        i             ddr_2x_dqs_clk_gate         6             !altr,socfpga-gate-clk               "        i            ddr_dq_clk_gate         6             !altr,socfpga-gate-clk               #        i            h2f_user2_clk           6             !altr,socfpga-gate-clk               $        i                  fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           |@                   a                  	  /disabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             |P                   `                  	  /disabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             |`                   b                  	  /disabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           |P         	  /disabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            |p`                                              ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         |   %   `             |p                      s           macirq                              &      
  stmmaceth                        
  stmmaceth                                                     	  /disabled          ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         |   %   `            |p                      x           macirq                              '      
  stmmaceth                 !      
  stmmaceth                                                       /okay            rgmii         gpio@ff708000                                      !snps,dw-apb-gpio             |p                (              9        /okay       gpio-controller@0            !snps,dw-apb-gpio-port                               #            |                                                         5         gpio@ff709000                                      !snps,dw-apb-gpio             |p                (              :        /okay       gpio-controller@0            !snps,dw-apb-gpio-port                               #            |                                                         6         gpio@ff70a000                                      !snps,dw-apb-gpio             |p                (              ;      	  /disabled       gpio-controller@0            !snps,dw-apb-gpio-port                               #            |                                                      i2c@ffc04000                                       !snps,designware-i2c          |@                  ,            )                           /okay       rtc@68        
   !st,m41t82            |   h         i2c@ffc05000                                       !snps,designware-i2c          |P                  -            )                         	  /disabled          i2c@ffc06000                                       !snps,designware-i2c          |`                  .            )                         	  /disabled          i2c@ffc07000                                       !snps,designware-i2c          |p                  /            )                         	  /disabled          eccmgr           !altr,socfpga-ecc-manager                                          l2-ecc@ffd08140          !altr,socfpga-l2-ecc          |Ё@                   $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           |ЁD           1   *                                      cache-controller@fffef000            !arm,pl310-cache          |                    &            6        D           P                 `                 q                                                                                                  l3regs@0xff800000            !altr,l3regs syscon           |           dwmmc0@ff704000          !altr,socfpga-dw-mshc             |p@                                                                        (   +        biu ciu               6        /okay                                 "         4      nand@ff900000                                      !altr,socfpga-denali-nand             |                  Enand_data denali_reg                                   ,      -        nand nand_x ecc               $      	  /disabled          sram@ffff0000         
   !mmio-sram            |                 *      spi@ff705000          !   !intel,socfpga-qspi cdns,qspi-nor                                       |pP                                    O           _           o                .              %        /okay       flash@0                                   !micron,n25q256a jedec,spi-nor            |                                            2           2                              /okay             rstmgr@ffd05000                     !altr,rst-mgr             |P                                 snoop-control-unit@fffec000          !arm,cortex-a9-scu            |          sdr@ffc25000             !altr,sdr-ctl syscon          |P                  =            /      sdramedac            !altr,sdram-edac            /                '         spi@fff00000             !snps,dw-apb-ssi                                    |                                               0              2        spi       	  /disabled          spi@fff01000             !snps,dw-apb-ssi                                    |                                              0              3        spi       	  /disabled          sysmgr@ffd08000          !altr,sys-mgr syscon          |Ѐ   @         $Ѐ            %      timer@fffec600           !arm,cortex-a9-twd-timer          |                                 1      timer0@ffc08000          !snps,dw-apb-timer                               |                )        timer                 *        timer         timer1@ffc09000          !snps,dw-apb-timer                               |                )        timer                 +        timer         timer2@ffd00000          !snps,dw-apb-timer                               |                 
        timer                 (        timer         timer3@ffd01000          !snps,dw-apb-timer                               |                
        timer                 )        timer         serial0@ffc02000             !snps,dw-apb-uart             |                                4           >               )        K   2      2           Ptx rx                 0      serial1@ffc03000             !snps,dw-apb-uart             |0                               4           >               )        K   2      2           Ptx rx                 1      usbphy          Z             !usb-nop-xceiv           /okay                4      usb@ffb00000          
   !snps,dwc2            |                    }               3        otg               "        dwc2            e   4      	  jusb2-phy          	  /disabled          usb@ffb40000          
   !snps,dwc2            |                                   3        otg               #        dwc2            e   4      	  jusb2-phy          	  /disabled          watchdog@ffd02000            !snps,dw-wdt          |                                    
              &        /okay          watchdog@ffd03000            !snps,dw-wdt          |0                                   
              '      	  /disabled             chosen          tearlyprintk         }serial0:115200n8          memory@0             pmemory           |    @         gpio-leds         
   !gpio-leds      led0            led:green:heartbeat         +   5            
  heartbeat         led1            led:green:D7            +   6            led2            led:green:D8            +   6                  	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 ethernet0 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate clk-phase altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth phy-mode gpio-controller #gpio-cells snps,nr-gpios iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address spi-max-frequency m25p,fast-read cdns,read-delay cdns,tshsl-ns cdns,tsd2d-ns cdns,tchsh-ns cdns,tslch-ns #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names bootargs stdout-path label linux,default-trigger 