Šžķ  Tg   H  N<   (            +  Mō                                                                        samtec VIN|ING FPGA       1   !samtec,vining altr,socfpga-cyclone5 altr,socfpga       aliases          ,/soc/serial0@ffc02000            4/soc/serial1@ffc03000            </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000             X/soc/ethernet@ff702000           b/soc/ethernet@ff700000        cpus                                       laltr,socfpga-smp       cpu@0            !arm,cortex-a9            zcpu                                            cpu@1            !arm,cortex-a9            zcpu                                              pmu@ff111000             !arm,cortex-a9-pmu            £            “       °          ±            æ               ’    ’0          interrupt-controller@fffed000            !arm,cortex-a9-gic            Ņ             ć         ’žŠ    ’žĮ                      soc                                   !simple-bus           zsoc          £             ų   amba             !simple-bus                                     ų   pdma@ffe01000            !arm,pl330 arm,primecell          ’ą          `   “       h          i          j          k          l          m          n          o            ’           
         	  apb_pclk                  <        $dma             4         base_fpga_region             !fpga-region         0                                  can@ffc00000             !bosch,d_can          ’Ą           0   “                                                
                 7      	  9disabled          can@ffc01000             !bosch,d_can          ’Ą          0   “                                                
   	              8      	  9disabled          clkmgr@ffd04000          !altr,clk-mgr             ’Š@       clocks                               osc1            @             !fixed-clock         M}x@            
      osc2            @             !fixed-clock                   f2s_periph_ref_clk          @             !fixed-clock                   f2s_sdram_ref_clk           @             !fixed-clock                   main_pll@40                                   @             !altr,socfpga-pll-clock          
   
            @               mpuclk@48           @             !altr,socfpga-perip-clk          
           ]   ą       	            H                  mainclk@4c          @             !altr,socfpga-perip-clk          
           ]   ä       	            L                  dbg_base_clk@50         @             !altr,socfpga-perip-clk          
      
        ]   č       	            P                  main_qspi_clk@54            @             !altr,socfpga-perip-clk          
               T                  main_nand_sdmmc_clk@58          @             !altr,socfpga-perip-clk          
               X                  cfg_h2f_usr0_clk@5c         @             !altr,socfpga-perip-clk          
               \                     periph_pll@80                                     @             !altr,socfpga-pll-clock          
   
                                 emac0_clk@88            @             !altr,socfpga-perip-clk          
                                 emac1_clk@8c            @             !altr,socfpga-perip-clk          
                                 per_qsi_clk@90          @             !altr,socfpga-perip-clk          
                                  per_nand_mmc_clk@94         @             !altr,socfpga-perip-clk          
                                 per_base_clk@98         @             !altr,socfpga-perip-clk          
                                 h2f_usr1_clk@9c         @             !altr,socfpga-perip-clk          
                                    sdram_pll@c0                                      @             !altr,socfpga-pll-clock          
   
                  Ą               ddr_dqs_clk@c8          @             !altr,socfpga-perip-clk          
               Č            !      ddr_2x_dqs_clk@cc           @             !altr,socfpga-perip-clk          
               Ģ            "      ddr_dq_clk@d0           @             !altr,socfpga-perip-clk          
               Š            #      h2f_usr2_clk@d4         @             !altr,socfpga-perip-clk          
               Ō            $         mpu_periph_clk          @             !altr,socfpga-perip-clk          
           e               3      mpu_l2_ram_clk          @             !altr,socfpga-perip-clk          
           e         l4_main_clk         @             !altr,socfpga-gate-clk           
           s   `                      l3_main_clk         @             !altr,socfpga-perip-clk          
           e         l3_mp_clk           @             !altr,socfpga-gate-clk           
           ]   d               s   `                     l3_sp_clk           @             !altr,socfpga-gate-clk           
           ]   d            l4_mp_clk           @             !altr,socfpga-gate-clk           
              ]   d              s   `               *      l4_sp_clk           @             !altr,socfpga-gate-clk           
              ]   d              s   `               +      dbg_at_clk          @             !altr,socfpga-gate-clk           
           ]   h               s   `                     dbg_clk         @             !altr,socfpga-gate-clk           
           ]   h              s   `         dbg_trace_clk           @             !altr,socfpga-gate-clk           
           ]   l               s   `         dbg_timer_clk           @             !altr,socfpga-gate-clk           
           s   `         cfg_clk         @             !altr,socfpga-gate-clk           
           s   `         h2f_user0_clk           @             !altr,socfpga-gate-clk           
           s   `   	      emac_0_clk          @             !altr,socfpga-gate-clk           
           s                    &      emac_1_clk          @             !altr,socfpga-gate-clk           
           s                   '      usb_mp_clk          @             !altr,socfpga-gate-clk           
           s               ]   ¤                   5      spi_m_clk           @             !altr,socfpga-gate-clk           
           s               ]   ¤                  2      can0_clk            @             !altr,socfpga-gate-clk           
           s               ]   ¤                        can1_clk            @             !altr,socfpga-gate-clk           
           s               ]   ¤   	               	      gpio_db_clk         @             !altr,socfpga-gate-clk           
           s               ]   Ø             h2f_user1_clk           @             !altr,socfpga-gate-clk           
           s             sdmmc_clk           @             !altr,socfpga-gate-clk           
                 s               |                         sdmmc_clk_divided           @             !altr,socfpga-gate-clk           
           s               e               -      nand_x_clk          @             !altr,socfpga-gate-clk           
                 s       	                  nand_ecc_clk            @             !altr,socfpga-gate-clk           
           s       	            /      nand_clk            @             !altr,socfpga-gate-clk           
           s       
        e               .      qspi_clk            @             !altr,socfpga-gate-clk           
                  s                   0      ddr_dqs_clk_gate            @             !altr,socfpga-gate-clk           
   !        s   Ų          ddr_2x_dqs_clk_gate         @             !altr,socfpga-gate-clk           
   "        s   Ų         ddr_dq_clk_gate         @             !altr,socfpga-gate-clk           
   #        s   Ų         h2f_user2_clk           @             !altr,socfpga-gate-clk           
   $        s   Ų               fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           ’@                   a        
         	  9disabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             ’P                   `        
         	  9disabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             ’`                   b        
         	  9disabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           ’ĀP         	  9disabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            ’p`    ’¹              “       Æ                     ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac            %   `             ’p               “       s           macirq          ©                
   &      
  stmmaceth                        
  $stmmaceth           µ           Š           ģ           ś         	  9disabled          ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac            %   `            ’p               “       x           macirq          ©                
   '      
  stmmaceth                 !      
  $stmmaceth           µ           Š           ģ           ś           9okay            rgmii              (           )                ,        B  '  '  '   mdio0                                      !snps,dwmac-mdio    ethernet-phy@1                      W            d            q            ~                                    „            ²            æ            Ģ  D        Ų            å  D            (            gpio@ff708000                                      !snps,dw-apb-gpio             ’p            
   *              9        9okay       gpio-controller@0            !snps,dw-apb-gpio-port            ń                                             ć         Ņ            “       ¤               )         gpio@ff709000                                      !snps,dw-apb-gpio             ’p            
   *              :        9okay       gpio-controller@0            !snps,dw-apb-gpio-port            ń                                             ć         Ņ            “       „               8         gpio@ff70a000                                      !snps,dw-apb-gpio             ’p             
   *              ;        9okay       gpio-controller@0            !snps,dw-apb-gpio-port            ń                                             ć         Ņ            “       ¦               7         i2c@ffc04000                                       !snps,designware-i2c          ’Ą@                  ,        
   +         “                  9okay       pca9557@1f           !nxp,pca9557                      ń                 lm75@48          !lm75                H      at24@50          !atmel,24c01                        P      i2cswitch@70             !nxp,pca9548                                       p   i2c@0                                                i2c@1                                               i2c@2                                               i2c@3                                               i2c@4                                               i2c@5                                               i2c@6                                            eeprom@51            !atmel,24c01                        Q         i2c@7                                            eeprom@51            !atmel,24c01                        Q               i2c@ffc05000                                       !snps,designware-i2c          ’ĄP                  -        
   +         “                  9okay            M     at24@50          !atmel,24c02                        P         i2c@ffc06000                                       !snps,designware-i2c          ’Ą`                  .        
   +         “                 	  9disabled          i2c@ffc07000                                       !snps,designware-i2c          ’Ąp                  /        
   +         “       ”         	  9disabled          eccmgr           !altr,socfpga-ecc-manager                                       ų   l2-ecc@ffd08140          !altr,socfpga-l2-ecc          ’Š@            “       $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           ’ŠD           $   ,         “       ²          ³            cache-controller@fffef000            !arm,pl310-cache          ’žš             “       &            )        7           C                 S                 d           r                               ©            Ā           Ū            ķ                     l3regs@0xff800000            !altr,l3regs syscon           ’           dwmmc0@ff704000          !altr,socfpga-dw-mshc             ’p@             “                  ļ                                     
   *   -        biu ciu               6      	  9disabled                                          '      nand@ff900000                                      !altr,socfpga-denali-nand             ’     ’ø             8nand_data denali_reg             “                  
   .      /        nand nand_x ecc               $      	  9disabled          sram@ffff0000         
   !mmio-sram            ’’                 ,      spi@ff705000          !   !intel,socfpga-qspi cdns,qspi-nor                                       ’pP    ’               “                  B           R           b            
   0              %        9okay       flash@0                                   !micron,n25q128 jedec,spi-nor                         wõį                             §           ·           Ē   2        Õ   2        ć           ń         flash@1                                   !micron,mt25qu02g jedec,spi-nor                      wõį                             §           ·           Ē   2        Õ   2        ć           ń            rstmgr@ffd05000         ’            !altr,rst-mgr             ’ŠP                                 snoop-control-unit@fffec000          !arm,cortex-a9-scu            ’žĄ          sdr@ffc25000             !altr,sdr-ctl syscon          ’ĀP                  =            1      sdramedac            !altr,sdram-edac            1         “       '         spi@fff00000             !snps,dw-apb-ssi                                    ’š              “                  /           
   2              2        $spi       	  9disabled          spi@fff01000             !snps,dw-apb-ssi                                    ’š             “                  /           
   2              3        $spi       	  9disabled          sysmgr@ffd08000          !altr,sys-mgr syscon          ’Š   @         6’ŠÄ            %      timer@fffec600           !arm,cortex-a9-twd-timer          ’žĘ             “                
   3      timer0@ffc08000          !snps,dw-apb-timer            “       §            ’Ą            
   +        timer                 *        $timer         timer1@ffc09000          !snps,dw-apb-timer            “       Ø            ’Ą            
   +        timer                 +        $timer         timer2@ffd00000          !snps,dw-apb-timer            “       ©            ’Š             
   
        timer                 (        $timer         timer3@ffd01000          !snps,dw-apb-timer            “       Ŗ            ’Š            
   
        timer                 )        $timer         serial0@ffc02000             !snps,dw-apb-uart             ’Ą              “       ¢           F           P           
   +        ]   4      4           btx rx                 0      serial1@ffc03000             !snps,dw-apb-uart             ’Ą0             “       £           F           P           
   +        ]   4      4           btx rx                 1      usbphy          l             !usb-nop-xceiv           9okay                6      usb@ffb00000          
   !snps,dwc2            ’°    ’’         “       }           
   5        otg               "        $dwc2            w   6      	  |usb2-phy            9okay            host          usb@ffb40000          
   !snps,dwc2            ’“    ’’         “                  
   5        otg               #        $dwc2            w   6      	  |usb2-phy            9okay            peripheral        watchdog@ffd02000            !snps,dw-wdt          ’Š              “       «           
   
              &        9okay          watchdog@ffd03000            !snps,dw-wdt          ’Š0             “       ¬           
   
              '      	  9disabled             chosen          earlyprintk         serial0:115200n8          memory@0             zmemory               @         gpio-keys         
   !gpio-keys      hps_temp0           £BTN_0              7              ©         hps_hkey0         
  £GP_SWITCH              7              ©        hps_hkey1           £RESET_SWITCH               7              ©        hps_hkey2           £POWER_DOWN             7              ©   t      hps_hkey3           £SENSE              )   	           ©           regulator-usb-nrst           !regulator-fixed       	  “usb_nrst            Ć LK@        Ū LK@        '   8               ó p                           	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 ethernet0 ethernet1 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate clk-phase altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth phy-mode phy-handle snps,reset-gpio snps,reset-active-low snps,reset-delays-us rxd0-skew-ps rxd1-skew-ps rxd2-skew-ps rxd3-skew-ps txd0-skew-ps txd1-skew-ps txd2-skew-ps txd3-skew-ps txen-skew-ps txc-skew-ps rxdv-skew-ps rxc-skew-ps gpio-controller #gpio-cells snps,nr-gpios pagesize iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address spi-max-frequency m25p,fast-read cdns,page-size cdns,block-size cdns,read-delay cdns,tshsl-ns cdns,tsd2d-ns cdns,tchsh-ns cdns,tslch-ns #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names dr_mode bootargs stdout-path label linux,code regulator-name regulator-min-microvolt regulator-max-microvolt startup-delay-us enable-active-high regulator-always-on 