  '   8      (            '                               "    amd,seattle-overdrive amd,seattle                                    +         *   7AMD Seattle Development Board (Overdrive)      interrupt-controller@e1101000             arm,gic-400 arm,cortex-a15-gic            =         R                        +         @   c                                                               g      	           r                              y      v2m@e0080000              arm,gic-v2m-frame                      c                          @                     y            timer             arm,armv8-timer       0   g                              
        pmu           arm,armv8-pmuv3       `   g                           	          
                                                 smb           simple-bus                       +             r                                   clk100mhz_0           fixed-clock                                 adl3clk_100mhz        clk375mhz             fixed-clock                       Z         ccpclk_375mhz         clk333mhz             fixed-clock                       -@         sataclk_333mhz           y         clk500mhz_0           fixed-clock                       e          pcieclk_500mhz        clk500mhz_1           fixed-clock                       e          dmaclk_500mhz         clk250mhz_4           fixed-clock                       沀         miscclk_250mhz           y         clk100mhz_1           fixed-clock                                 uartspiclk_100mhz            y         sata@e0300000             snps,dwc-ahci            c    0                  g      c                               sata@e0d00000         	  disabled              snps,dwc-ahci            c                      g      b                               i2c@e1000000            ok            snps,designware-i2c          c                       g      e                     i2c@e0050000          	  disabled              snps,designware-i2c          c                      g      T                     serial@e1010000           arm,pl011 arm,primecell          c                      g      H                          uartclk apb_pclk          spi@e1020000            ok            arm,pl022 arm,primecell          c                               g      J                     	  apb_pclk          spi@e1030000            ok            arm,pl022 arm,primecell          c                               g      I                     	  apb_pclk            #                        +       sdcard@0              mmc-spi-slot             c            *1-         <    H        K                               g              Q            a            q                                     gpio@e1040000           ok            arm,pl061 arm,primecell                     c                               g      g             =         R                     	  apb_pclk             y         gpio@e1050000           ok            arm,pl061 arm,primecell                     c                                =         R            g      f                     	  apb_pclk          gpio@e0020000         	  disabled              arm,pl061 arm,primecell                     c                                =         R            g      n                     	  apb_pclk          gpio@e0030000         	  disabled              arm,pl061 arm,primecell                     c                                =         R            g      m                     	  apb_pclk          gpio@e0080000         	  disabled              arm,pl061 arm,primecell                     c                                =         R            g      i                     	  apb_pclk          ccp@e0100000            ok            amd,ccp-seattle-v1a          c                      g                          pcie@f0000000             pci-host-ecam-generic                        +            R           pci                                    c                                                                                                              !                                  "                                  #                      C                                T   r                               @       @                                          ok        ccn@e8000000              arm,ccn-504          c                       g      |         kcs@e0010000          	  disabled          	    ipmi-kcs            ipmi             c                      g                                        chosen          /smb/serial@e1010000             	compatible interrupt-parent #address-cells #size-cells model interrupt-controller #interrupt-cells reg interrupts ranges phandle msi-controller arm,msi-base-spi arm,msi-num-spis dma-ranges #clock-cells clock-frequency clock-output-names clocks dma-coherent status clock-names spi-controller num-cs spi-max-frequency voltage-ranges gpios pl022,hierarchy pl022,interface pl022,com-mode pl022,rx-level-trig pl022,tx-level-trig #gpio-cells gpio-controller device_type bus-range msi-parent interrupt-map-mask interrupt-map reg-size reg-spacing stdout-path 