  a   8  \@   (              \                                  ARM Juno development board (r2)       "   arm,juno-r2 arm,juno arm,vexpress                        "            1      refclk7372800hz          fixed-clock          =             J p          Zjuno:uartclk             m   9      clk48mhz             fixed-clock          =             Jl       	   Zclk48mhz             m   =      clk50mhz             fixed-clock          =             J         Zsmc_clk          m   	      refclk100mhz             fixed-clock          =             J       	   Zapb_pclk             m   
      refclk400mhz             fixed-clock          =             Jׄ       	   Zfaxi_clk             m   3      clk24mhz             fixed-clock          =             Jn6          Zjuno_mb:clk24mhz             m         clk25mhz             fixed-clock          =             J}x@         Zjuno_mb:clk25mhz             m         refclk1mhz           fixed-clock          =             J B@         Zjuno_mb:refclk1mhz           m         refclk32khz          fixed-clock          =             J            Zjuno_mb:refclk32khz          m         mcc-sb-3v3           regulator-fixed          uMCC_SB_3V3            2Z          2Z                   m         gpio-keys         
   gpio-keys      power-button                2                      t         POWER                            home-button             2                      f         HOME                            rlock-button                2                               RLOCK                           vol-up-button               2                      s         VOL+                            vol-down-button             2                      r         VOL-                            nmi-button              2                      c         NMI                            bus@8000000          simple-bus           "            1         x                                                                                                                                               *                          D                            E                            F                                                                                                                                                                                      	                            
                                                                            motherboard-bus          arm,vexpress,v2p-p1 simple-bus           "            1                              	    V2M-Juno            8  R        @            Rrs1    flash@0          arm,vexpress-flash cfi-flash            e                   i         	  tdisabled       partitions           arm,arm-firmware-suite           ethernet@200000000           smsc,lan9118 smsc,lan9115           e                  {           mii                                                                     iofpga-bus@300000000             simple-bus           "            1                              sysctl@20000             arm,sp810 arm,primecell         e                               refclk timclk apb_pclk           =         0   Ztimerclken0 timerclken1 timerclken2 timerclken3                                                                m         apbregs@10000            syscon simple-mfd           e         led0             register-bit-led                       %            vexpress:0        
  #heartbeat           9on        led1             register-bit-led                       %            vexpress:1          #mmc0            9off       led2             register-bit-led                       %            vexpress:2          #cpu0            9off       led3             register-bit-led                       %            vexpress:3          #cpu1            9off       led4             register-bit-led                       %            vexpress:4          #cpu2            9off       led5             register-bit-led                       %             vexpress:5          #cpu3            9off       led6             register-bit-led                       %   @         vexpress:6          9off       led7             register-bit-led                       %            vexpress:7          9off          mmci@50000           arm,pl180 arm,primecell         e              {           G          U                 	        mclk apb_pclk         kmi@60000            arm,pl050 arm,primecell         e              {                 	        KMIREFCLK apb_pclk        kmi@70000            arm,pl050 arm,primecell         e              {                 	        KMIREFCLK apb_pclk        wdt@f0000            arm,sp805 arm,primecell         e              {                 	        wdog_clk apb_pclk         timer@110000             arm,sp804 arm,primecell         e              {   	                                timclken1 timclken2 apb_pclk          timer@120000             arm,sp804 arm,primecell         e              {   	                               timclken1 timclken2 apb_pclk          rtc@170000           arm,pl031 arm,primecell         e              {               	      	  apb_pclk          gpio@1d0000          arm,pl061 arm,primecell         e              {              	      	  apb_pclk             a        q            }                    m                  timer@2a810000           arm,armv7-timer-mem         e    *                  J         "            1                    *             tokay       frame@2a830000                     {       <           e               mhu@2b1f0000             arm,mhu arm,primecell           e    +                 {       $          #           mhu_lpri_rx mhu_hpri_rx                       
      	  apb_pclk             m   /      iommu@2b400000           arm,mmu-400 arm,smmu-v1         e    +@                 {       &          &                                                      	  tdisabled          iommu@2b500000           arm,mmu-401 arm,smmu-v1         e    +P                 {       (          (                                        	  tdisabled             m   .      iommu@2b600000           arm,mmu-401 arm,smmu-v1         e    +`                 {       *          *                                                          m         interrupt-controller@2c010000            arm,gic-400 arm,cortex-a15-gic        @  e    ,             ,             ,             ,                  "                       1            }        {      	  ?                 ,              m      v2m@0            arm,gic-v2m-frame                    e                m   -      v2m@10000            arm,gic-v2m-frame                    e            v2m@20000            arm,gic-v2m-frame                    e            v2m@30000            arm,gic-v2m-frame                    e               timer            arm,armv8-timer       0  {        ?        ?        ?      
  ?      etf@20010000              arm,coresight-tmc arm,primecell         e                         	      	  apb_pclk                      in-ports       port       endpoint                        m               out-ports      port       endpoint                        m   C               tpiu@20030000         !   arm,coresight-tpiu arm,primecell            e                         	      	  apb_pclk                      in-ports       port       endpoint                        m                  funnel@20040000       +   arm,coresight-dynamic-funnel arm,primecell          e                         	      	  apb_pclk                      out-ports      port       endpoint                        m               in-ports             "            1       port@0          e       endpoint                        m            port@1          e      endpoint                        m   !               etr@20070000              arm,coresight-tmc arm,primecell         e                                        	      	  apb_pclk                               in-ports       port       endpoint                        m                  stm@20100000              arm,coresight-stm arm,primecell          e                  (                  /stm-base stm-stimulus-base             	      	  apb_pclk                      out-ports      port       endpoint                        m   ?               replicator@20120000       /   arm,coresight-dynamic-replicator arm,primecell          e                         	      	  apb_pclk                      out-ports            "            1       port@0          e       endpoint                        m            port@1          e      endpoint                        m               in-ports       port       endpoint                        m   B               cpu-debug@22010000        &   arm,coresight-cpu-debug arm,primecell           e    "                    	      	  apb_pclk                           9         etm@22040000          "   arm,coresight-etm4x arm,primecell           e    "                    	      	  apb_pclk                           9      out-ports      port       endpoint                        m                  funnel@220c0000       +   arm,coresight-dynamic-funnel arm,primecell          e    "                    	      	  apb_pclk                      out-ports      port       endpoint                        m               in-ports             "            1       port@0          e       endpoint                        m            port@1          e      endpoint                        m                  cpu-debug@22110000        &   arm,coresight-cpu-debug arm,primecell           e    "                    	      	  apb_pclk                           9         etm@22140000          "   arm,coresight-etm4x arm,primecell           e    "                    	      	  apb_pclk                           9      out-ports      port       endpoint                        m                  cpu-debug@23010000        &   arm,coresight-cpu-debug arm,primecell           e    #                    	      	  apb_pclk                           9         etm@23040000          "   arm,coresight-etm4x arm,primecell           e    #                    	      	  apb_pclk                           9      out-ports      port       endpoint                         m   "               funnel@230c0000       +   arm,coresight-dynamic-funnel arm,primecell          e    #                    	      	  apb_pclk                      out-ports      port       endpoint               !         m               in-ports             "            1       port@0          e       endpoint               "         m             port@1          e      endpoint               #         m   '         port@2          e      endpoint               $         m   )         port@3          e      endpoint               %         m   +               cpu-debug@23110000        &   arm,coresight-cpu-debug arm,primecell           e    #                    	      	  apb_pclk                           9   &      etm@23140000          "   arm,coresight-etm4x arm,primecell           e    #                    	      	  apb_pclk                           9   &   out-ports      port       endpoint               '         m   #               cpu-debug@23210000        &   arm,coresight-cpu-debug arm,primecell           e    #!                    	      	  apb_pclk                           9   (      etm@23240000          "   arm,coresight-etm4x arm,primecell           e    #$                    	      	  apb_pclk                           9   (   out-ports      port       endpoint               )         m   $               cpu-debug@23310000        &   arm,coresight-cpu-debug arm,primecell           e    #1                    	      	  apb_pclk                           9   *      etm@23340000          "   arm,coresight-etm4x arm,primecell           e    #4                    	      	  apb_pclk                           9   *   out-ports      port       endpoint               +         m   %               gpu@2d000000             arm,juno-mali arm,mali-t624         e    -                $  {       !          "                      job mmu gpu            ,                                	  tdisabled          sram@2e000000            arm,juno-sram-ns mmio-sram          e    .                   "            1                    .         scp-sram@0           arm,juno-scp-shmem          e             scp-sram@200             arm,juno-scp-shmem          e               m   0         pcie@40000000         <   arm,juno-r1-pcie plda,xpressrich3-axi pci-host-ecam-generic         =pci         e    @                  I               S             "            1                  T                  _                P       P          B      @       @                                                     *                                                                                                                                        d   -        tokay            o            ~       .             scpi          	   arm,scpi               /              0   clocks           arm,scpi-clocks    clocks-0             arm,scpi-dvfs-clocks             =                              Zatlclk aplclk gpuclk             m   ,      clocks-1             arm,scpi-variable-clocks             =                       Zpxlclk           m   5         power-controller             arm,scpi-power-domains                                 m         sensors          arm,scpi-sensors                        m   1         thermal-zones      pmic                         d           1       trips      trip0            _                	  Dcritical                soc                      d           1      trips      trip0            8                	  Dcritical                big-cluster                      d           1           tokay          little-cluster                       d           1           tokay          gpu0                         d           1           tokay          gpu1                         d           1           tokay             iommu@7fb00000           arm,mmu-401 arm,smmu-v1         e                     {       _          _                                        	  tdisabled             m   2      iommu@7fb10000           arm,mmu-401 arm,smmu-v1         e                     {       c          c                                  m   4      iommu@7fb20000           arm,mmu-401 arm,smmu-v1         e                     {       a          a                                  m   7      iommu@7fb30000           arm,mmu-401 arm,smmu-v1         e                     {       e          e                                           m   <      dma@7ff00000             arm,pl330 arm,primecell         e                     $           /           =          l  {       X          Y          Z          [          \          l          m          n          o         H     2       2      2      2      2      2      2      2      2              3      	  apb_pclk          hdlcd@7ff50000        
   arm,hdlcd           e                     {       ]              4               5           pxlclk     port       endpoint               6         m   ;            hdlcd@7ff60000        
   arm,hdlcd           e                     {       U              7               5           pxlclk     port       endpoint               8         m   :            serial@7ff80000          arm,pl011 arm,primecell         e                     {       S              9   
        uartclk apb_pclk          i2c@7ffa0000             snps,designware-i2c         e                      "            1            {       h            J         K             	   hdmi-transmitter@70          nxp,tda998x         e   p   port       endpoint               :         m   8            hdmi-transmitter@71          nxp,tda998x         e   q   port       endpoint               ;         m   6               usb@7ffb0000             generic-ohci            e                     {       t              <               =      usb@7ffc0000             generic-ehci            e                     {       u              <               =      memory-controller@7ffd0000           arm,pl354 arm,primecell         e                     {       V          W              	      	  apb_pclk          memory@80000000         =memory           e                                tlx-bus@60000000             simple-bus           "            1                    `                                         *                               funnel@20130000       +   arm,coresight-dynamic-funnel arm,primecell          e                         	      	  apb_pclk                      out-ports      port       endpoint               >         m   @            in-ports       port       endpoint               ?         m                  etf@20140000              arm,coresight-tmc arm,primecell         e                         	      	  apb_pclk                      in-ports       port       endpoint               @         m   >            out-ports      port       endpoint               A         m   D               funnel@20150000       +   arm,coresight-dynamic-funnel arm,primecell          e                         	      	  apb_pclk                      out-ports      port       endpoint               B         m               in-ports             "            1       port@0          e       endpoint             `           C         m            port@1          e      endpoint             `           D         m   A               aliases         k/serial@7ff80000          chosen          sserial0:115200n8          psci             arm,psci-0.2            smc       cpus             "            1       cpu-map    cluster0       core0           9         core1           9            cluster1       core0           9         core1           9   &      core2           9   (      core3           9   *            idle-states         psci       cpu-sleep-0          arm,idle-state                                ,                             m   F      cluster-sleep-0          arm,idle-state                                                   	         m   G         cpu@0            arm,cortex-a72          e                =cpu         psci                          @                   '           4   @        F           S   E           ,            d   F   G        t                      m         cpu@1            arm,cortex-a72          e               =cpu         psci                          @                   '           4   @        F           S   E           ,            d   F   G        t                      m         cpu@100          arm,cortex-a53          e               =cpu         psci                          @                   '           4   @        F           S   H           ,           d   F   G        t                      m         cpu@101          arm,cortex-a53          e              =cpu         psci                          @                   '           4   @        F           S   H           ,           d   F   G        t                      m   &      cpu@102          arm,cortex-a53          e              =cpu         psci                          @                   '           4   @        F           S   H           ,           d   F   G        t                      m   (      cpu@103          arm,cortex-a53          e              =cpu         psci                          @                   '           4   @        F           S   H           ,           d   F   G        t                      m   *      l2-cache0            cache                       
   @                    m   E      l2-cache1            cache                      
   @                    m   H         pmu-a72          arm,cortex-a72-pmu          {                                        pmu-a53          arm,cortex-a53-pmu        0  {                                                      &   (   *         	model compatible interrupt-parent #address-cells #size-cells #clock-cells clock-frequency clock-output-names phandle regulator-name regulator-min-microvolt regulator-max-microvolt regulator-always-on debounce-interval wakeup-source linux,code label gpios ranges #interrupt-cells interrupt-map-mask interrupt-map arm,hbi arm,vexpress,site arm,v2m-memory-map reg bank-width status interrupts phy-mode reg-io-width smsc,irq-active-high smsc,irq-push-pull clocks vdd33a-supply vddvario-supply clock-names assigned-clocks assigned-clock-parents offset linux,default-trigger default-state max-frequency vmmc-supply gpio-controller #gpio-cells interrupt-controller frame-number interrupt-names #mbox-cells #iommu-cells #global-interrupts power-domains dma-coherent msi-controller remote-endpoint iommus arm,scatter-gather reg-names cpu device_type bus-range linux,pci-domain msi-parent iommu-map-mask iommu-map mboxes shmem clock-indices num-domains #power-domain-cells #thermal-sensor-cells polling-delay polling-delay-passive thermal-sensors temperature hysteresis #dma-cells #dma-channels #dma-requests i2c-sda-hold-time-ns slave-mode serial0 stdout-path method entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache cpu-idle-states capacity-dmips-mhz dynamic-power-coefficient interrupt-affinity 