Ðþí  
‰   8  	$   (            e  ì                                 Cavium ThunderX2 CN99XX       (   cavium,thunderx2-cn9900 brcm,vulcan-soc                      "            1      cpus             "            1       cpu@0            =cpu          cavium,thunder2 brcm,vulcan          I                 Mpsci          cpu@1            =cpu          cavium,thunder2 brcm,vulcan          I                Mpsci          cpu@2            =cpu          cavium,thunder2 brcm,vulcan          I                Mpsci          cpu@3            =cpu          cavium,thunder2 brcm,vulcan          I                Mpsci             psci             arm,psci-0.2             Tsmc       interrupt-controller@400080000           arm,gic-v3           [            "            1             l          s         ˆ             I                                   Ÿ      	            ª      gic-its@40010000             arm,gic-v3-its            ²         I                      ª            timer            arm,armv8-timer       0   Ÿ                                 
         pmu           brcm,vulcan-pmu arm,armv8-pmuv3          Ÿ               uart_clk125mhz           fixed-clock          Á             ÎsY@      
   Þclk125mhz            ª         pcie@30000000            pci-host-ecam-generic            =pci          [            "            1            I    0                	   ñPCI ECAM          8   l       @       @           C      @       @                     û       ÿ                                                                                                                                                                                         &            1      soc          simple-bus           "            1             l   serial@402020000             arm,pl011 arm,primecell          I                                 Ÿ       1           >         	  Eapb_pclk             memory           =memory            I    €       €      €       €         aliases         Q/soc/serial@402020000         chosen          Yserial0:115200n8             	model compatible interrupt-parent #address-cells #size-cells device_type reg enable-method #interrupt-cells ranges interrupt-controller #redistributor-regions interrupts phandle msi-controller #clock-cells clock-frequency clock-output-names reg-names bus-range interrupt-map-mask interrupt-map msi-parent dma-coherent clocks clock-names serial0 stdout-path 