     8  `   (            y  (                             (    ti,am3517-craneboard ti,am3517 ti,omap3                                  +         #   7TI AM3517 CraneBoard (TMDSEVM3517)     chosen        aliases          =/ocp@68000000/i2c@48070000           B/ocp@68000000/i2c@48072000           G/ocp@68000000/i2c@48060000           L/ocp@68000000/mmc@4809c000           Q/ocp@68000000/mmc@480b4000           V/ocp@68000000/mmc@480ad000           [/ocp@68000000/serial@4806a000            c/ocp@68000000/serial@4806c000            k/ocp@68000000/serial@49020000            s/ocp@68000000/serial@4809e000            {/ocp@68000000/can@5c050000        cpus                         +       cpu@0             arm,cortex-a8            cpu                                   cpu                                pmu@54000000              arm,cortex-a8-pmu            T                           debugss       soc           ti,omap-infra      mpu           ti,omap3-mpu             mpu       iva       
    ti,iva2.2            iva       	   disabled       dsp           ti,omap3-c64                ocp@68000000              ti,omap3-l3-smx simple-bus           h                  	   
                     +                      l3_main    l4@48000000           ti,omap3-l4-core simple-bus                      +                H         scm@2000              ti,omap3-scm simple-bus                                       +                           pinmux@30              ti,omap3-padconf pinctrl-single             0  8                     +                                                        :     pinmux_tps_pins         W            k            scm_conf@270              syscon simple-bus              p  0                     +                  p  0        k      pbias_regulator@2b0           ti,pbias-omap3 ti,pbias-omap                          s      pbias_mmc_omap2430          zpbias_mmc_omap2430           w@         -        k            clocks                       +       mcbsp5_mux_fck@68                         ti,composite-mux-clock                                        h        k         mcbsp5_fck                        ti,composite-clock                         k         mcbsp1_mux_fck@4                          ti,composite-mux-clock                                                k   
      mcbsp1_fck                        ti,composite-clock              	   
        k         mcbsp2_mux_fck@4                          ti,composite-mux-clock                                                k         mcbsp2_fck                        ti,composite-clock                         k         mcbsp3_mux_fck@68                         ti,composite-mux-clock                             h        k         mcbsp3_fck                        ti,composite-clock                         k         mcbsp4_mux_fck@68                         ti,composite-mux-clock                                        h        k         mcbsp4_fck                        ti,composite-clock                         k         emac_ick@32c                          ti,am35xx-gate-clock                           ,                   k   x      emac_fck@32c                          ti,gate-clock                          ,           	        k         vpfe_ick@32c                          ti,am35xx-gate-clock                           ,                   k   y      vpfe_fck@32c                          ti,gate-clock                          ,           
      hsotgusb_ick_am35xx@32c                       ti,am35xx-gate-clock                           ,                    k   z      hsotgusb_fck_am35xx@32c                       ti,gate-clock                          ,                   k   {      hecc_ck@32c                       ti,am35xx-gate-clock                           ,                   k   |            clockdomains          pinmux@a00             ti,omap3-padconf pinctrl-single            
    \                     +                                                        :              prm@48306000              ti,omap3-prm             H0`   @                clocks                       +       virt_16_8m_ck                         fixed-clock          Y         k         osc_sys_ck@d40                        ti,mux-clock                                          @        k         sys_ck@1270                       ti,divider-clock                                                 p                 k         sys_clkout1@d70                       ti,gate-clock                          p                 dpll3_x2_ck                       fixed-factor-clock                                          dpll3_m2x2_ck                         fixed-factor-clock                                            k          dpll4_x2_ck                       fixed-factor-clock                                          corex2_fck                        fixed-factor-clock                                             k   !      wkup_l4_ick                       fixed-factor-clock                                            k   P      corex2_d3_fck                         fixed-factor-clock              !                              k   q      corex2_d5_fck                         fixed-factor-clock              !                              k   r         clockdomains             cm@48004000           ti,omap3-cm          H @   @    clocks                       +       dummy_apb_pclk                        fixed-clock                   omap_32k_fck                          fixed-clock                    k   B      virt_12m_ck                       fixed-clock                   k         virt_13m_ck                       fixed-clock          ]@        k         virt_19200000_ck                          fixed-clock         $         k         virt_26000000_ck                          fixed-clock                 k         virt_38_4m_ck                         fixed-clock         I         k         dpll4_ck@d00                          ti,omap3-dpll-per-clock                                 D  0        k         dpll4_m2_ck@d48                       ti,divider-clock                           ?           H                 k   "      dpll4_m2x2_mul_ck                         fixed-factor-clock              "                              k   #      dpll4_m2x2_ck@d00                         ti,gate-clock               #                                        k   $      omap_96m_alwon_fck                        fixed-factor-clock              $                              k   +      dpll3_ck@d00                          ti,omap3-dpll-core-clock                                    @  0        k         dpll3_m3_ck@1140                          ti,divider-clock                                                 @                 k   %      dpll3_m3x2_mul_ck                         fixed-factor-clock              %                              k   &      dpll3_m3x2_ck@d00                         ti,gate-clock               &                                        k   '      emu_core_alwon_ck                         fixed-factor-clock              '                              k   d      sys_altclk                        fixed-clock                     k   0      mcbsp_clks                        fixed-clock                     k         dpll3_m2_ck@d40                       ti,divider-clock                                                 @                 k         core_ck                       fixed-factor-clock                                            k   (      dpll1_fck@940                         ti,divider-clock                (                                 	@                 k   )      dpll1_ck@904                          ti,omap3-dpll-clock                )           	  	$  	@  	4        k         dpll1_x2_ck                       fixed-factor-clock                                            k   *      dpll1_x2m2_ck@944                         ti,divider-clock                *                      	D                 k   >      cm_96m_fck                        fixed-factor-clock              +                              k   ,      omap_96m_fck@d40                          ti,mux-clock                ,                         @        k   G      dpll4_m3_ck@e40                       ti,divider-clock                                                  @                 k   -      dpll4_m3x2_mul_ck                         fixed-factor-clock              -                              k   .      dpll4_m3x2_ck@d00                         ti,gate-clock               .                                        k   /      omap_54m_fck@d40                          ti,mux-clock                /   0                      @        k   :      cm_96m_d2_fck                         fixed-factor-clock              ,                              k   1      omap_48m_fck@d40                          ti,mux-clock                1   0                      @        k   2      omap_12m_fck                          fixed-factor-clock              2                              k   I      dpll4_m4_ck@e40                       ti,divider-clock                                      @                 k   3      dpll4_m4x2_mul_ck                         ti,fixed-factor-clock               3        0           >            K        k   4      dpll4_m4x2_ck@d00                         ti,gate-clock               4                                         K        k   v      dpll4_m5_ck@f40                       ti,divider-clock                           ?           @                 k   5      dpll4_m5x2_mul_ck                         ti,fixed-factor-clock               5        0           >            K        k   6      dpll4_m5x2_ck@d00                         ti,gate-clock               6                                         K      dpll4_m6_ck@1140                          ti,divider-clock                                      ?           @                 k   7      dpll4_m6x2_mul_ck                         fixed-factor-clock              7                              k   8      dpll4_m6x2_ck@d00                         ti,gate-clock               8                                        k   9      emu_per_alwon_ck                          fixed-factor-clock              9                              k   e      clkout2_src_gate_ck@d70                        ti,composite-no-wait-gate-clock             (                      p        k   ;      clkout2_src_mux_ck@d70                        ti,composite-mux-clock              (      ,   :           p        k   <      clkout2_src_ck                        ti,composite-clock              ;   <        k   =      sys_clkout2@d70                       ti,divider-clock                =                      @           p         ^      mpu_ck                        fixed-factor-clock              >                              k   ?      arm_fck@924                       ti,divider-clock                ?           	$                 emu_mpu_alwon_ck                          fixed-factor-clock              ?                              k   f      l3_ick@a40                        ti,divider-clock                (                      
@                 k   @      l4_ick@a40                        ti,divider-clock                @                                 
@                 k   A      rm_ick@c40                        ti,divider-clock                A                                 @               gpt10_gate_fck@a00                        ti,composite-gate-clock                                   
         k   C      gpt10_mux_fck@a40                         ti,composite-mux-clock              B                         
@        k   D      gpt10_fck                         ti,composite-clock              C   D      gpt11_gate_fck@a00                        ti,composite-gate-clock                                   
         k   E      gpt11_mux_fck@a40                         ti,composite-mux-clock              B                         
@        k   F      gpt11_fck                         ti,composite-clock              E   F      core_96m_fck                          fixed-factor-clock              G                              k         mmchs2_fck@a00                        ti,wait-gate-clock                         
                    k         mmchs1_fck@a00                        ti,wait-gate-clock                         
                    k         i2c3_fck@a00                          ti,wait-gate-clock                         
                    k         i2c2_fck@a00                          ti,wait-gate-clock                         
                    k         i2c1_fck@a00                          ti,wait-gate-clock                         
                    k         mcbsp5_gate_fck@a00                       ti,composite-gate-clock                        
           
         k         mcbsp1_gate_fck@a00                       ti,composite-gate-clock                        	           
         k   	      core_48m_fck                          fixed-factor-clock              2                              k   H      mcspi4_fck@a00                        ti,wait-gate-clock              H           
                    k         mcspi3_fck@a00                        ti,wait-gate-clock              H           
                    k         mcspi2_fck@a00                        ti,wait-gate-clock              H           
                    k         mcspi1_fck@a00                        ti,wait-gate-clock              H           
                    k         uart2_fck@a00                         ti,wait-gate-clock              H           
                    k         uart1_fck@a00                         ti,wait-gate-clock              H           
                    k         core_12m_fck                          fixed-factor-clock              I                              k   J      hdq_fck@a00                       ti,wait-gate-clock              J           
                    k         core_l3_ick                       fixed-factor-clock              @                              k   K      sdrc_ick@a10                          ti,wait-gate-clock              K           
                   k   w      gpmc_fck                          fixed-factor-clock              K                            core_l4_ick                       fixed-factor-clock              A                              k   L      mmchs2_ick@a10                        ti,omap3-interface-clock                L           
                   k         mmchs1_ick@a10                        ti,omap3-interface-clock                L           
                   k         hdq_ick@a10                       ti,omap3-interface-clock                L           
                   k         mcspi4_ick@a10                        ti,omap3-interface-clock                L           
                   k         mcspi3_ick@a10                        ti,omap3-interface-clock                L           
                   k         mcspi2_ick@a10                        ti,omap3-interface-clock                L           
                   k         mcspi1_ick@a10                        ti,omap3-interface-clock                L           
                   k         i2c3_ick@a10                          ti,omap3-interface-clock                L           
                   k         i2c2_ick@a10                          ti,omap3-interface-clock                L           
                   k         i2c1_ick@a10                          ti,omap3-interface-clock                L           
                   k         uart2_ick@a10                         ti,omap3-interface-clock                L           
                   k         uart1_ick@a10                         ti,omap3-interface-clock                L           
                   k         gpt11_ick@a10                         ti,omap3-interface-clock                L           
                   k         gpt10_ick@a10                         ti,omap3-interface-clock                L           
                   k         mcbsp5_ick@a10                        ti,omap3-interface-clock                L           
           
        k         mcbsp1_ick@a10                        ti,omap3-interface-clock                L           
           	        k         omapctrl_ick@a10                          ti,omap3-interface-clock                L           
                   k         dss_tv_fck@e00                        ti,gate-clock               :                               k         dss_96m_fck@e00                       ti,gate-clock               G                               k         dss2_alwon_fck@e00                        ti,gate-clock                                              k         dummy_ck                          fixed-clock                   gpt1_gate_fck@c00                         ti,composite-gate-clock                                             k   M      gpt1_mux_fck@c40                          ti,composite-mux-clock              B              @        k   N      gpt1_fck                          ti,composite-clock              M   N        k         aes2_ick@a10                          ti,omap3-interface-clock                L                      
        k         wkup_32k_fck                          fixed-factor-clock              B                              k   O      gpio1_dbck@c00                        ti,gate-clock               O                               k         sha12_ick@a10                         ti,omap3-interface-clock                L           
                   k         wdt2_fck@c00                          ti,wait-gate-clock              O                               k         wdt2_ick@c10                          ti,omap3-interface-clock                P                              k         wdt1_ick@c10                          ti,omap3-interface-clock                P                              k         gpio1_ick@c10                         ti,omap3-interface-clock                P                              k         omap_32ksync_ick@c10                          ti,omap3-interface-clock                P                              k         gpt12_ick@c10                         ti,omap3-interface-clock                P                              k         gpt1_ick@c10                          ti,omap3-interface-clock                P                               k         per_96m_fck                       fixed-factor-clock              +                              k         per_48m_fck                       fixed-factor-clock              2                              k   Q      uart3_fck@1000                        ti,wait-gate-clock              Q                               k   }      gpt2_gate_fck@1000                        ti,composite-gate-clock                                            k   R      gpt2_mux_fck@1040                         ti,composite-mux-clock              B              @        k   S      gpt2_fck                          ti,composite-clock              R   S        k         gpt3_gate_fck@1000                        ti,composite-gate-clock                                            k   T      gpt3_mux_fck@1040                         ti,composite-mux-clock              B                         @        k   U      gpt3_fck                          ti,composite-clock              T   U      gpt4_gate_fck@1000                        ti,composite-gate-clock                                            k   V      gpt4_mux_fck@1040                         ti,composite-mux-clock              B                         @        k   W      gpt4_fck                          ti,composite-clock              V   W      gpt5_gate_fck@1000                        ti,composite-gate-clock                                            k   X      gpt5_mux_fck@1040                         ti,composite-mux-clock              B                         @        k   Y      gpt5_fck                          ti,composite-clock              X   Y      gpt6_gate_fck@1000                        ti,composite-gate-clock                                            k   Z      gpt6_mux_fck@1040                         ti,composite-mux-clock              B                         @        k   [      gpt6_fck                          ti,composite-clock              Z   [      gpt7_gate_fck@1000                        ti,composite-gate-clock                                            k   \      gpt7_mux_fck@1040                         ti,composite-mux-clock              B                         @        k   ]      gpt7_fck                          ti,composite-clock              \   ]      gpt8_gate_fck@1000                        ti,composite-gate-clock                        	                    k   ^      gpt8_mux_fck@1040                         ti,composite-mux-clock              B                         @        k   _      gpt8_fck                          ti,composite-clock              ^   _      gpt9_gate_fck@1000                        ti,composite-gate-clock                        
                    k   `      gpt9_mux_fck@1040                         ti,composite-mux-clock              B                         @        k   a      gpt9_fck                          ti,composite-clock              `   a      per_32k_alwon_fck                         fixed-factor-clock              B                              k   b      gpio6_dbck@1000                       ti,gate-clock               b                               k   ~      gpio5_dbck@1000                       ti,gate-clock               b                               k         gpio4_dbck@1000                       ti,gate-clock               b                               k         gpio3_dbck@1000                       ti,gate-clock               b                               k         gpio2_dbck@1000                       ti,gate-clock               b                               k         wdt3_fck@1000                         ti,wait-gate-clock              b                               k         per_l4_ick                        fixed-factor-clock              A                              k   c      gpio6_ick@1010                        ti,omap3-interface-clock                c                              k         gpio5_ick@1010                        ti,omap3-interface-clock                c                              k         gpio4_ick@1010                        ti,omap3-interface-clock                c                              k         gpio3_ick@1010                        ti,omap3-interface-clock                c                              k         gpio2_ick@1010                        ti,omap3-interface-clock                c                              k         wdt3_ick@1010                         ti,omap3-interface-clock                c                              k         uart3_ick@1010                        ti,omap3-interface-clock                c                              k         uart4_ick@1010                        ti,omap3-interface-clock                c                              k         gpt9_ick@1010                         ti,omap3-interface-clock                c                      
        k         gpt8_ick@1010                         ti,omap3-interface-clock                c                      	        k         gpt7_ick@1010                         ti,omap3-interface-clock                c                              k         gpt6_ick@1010                         ti,omap3-interface-clock                c                              k         gpt5_ick@1010                         ti,omap3-interface-clock                c                              k         gpt4_ick@1010                         ti,omap3-interface-clock                c                              k         gpt3_ick@1010                         ti,omap3-interface-clock                c                              k         gpt2_ick@1010                         ti,omap3-interface-clock                c                              k         mcbsp2_ick@1010                       ti,omap3-interface-clock                c                               k         mcbsp3_ick@1010                       ti,omap3-interface-clock                c                              k         mcbsp4_ick@1010                       ti,omap3-interface-clock                c                              k         mcbsp2_gate_fck@1000                          ti,composite-gate-clock                                             k         mcbsp3_gate_fck@1000                          ti,composite-gate-clock                                            k         mcbsp4_gate_fck@1000                          ti,composite-gate-clock                                            k         emu_src_mux_ck@1140                       ti,mux-clock                   d   e   f           @        k   g      emu_src_ck                        ti,clkdm-gate-clock             g        k   h      pclk_fck@1140                         ti,divider-clock                h                                 @               pclkx2_fck@1140                       ti,divider-clock                h                                 @               atclk_fck@1140                        ti,divider-clock                h                                 @               traceclk_src_fck@1140                         ti,mux-clock                   d   e   f                      @        k   i      traceclk_fck@1140                         ti,divider-clock                i                                 @               secure_32k_fck                        fixed-clock                    k   j      gpt12_fck                         fixed-factor-clock              j                              k         wdt1_fck                          fixed-factor-clock              j                            ipss_ick@a10                          ti,am35xx-interface-clock               K           
                   k         rmii_ck                       fixed-clock                 k         pclk_ck                       fixed-clock                 k         uart4_ick_am35xx@a10                          ti,omap3-interface-clock                L           
                 uart4_fck_am35xx@a00                          ti,wait-gate-clock              H           
                  dpll5_ck@d04                          ti,omap3-dpll-clock                             $  L  4         t                 k   k      dpll5_m2_ck@d50                       ti,divider-clock                k                      P                 k   u      sgx_gate_fck@b00                          ti,composite-gate-clock             (                               k   s      core_d3_ck                        fixed-factor-clock              (                              k   l      core_d4_ck                        fixed-factor-clock              (                              k   m      core_d6_ck                        fixed-factor-clock              (                              k   n      omap_192m_alwon_fck                       fixed-factor-clock              $                              k   o      core_d2_ck                        fixed-factor-clock              (                              k   p      sgx_mux_fck@b40                       ti,composite-mux-clock               l   m   n   ,   o   p   q   r           @        k   t      sgx_fck                       ti,composite-clock              s   t        k         sgx_ick@b10                       ti,wait-gate-clock              @                               k         cpefuse_fck@a08                       ti,gate-clock                          
                    k         ts_fck@a08                        ti,gate-clock               B           
                   k         usbtll_fck@a08                        ti,wait-gate-clock              u           
                   k         usbtll_ick@a18                        ti,omap3-interface-clock                L           
                   k         mmchs3_ick@a10                        ti,omap3-interface-clock                L           
                   k         mmchs3_fck@a00                        ti,wait-gate-clock                         
                    k         dss1_alwon_fck_3430es2@e00                        ti,dss-gate-clock               v                                 K        k         dss_ick_3430es2@e10                       ti,omap3-dss-interface-clock                A                               k         usbhost_120m_fck@1400                         ti,gate-clock               u                               k         usbhost_48m_fck@1400                          ti,dss-gate-clock               2                                k         usbhost_ick@1410                          ti,omap3-dss-interface-clock                A                               k            clockdomains       core_l3_clkdm             ti,clockdomain              w      x   y   z   {   |      dpll3_clkdm           ti,clockdomain                    dpll1_clkdm           ti,clockdomain                    per_clkdm             ti,clockdomain        h      }   ~                                                                              emu_clkdm             ti,clockdomain              h      dpll4_clkdm           ti,clockdomain                    wkup_clkdm            ti,clockdomain                                          dss_clkdm             ti,clockdomain                                core_l4_clkdm             ti,clockdomain                                                                                                                                dpll5_clkdm           ti,clockdomain              k      sgx_clkdm             ti,clockdomain                    usbhost_clkdm             ti,clockdomain                                target-module@48320000            ti,sysc-omap2 ti,sysc            H2     H2          	  rev sysc                               O            fck ick                      +                H2        counter@0             ti,omap-counter32k                            interrupt-controller@48200000             ti,omap3-intc                                 H              k         target-module@48056000            ti,sysc-omap2 ti,sysc            H`    H`,   H`(           rev sysc syss             #                                                           K         ick                      +                H`       dma-controller@0              ti,omap3430-sdma ti,omap-sdma                                                                          `        k            gpio@48310000             ti,omap3-gpio            H1                          gpio1                                                           gpio@49050000             ti,omap3-gpio            I                          gpio2                                                  gpio@49052000             ti,omap3-gpio            I                          gpio3                                                  gpio@49054000             ti,omap3-gpio            I@                          gpio4                                                  gpio@49056000             ti,omap3-gpio            I`                !         gpio5                                                  gpio@49058000             ti,omap3-gpio            I                "         gpio6                                                  serial@4806a000           ti,omap3-uart            H             !      H        5      1      2        :tx rx            uart1           l       serial@4806c000           ti,omap3-uart            H            !      I        5      3      4        :tx rx            uart2           l       serial@49020000           ti,omap3-uart            I             !      J        5      5      6        :tx rx            uart3           l       i2c@48070000              ti,omap3-i2c             H                 8        5                    :tx rx                        +             i2c1             '@   tps@2d              -          ti,tps65910         Ddefault         R                                    \        m           y                                                                        regulators                       +       regulator@0                      vrtc                   regulator@1                     vio                regulator@2                     vdd1          	  zvdd_core             O         O                        regulator@3                     vdd2            zvdd_shv          2Z         2Z                 k         regulator@4                     vdd3          regulator@5                     vdig1         regulator@6                     vdig2         regulator@7                     vpll             w@         w@               regulator@8                     vdac             w@         w@               regulator@9             	        vaux1            w@         w@               regulator@10                
        vaux2            w@         w@               regulator@11                        vaux33        regulator@12                        vmmc             2Z         2Z               regulator@13                        vbb                i2c@48072000              ti,omap3-i2c             H                 9        5                    :tx rx                        +             i2c2                   	   disabled          i2c@48060000              ti,omap3-i2c             H                 =        5                    :tx rx                        +             i2c3                   	   disabled          mailbox@48094000              ti,omap3-mailbox             mailbox          H	@                        	                      '         	   disabled       dsp         9                    D                    spi@48098000              ti,omap2-mcspi           H	                A                     +             mcspi1          O         @  5      #      $      %      &      '      (      )      *         :tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3       spi@4809a000              ti,omap2-mcspi           H	                B                     +             mcspi2          O            5      +      ,      -      .        :tx0 rx0 tx1 rx1       spi@480b8000              ti,omap2-mcspi           H                [                     +             mcspi3          O            5                                :tx0 rx0 tx1 rx1       spi@480ba000              ti,omap2-mcspi           H                0                     +             mcspi4          O           5      F      G        :tx0 rx0       1w@480b2000           ti,omap3-1w          H                 :         hdq1w         mmc@4809c000              ti,omap3-hsmmc           H	                S         mmc1             ]        5      =      >        :tx rx           j           w                    mmc@480b4000              ti,omap3-hsmmc           H@                V         mmc2            5      /      0        :tx rx         	   disabled          mmc@480ad000              ti,omap3-hsmmc           H
                ^         mmc3            5      M      N        :tx rx         	   disabled          mmu@480bd400                          ti,omap2-iommu           H                         mmu_isp                  	   disabled          mmu@5d000000                          ti,omap2-iommu           ]                           mmu_iva       	   disabled          wdt@48314000              ti,omap3-wdt             H1@          
   wd_timer2         mcbsp@48074000            ti,omap3-mcbsp           H@            mpu                ;   <        common tx rx                        mcbsp1          5                     :tx rx                        fck       	   disabled          target-module@480a0000            ti,sysc-omap2 ti,sysc            H
 <   H
 @   H
 D           rev sysc syss                                                 ick                      +                H
            	   disabled       rng@0             ti,omap2-rng                                 4         mcbsp@49022000            ti,omap3-mcbsp           I     I            mpu sidetone                   >   ?           common tx rx sidetone                       mcbsp2 mcbsp2_sidetone          5      !      "        :tx rx                           fck ick       	   disabled          mcbsp@49024000            ti,omap3-mcbsp           I@    I            mpu sidetone                   Y   Z           common tx rx sidetone                       mcbsp3 mcbsp3_sidetone          5                    :tx rx                           fck ick       	   disabled          mcbsp@49026000            ti,omap3-mcbsp           I`            mpu                6   7        common tx rx                        mcbsp4          5                    :tx rx                        fck                   	   disabled          mcbsp@48096000            ti,omap3-mcbsp           H	`            mpu                Q   R        common tx rx                        mcbsp5          5                    :tx rx                        fck       	   disabled          sham@480c3000             ti,omap3-sham            sham             H0    d            1        5      E        :rx        target-module@48318000            ti,sysc-omap2-timer ti,sysc          H1    H1   H1           rev sysc syss             '                                                     fck ick                      +                H1                         timer@0           ti,omap3430-timer                                        fck             %                                        target-module@49032000            ti,sysc-omap2-timer ti,sysc          I     I    I            rev sysc syss             '                                                     fck ick                      +                I                          timer@0           ti,omap3430-timer                               &                               timer@49034000            ti,omap3430-timer            I@                '         timer3        timer@49036000            ti,omap3430-timer            I`                (         timer4        timer@49038000            ti,omap3430-timer            I                )         timer5           /      timer@4903a000            ti,omap3430-timer            I                *         timer6           /      timer@4903c000            ti,omap3430-timer            I                +         timer7           /      timer@4903e000            ti,omap3430-timer            I                ,         timer8           <         /      timer@49040000            ti,omap3430-timer            I                 -         timer9           <      timer@48086000            ti,omap3430-timer            H`                .         timer10          <      timer@48088000            ti,omap3430-timer            H                /         timer11          <      target-module@48304000            ti,sysc-omap2-timer ti,sysc          H0@    H0@   H0@           rev sysc syss             '                                                     fck ick                      +                H0@       timer@0           ti,omap3430-timer                               _                  I         usbhstll@48062000             ti,usbhs-tll             H                 N         usb_tll_hs        usbhshost@48064000            ti,usbhs-host            H@             usb_host_hs                      +                ohci@48064400             ti,ohci-omap3            HD                L         Y      ehci@48064800             ti,ehci-omap             HH                M         gpmc@6e000000             ti,omap3430-gpmc             gpmc             n                         5              :rxtx            q           }                        +                                                  usb_otg_hs@480ab000           ti,omap3-musb            H
                \   ]        mc dma           usb_otg_hs                                         	   disabled          dss@48050000              ti,omap3-dss             H           	   disabled          	   dss_core                         fck                      +                dispc@48050400            ti,omap3-dispc           H                      
   dss_dispc                        fck       encoder@4804fc00              ti,omap3-dsi             H    H    @H             proto phy pll                     	   disabled          	   dss_dsi1                            fck sys_clk                      +          encoder@48050800              ti,omap3-rfbi            H          	   disabled          	   dss_rfbi                            fck ick       encoder@48050c00              ti,omap3-venc            H          	   disabled          	   dss_venc                         fck          ssi-controller@48058000           ti,omap3-ssi             ssi       	   disabled             H    H            sys gdd             G        gdd_mpu                      +                ssi-port@4805a000             ti,omap3-ssi-port            H    H            tx rx               C   D      ssi-port@4805b000             ti,omap3-ssi-port            H    H            tx rx               E   F         am35x_otg_hs@5c040000             ti,omap3-musb            am35x_otg_hs          	   disabled             \                 G        mc        ethernet@5c000000             ti,am3517-emac           davinci_emac             okay             \                  C   D   E   F        s                                                                     ,                    x         ick       mdio@5c030000             ti,davinci_mdio          davinci_mdio             okay             \             > B@                     +                         fck       serial@4809e000           ti,omap3-uart            uart4         	   disabled             H	                T        5      7      6        :tx rx           l       pinmux@480025d8            ti,omap3-padconf pinctrl-single          H %   $                     +                                                        :        can@5c050000              ti,am3517-hecc        	   disabled             \     \0   \             hecc hecc-ram mbx                           |      target-module@50000000            ti,sysc-omap2 ti,sysc            P             rev                         fck ick                      +                P     @          opp-table             operating-points-v2-ti-cpu          s           k      opp50-300000000         G             N O        \         m      opp100-600000000            G    #F         N O        \         memory@80000000          memory                       fixedregulator            regulator-fixed         zvbat             LK@         LK@                 k            	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 can device_type reg clocks clock-names clock-latency operating-points-v2 interrupts ti,hwmods status ranges #pinctrl-cells #interrupt-cells interrupt-controller pinctrl-single,register-width pinctrl-single,function-mask pinctrl-single,pins phandle syscon regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift clock-frequency ti,max-div ti,index-starts-at-one clock-mult clock-div ti,set-bit-to-disable ti,clock-mult ti,clock-div ti,set-rate-parent ti,index-power-of-two ti,low-power-stop ti,lock reg-names ti,sysc-sidle ti,sysc-mask ti,sysc-midle ti,syss-mask #dma-cells dma-channels dma-requests ti,gpio-always-on gpio-controller #gpio-cells interrupts-extended dmas dma-names pinctrl-names pinctrl-0 ti,en-ck32k-xtal vcc1-supply vcc2-supply vcc3-supply vcc4-supply vcc5-supply vcc6-supply vcc7-supply vccio-supply regulator-compatible regulator-always-on regulator-boot-on #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,spi-num-cs ti,dual-volt pbias-supply vmmc-supply bus-width #iommu-cells ti,#tlb-entries interrupt-names ti,buffer-size #sound-dai-cells ti,no-reset-on-init ti,no-idle ti,timer-alwon assigned-clocks assigned-clock-parents ti,timer-dsp ti,timer-pwm ti,timer-secure remote-wakeup-connected gpmc,num-cs gpmc,num-waitpins multipoint num-eps ram-bits ti,davinci-ctrl-reg-offset ti,davinci-ctrl-mod-reg-offset ti,davinci-ctrl-ram-offset ti,davinci-ctrl-ram-size ti,davinci-rmii-en local-mac-address bus_freq opp-hz opp-microvolt opp-supported-hw opp-suspend 