     8  (   (                                           %    teejet,mt_ventoux ti,am3517 ti,omap3                                     +            7TeeJet Mt.Ventoux      chosen        aliases          =/ocp@68000000/i2c@48070000           B/ocp@68000000/i2c@48072000           G/ocp@68000000/i2c@48060000           L/ocp@68000000/mmc@4809c000           Q/ocp@68000000/mmc@480b4000           V/ocp@68000000/mmc@480ad000           [/ocp@68000000/serial@4806a000            c/ocp@68000000/serial@4806c000            k/ocp@68000000/serial@49020000         cpus                         +       cpu@0             arm,cortex-a8            scpu                                   cpu                                                        pmu@54000000              arm,cortex-a8-pmu            T                           debugss       soc           ti,omap-infra      mpu           ti,omap3-mpu             mpu       iva       
    ti,iva2.2            iva       	   disabled       dsp           ti,omap3-c64                ocp@68000000              ti,omap3-l3-smx simple-bus           h                  	   
                     +                      l3_main    l4@48000000           ti,omap3-l4-core simple-bus                      +                H         scm@2000              ti,omap3-scm simple-bus                                       +                           pinmux@30              ti,omap3-padconf pinctrl-single             0  8                     +                                            '           E        scm_conf@270              syscon simple-bus              p  0                     +                  p  0               pbias_regulator@2b0           ti,pbias-omap3 ti,pbias-omap                          b      pbias_mmc_omap2430          ipbias_mmc_omap2430          x w@         -                     clocks                       +       mcbsp5_mux_fck@68                         ti,composite-mux-clock                                        h                  mcbsp5_fck                        ti,composite-clock                                   mcbsp1_mux_fck@4                          ti,composite-mux-clock                                                    
      mcbsp1_fck                        ti,composite-clock              	   
                  mcbsp2_mux_fck@4                          ti,composite-mux-clock                                                          mcbsp2_fck                        ti,composite-clock                                   mcbsp3_mux_fck@68                         ti,composite-mux-clock                             h                  mcbsp3_fck                        ti,composite-clock                                   mcbsp4_mux_fck@68                         ti,composite-mux-clock                                        h                  mcbsp4_fck                        ti,composite-clock                                         clockdomains          pinmux@a00             ti,omap3-padconf pinctrl-single            
    \                     +                                            '           E              target-module@480a6000            ti,sysc-omap2 ti,sysc            H
`D   H
`H   H
`L           rev sysc syss                                                                ick                      +                H
`        aes1@0            ti,omap3-aes                    P                           	      
        tx rx            target-module@480c5000            ti,sysc-omap2 ti,sysc            HPD   HPH   HPL           rev sysc syss                                                                ick                      +                HP        aes2@0            ti,omap3-aes                    P                           A      B        tx rx            prm@48306000              ti,omap3-prm             H0`   @                clocks                       +       virt_16_8m_ck                         fixed-clock          Y                   osc_sys_ck@d40                        ti,mux-clock                                          @                  sys_ck@1270                       ti,divider-clock                                                 p                            sys_clkout1@d70                       ti,gate-clock                          p                 dpll3_x2_ck                       fixed-factor-clock                      5           @         dpll3_m2x2_ck                         fixed-factor-clock                      5           @                     dpll4_x2_ck                       fixed-factor-clock                      5           @         corex2_fck                        fixed-factor-clock                      5           @               !      wkup_l4_ick                       fixed-factor-clock                       5           @               P      corex2_d3_fck                         fixed-factor-clock              !        5           @                     corex2_d5_fck                         fixed-factor-clock              !        5           @                        clockdomains             cm@48004000           ti,omap3-cm          H @   @    clocks                       +       dummy_apb_pclk                        fixed-clock                   omap_32k_fck                          fixed-clock                        B      virt_12m_ck                       fixed-clock                             virt_13m_ck                       fixed-clock          ]@                  virt_19200000_ck                          fixed-clock         $                   virt_26000000_ck                          fixed-clock                           virt_38_4m_ck                         fixed-clock         I                   dpll4_ck@d00                          ti,omap3-dpll-per-clock                                   D  0                  dpll4_m2_ck@d48                       ti,divider-clock                           ?           H                     "      dpll4_m2x2_mul_ck                         fixed-factor-clock              "        5           @               #      dpll4_m2x2_ck@d00                         ti,gate-clock               #                                J            $      omap_96m_alwon_fck                        fixed-factor-clock              $        5           @               +      dpll3_ck@d00                          ti,omap3-dpll-core-clock                                      @  0                  dpll3_m3_ck@1140                          ti,divider-clock                                                 @                     %      dpll3_m3x2_mul_ck                         fixed-factor-clock              %        5           @               &      dpll3_m3x2_ck@d00                         ti,gate-clock               &                                J            '      emu_core_alwon_ck                         fixed-factor-clock              '        5           @               d      sys_altclk                        fixed-clock                         0      mcbsp_clks                        fixed-clock                               dpll3_m2_ck@d40                       ti,divider-clock                                                 @                           core_ck                       fixed-factor-clock                      5           @               (      dpll1_fck@940                         ti,divider-clock                (                                 	@                     )      dpll1_ck@904                          ti,omap3-dpll-clock                 )           	  	$  	@  	4                  dpll1_x2_ck                       fixed-factor-clock                      5           @               *      dpll1_x2m2_ck@944                         ti,divider-clock                *                      	D                     >      cm_96m_fck                        fixed-factor-clock              +        5           @               ,      omap_96m_fck@d40                          ti,mux-clock                ,                          @            G      dpll4_m3_ck@e40                       ti,divider-clock                                                  @                     -      dpll4_m3x2_mul_ck                         fixed-factor-clock              -        5           @               .      dpll4_m3x2_ck@d00                         ti,gate-clock               .                                J            /      omap_54m_fck@d40                          ti,mux-clock                /   0                      @            :      cm_96m_d2_fck                         fixed-factor-clock              ,        5           @               1      omap_48m_fck@d40                          ti,mux-clock                1   0                      @            2      omap_12m_fck                          fixed-factor-clock              2        5           @               I      dpll4_m4_ck@e40                       ti,divider-clock                                      @                     3      dpll4_m4x2_mul_ck                         ti,fixed-factor-clock               3        `           n            {            4      dpll4_m4x2_ck@d00                         ti,gate-clock               4                                J         {                  dpll4_m5_ck@f40                       ti,divider-clock                           ?           @                     5      dpll4_m5x2_mul_ck                         ti,fixed-factor-clock               5        `           n            {            6      dpll4_m5x2_ck@d00                         ti,gate-clock               6                                J         {            l      dpll4_m6_ck@1140                          ti,divider-clock                                      ?           @                     7      dpll4_m6x2_mul_ck                         fixed-factor-clock              7        5           @               8      dpll4_m6x2_ck@d00                         ti,gate-clock               8                                J            9      emu_per_alwon_ck                          fixed-factor-clock              9        5           @               e      clkout2_src_gate_ck@d70                        ti,composite-no-wait-gate-clock             (                      p            ;      clkout2_src_mux_ck@d70                        ti,composite-mux-clock              (       ,   :           p            <      clkout2_src_ck                        ti,composite-clock              ;   <            =      sys_clkout2@d70                       ti,divider-clock                =                      @           p               mpu_ck                        fixed-factor-clock              >        5           @               ?      arm_fck@924                       ti,divider-clock                ?           	$                 emu_mpu_alwon_ck                          fixed-factor-clock              ?        5           @               f      l3_ick@a40                        ti,divider-clock                (                      
@                     @      l4_ick@a40                        ti,divider-clock                @                                 
@                     A      rm_ick@c40                        ti,divider-clock                A                                 @               gpt10_gate_fck@a00                        ti,composite-gate-clock                                    
             C      gpt10_mux_fck@a40                         ti,composite-mux-clock              B                          
@            D      gpt10_fck                         ti,composite-clock              C   D      gpt11_gate_fck@a00                        ti,composite-gate-clock                                    
             E      gpt11_mux_fck@a40                         ti,composite-mux-clock              B                          
@            F      gpt11_fck                         ti,composite-clock              E   F      core_96m_fck                          fixed-factor-clock              G        5           @                     mmchs2_fck@a00                        ti,wait-gate-clock                         
                              mmchs1_fck@a00                        ti,wait-gate-clock                         
                              i2c3_fck@a00                          ti,wait-gate-clock                         
                              i2c2_fck@a00                          ti,wait-gate-clock                         
                              i2c1_fck@a00                          ti,wait-gate-clock                         
                              mcbsp5_gate_fck@a00                       ti,composite-gate-clock                        
           
                   mcbsp1_gate_fck@a00                       ti,composite-gate-clock                        	           
             	      core_48m_fck                          fixed-factor-clock              2        5           @               H      mcspi4_fck@a00                        ti,wait-gate-clock              H           
                              mcspi3_fck@a00                        ti,wait-gate-clock              H           
                              mcspi2_fck@a00                        ti,wait-gate-clock              H           
                              mcspi1_fck@a00                        ti,wait-gate-clock              H           
                              uart2_fck@a00                         ti,wait-gate-clock              H           
                              uart1_fck@a00                         ti,wait-gate-clock              H           
                              core_12m_fck                          fixed-factor-clock              I        5           @               J      hdq_fck@a00                       ti,wait-gate-clock              J           
                              core_l3_ick                       fixed-factor-clock              @        5           @               K      sdrc_ick@a10                          ti,wait-gate-clock              K           
                             gpmc_fck                          fixed-factor-clock              K        5           @         core_l4_ick                       fixed-factor-clock              A        5           @               L      mmchs2_ick@a10                        ti,omap3-interface-clock                L           
                             mmchs1_ick@a10                        ti,omap3-interface-clock                L           
                             hdq_ick@a10                       ti,omap3-interface-clock                L           
                             mcspi4_ick@a10                        ti,omap3-interface-clock                L           
                             mcspi3_ick@a10                        ti,omap3-interface-clock                L           
                             mcspi2_ick@a10                        ti,omap3-interface-clock                L           
                             mcspi1_ick@a10                        ti,omap3-interface-clock                L           
                             i2c3_ick@a10                          ti,omap3-interface-clock                L           
                             i2c2_ick@a10                          ti,omap3-interface-clock                L           
                             i2c1_ick@a10                          ti,omap3-interface-clock                L           
                             uart2_ick@a10                         ti,omap3-interface-clock                L           
                             uart1_ick@a10                         ti,omap3-interface-clock                L           
                             gpt11_ick@a10                         ti,omap3-interface-clock                L           
                             gpt10_ick@a10                         ti,omap3-interface-clock                L           
                             mcbsp5_ick@a10                        ti,omap3-interface-clock                L           
           
                  mcbsp1_ick@a10                        ti,omap3-interface-clock                L           
           	                  omapctrl_ick@a10                          ti,omap3-interface-clock                L           
                             dss_tv_fck@e00                        ti,gate-clock               :                                         dss_96m_fck@e00                       ti,gate-clock               G                                         dss2_alwon_fck@e00                        ti,gate-clock                                                         dummy_ck                          fixed-clock                   gpt1_gate_fck@c00                         ti,composite-gate-clock                                                  M      gpt1_mux_fck@c40                          ti,composite-mux-clock              B               @            N      gpt1_fck                          ti,composite-clock              M   N                  aes2_ick@a10                          ti,omap3-interface-clock                L                      
                  wkup_32k_fck                          fixed-factor-clock              B        5           @               O      gpio1_dbck@c00                        ti,gate-clock               O                                         sha12_ick@a10                         ti,omap3-interface-clock                L           
                             wdt2_fck@c00                          ti,wait-gate-clock              O                                         wdt2_ick@c10                          ti,omap3-interface-clock                P                                        wdt1_ick@c10                          ti,omap3-interface-clock                P                                        gpio1_ick@c10                         ti,omap3-interface-clock                P                                        omap_32ksync_ick@c10                          ti,omap3-interface-clock                P                                        gpt12_ick@c10                         ti,omap3-interface-clock                P                                        gpt1_ick@c10                          ti,omap3-interface-clock                P                                         per_96m_fck                       fixed-factor-clock              +        5           @                     per_48m_fck                       fixed-factor-clock              2        5           @               Q      uart3_fck@1000                        ti,wait-gate-clock              Q                                         gpt2_gate_fck@1000                        ti,composite-gate-clock                                                 R      gpt2_mux_fck@1040                         ti,composite-mux-clock              B               @            S      gpt2_fck                          ti,composite-clock              R   S                  gpt3_gate_fck@1000                        ti,composite-gate-clock                                                 T      gpt3_mux_fck@1040                         ti,composite-mux-clock              B                          @            U      gpt3_fck                          ti,composite-clock              T   U      gpt4_gate_fck@1000                        ti,composite-gate-clock                                                 V      gpt4_mux_fck@1040                         ti,composite-mux-clock              B                          @            W      gpt4_fck                          ti,composite-clock              V   W      gpt5_gate_fck@1000                        ti,composite-gate-clock                                                 X      gpt5_mux_fck@1040                         ti,composite-mux-clock              B                          @            Y      gpt5_fck                          ti,composite-clock              X   Y      gpt6_gate_fck@1000                        ti,composite-gate-clock                                                 Z      gpt6_mux_fck@1040                         ti,composite-mux-clock              B                          @            [      gpt6_fck                          ti,composite-clock              Z   [      gpt7_gate_fck@1000                        ti,composite-gate-clock                                                 \      gpt7_mux_fck@1040                         ti,composite-mux-clock              B                          @            ]      gpt7_fck                          ti,composite-clock              \   ]      gpt8_gate_fck@1000                        ti,composite-gate-clock                         	                        ^      gpt8_mux_fck@1040                         ti,composite-mux-clock              B                          @            _      gpt8_fck                          ti,composite-clock              ^   _      gpt9_gate_fck@1000                        ti,composite-gate-clock                         
                        `      gpt9_mux_fck@1040                         ti,composite-mux-clock              B                          @            a      gpt9_fck                          ti,composite-clock              `   a      per_32k_alwon_fck                         fixed-factor-clock              B        5           @               b      gpio6_dbck@1000                       ti,gate-clock               b                                         gpio5_dbck@1000                       ti,gate-clock               b                                         gpio4_dbck@1000                       ti,gate-clock               b                                         gpio3_dbck@1000                       ti,gate-clock               b                                         gpio2_dbck@1000                       ti,gate-clock               b                                         wdt3_fck@1000                         ti,wait-gate-clock              b                                         per_l4_ick                        fixed-factor-clock              A        5           @               c      gpio6_ick@1010                        ti,omap3-interface-clock                c                                        gpio5_ick@1010                        ti,omap3-interface-clock                c                                        gpio4_ick@1010                        ti,omap3-interface-clock                c                                        gpio3_ick@1010                        ti,omap3-interface-clock                c                                        gpio2_ick@1010                        ti,omap3-interface-clock                c                                        wdt3_ick@1010                         ti,omap3-interface-clock                c                                        uart3_ick@1010                        ti,omap3-interface-clock                c                                        uart4_ick@1010                        ti,omap3-interface-clock                c                                        gpt9_ick@1010                         ti,omap3-interface-clock                c                      
                  gpt8_ick@1010                         ti,omap3-interface-clock                c                      	                  gpt7_ick@1010                         ti,omap3-interface-clock                c                                        gpt6_ick@1010                         ti,omap3-interface-clock                c                                        gpt5_ick@1010                         ti,omap3-interface-clock                c                                        gpt4_ick@1010                         ti,omap3-interface-clock                c                                        gpt3_ick@1010                         ti,omap3-interface-clock                c                                        gpt2_ick@1010                         ti,omap3-interface-clock                c                                        mcbsp2_ick@1010                       ti,omap3-interface-clock                c                                         mcbsp3_ick@1010                       ti,omap3-interface-clock                c                                        mcbsp4_ick@1010                       ti,omap3-interface-clock                c                                        mcbsp2_gate_fck@1000                          ti,composite-gate-clock                                                       mcbsp3_gate_fck@1000                          ti,composite-gate-clock                                                      mcbsp4_gate_fck@1000                          ti,composite-gate-clock                                                      emu_src_mux_ck@1140                       ti,mux-clock                    d   e   f           @            g      emu_src_ck                        ti,clkdm-gate-clock             g            h      pclk_fck@1140                         ti,divider-clock                h                                 @               pclkx2_fck@1140                       ti,divider-clock                h                                 @               atclk_fck@1140                        ti,divider-clock                h                                 @               traceclk_src_fck@1140                         ti,mux-clock                    d   e   f                      @            i      traceclk_fck@1140                         ti,divider-clock                i                                 @               secure_32k_fck                        fixed-clock                        j      gpt12_fck                         fixed-factor-clock              j        5           @                     wdt1_fck                          fixed-factor-clock              j        5           @         security_l4_ick2                          fixed-factor-clock              A        5           @               k      aes1_ick@a14                          ti,omap3-interface-clock                k                      
                  rng_ick@a14                       ti,omap3-interface-clock                k           
                             sha11_ick@a14                         ti,omap3-interface-clock                k           
                 des1_ick@a14                          ti,omap3-interface-clock                k           
                  cam_mclk@f00                          ti,gate-clock               l                                 {      cam_ick@f10                   !    ti,omap3-no-wait-interface-clock                A                                         csi2_96m_fck@f00                          ti,gate-clock                                                        security_l3_ick                       fixed-factor-clock              @        5           @               m      pka_ick@a14                       ti,omap3-interface-clock                m           
                 icr_ick@a10                       ti,omap3-interface-clock                L           
                 des2_ick@a10                          ti,omap3-interface-clock                L           
                 mspro_ick@a10                         ti,omap3-interface-clock                L           
                 mailboxes_ick@a10                         ti,omap3-interface-clock                L           
                 ssi_l4_ick                        fixed-factor-clock              A        5           @               t      sr1_fck@c00                       ti,wait-gate-clock                                                        sr2_fck@c00                       ti,wait-gate-clock                                                        sr_l4_ick                         fixed-factor-clock              A        5           @         dpll2_fck@40                          ti,divider-clock                (                                  @                     n      dpll2_ck@4                        ti,omap3-dpll-clock                 n               $   @   4                                       o      dpll2_m2_ck@44                        ti,divider-clock                o                       D                     p      iva2_ck@0                         ti,wait-gate-clock              p                                           modem_fck@a00                         ti,omap3-interface-clock                            
                              sad2d_ick@a10                         ti,omap3-interface-clock                @           
                             mad2d_ick@a18                         ti,omap3-interface-clock                @           
                             mspro_fck@a00                         ti,wait-gate-clock                         
                  ssi_ssr_gate_fck_3430es2@a00                           ti,composite-no-wait-gate-clock             !                       
             q      ssi_ssr_div_fck_3430es2@a40                       ti,composite-divider-clock              !                      
@      $                                            r      ssi_ssr_fck_3430es2                       ti,composite-clock              q   r            s      ssi_sst_fck_3430es2                       fixed-factor-clock              s        5           @                     hsotgusb_ick_3430es2@a10                      "    ti,omap3-hsotgusb-interface-clock               K           
                             ssi_ick_3430es2@a10                       ti,omap3-ssi-interface-clock                t           
                              usim_gate_fck@c00                         ti,composite-gate-clock             G           	                              sys_d2_ck                         fixed-factor-clock                       5           @               v      omap_96m_d2_fck                       fixed-factor-clock              G        5           @               w      omap_96m_d4_fck                       fixed-factor-clock              G        5           @               x      omap_96m_d8_fck                       fixed-factor-clock              G        5           @               y      omap_96m_d10_fck                          fixed-factor-clock              G        5           @   
            z      dpll5_m2_d4_ck                        fixed-factor-clock              u        5           @               {      dpll5_m2_d8_ck                        fixed-factor-clock              u        5           @               |      dpll5_m2_d16_ck                       fixed-factor-clock              u        5           @               }      dpll5_m2_d20_ck                       fixed-factor-clock              u        5           @               ~      usim_mux_fck@c40                          ti,composite-mux-clock        (          v   w   x   y   z   {   |   }   ~                      @                           usim_fck                          ti,composite-clock                       usim_ick@c10                          ti,omap3-interface-clock                P                      	                  dpll5_ck@d04                          ti,omap3-dpll-clock                               $  L  4                                    dpll5_m2_ck@d50                       ti,divider-clock                                      P                     u      sgx_gate_fck@b00                          ti,composite-gate-clock             (                                         core_d3_ck                        fixed-factor-clock              (        5           @                     core_d4_ck                        fixed-factor-clock              (        5           @                     core_d6_ck                        fixed-factor-clock              (        5           @                     omap_192m_alwon_fck                       fixed-factor-clock              $        5           @                     core_d2_ck                        fixed-factor-clock              (        5           @                     sgx_mux_fck@b40                       ti,composite-mux-clock                        ,                       @                  sgx_fck                       ti,composite-clock                                   sgx_ick@b10                       ti,wait-gate-clock              @                                         cpefuse_fck@a08                       ti,gate-clock                           
                              ts_fck@a08                        ti,gate-clock               B           
                             usbtll_fck@a08                        ti,wait-gate-clock              u           
                             usbtll_ick@a18                        ti,omap3-interface-clock                L           
                             mmchs3_ick@a10                        ti,omap3-interface-clock                L           
                             mmchs3_fck@a00                        ti,wait-gate-clock                         
                              dss1_alwon_fck_3430es2@e00                        ti,dss-gate-clock                                                {                  dss_ick_3430es2@e10                       ti,omap3-dss-interface-clock                A                                         usbhost_120m_fck@1400                         ti,gate-clock               u                                         usbhost_48m_fck@1400                          ti,dss-gate-clock               2                                          usbhost_ick@1410                          ti,omap3-dss-interface-clock                A                                            clockdomains       core_l3_clkdm             ti,clockdomain                       dpll3_clkdm           ti,clockdomain                    dpll1_clkdm           ti,clockdomain                    per_clkdm             ti,clockdomain        h                                                                                       emu_clkdm             ti,clockdomain              h      dpll4_clkdm           ti,clockdomain                    wkup_clkdm            ti,clockdomain        $                                    dss_clkdm             ti,clockdomain                                core_l4_clkdm             ti,clockdomain                                                                                                                                cam_clkdm             ti,clockdomain                       iva2_clkdm            ti,clockdomain                    dpll2_clkdm           ti,clockdomain              o      d2d_clkdm             ti,clockdomain                          dpll5_clkdm           ti,clockdomain                    sgx_clkdm             ti,clockdomain                    usbhost_clkdm             ti,clockdomain                                target-module@48320000            ti,sysc-omap2 ti,sysc            H2     H2          	  rev sysc                               O            fck ick                      +                H2        counter@0             ti,omap-counter32k                            interrupt-controller@48200000             ti,omap3-intc                                H                        target-module@48056000            ti,sysc-omap2 ti,sysc            H`    H`,   H`(           rev sysc syss             #                                                           K         ick                      +                H`       dma-controller@0              ti,omap3430-sdma ti,omap-sdma                                                                          `                     gpio@48310000             ti,omap3-gpio            H1                          gpio1                     #        3                             gpio@49050000             ti,omap3-gpio            I                          gpio2            #        3                             gpio@49052000             ti,omap3-gpio            I                          gpio3            #        3                             gpio@49054000             ti,omap3-gpio            I@                          gpio4            #        3                             gpio@49056000             ti,omap3-gpio            I`                !         gpio5            #        3                             gpio@49058000             ti,omap3-gpio            I                "         gpio6            #        3                             serial@4806a000           ti,omap3-uart            H             ?      H              1      2        tx rx            uart1           l       serial@4806c000           ti,omap3-uart            H            ?      I              3      4        tx rx            uart2           l       serial@49020000           ti,omap3-uart            I             ?      J              5      6        tx rx            uart3           l       i2c@48070000              ti,omap3-i2c             H                 8                            tx rx                        +             i2c1          i2c@48072000              ti,omap3-i2c             H                 9                            tx rx                        +             i2c2          i2c@48060000              ti,omap3-i2c             H                 =                            tx rx                        +             i2c3          mailbox@48094000              ti,omap3-mailbox             mailbox          H	@                        S           _           q      dsp                                                 spi@48098000              ti,omap2-mcspi           H	                A                     +             mcspi1                   @        #      $      %      &      '      (      )      *         tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3       spi@4809a000              ti,omap2-mcspi           H	                B                     +             mcspi2                            +      ,      -      .        tx0 rx0 tx1 rx1       spi@480b8000              ti,omap2-mcspi           H                [                     +             mcspi3                                                      tx0 rx0 tx1 rx1       spi@480ba000              ti,omap2-mcspi           H                0                     +             mcspi4                           F      G        tx0 rx0       1w@480b2000           ti,omap3-1w          H                 :         hdq1w         mmc@4809c000              ti,omap3-hsmmc           H	                S         mmc1                           =      >        tx rx                    mmc@480b4000              ti,omap3-hsmmc           H@                V         mmc2                  /      0        tx rx         mmc@480ad000              ti,omap3-hsmmc           H
                ^         mmc3                  M      N        tx rx         mmu@480bd400                          ti,omap2-iommu           H                         mmu_isp                              mmu@5d000000                          ti,omap2-iommu           ]                           mmu_iva       	   disabled          wdt@48314000              ti,omap3-wdt             H1@          
   wd_timer2         mcbsp@48074000            ti,omap3-mcbsp           H@            mpu                ;   <        common tx rx                        mcbsp1                               tx rx                        fck       	   disabled          target-module@480a0000            ti,sysc-omap2 ti,sysc            H
 <   H
 @   H
 D           rev sysc syss                                                             ick                      +                H
         rng@0             ti,omap2-rng                                 4         mcbsp@49022000            ti,omap3-mcbsp           I     I            mpu sidetone                   >   ?           common tx rx sidetone                       mcbsp2 mcbsp2_sidetone                !      "        tx rx                           fck ick       	   disabled          mcbsp@49024000            ti,omap3-mcbsp           I@    I            mpu sidetone                   Y   Z           common tx rx sidetone                       mcbsp3 mcbsp3_sidetone                              tx rx                           fck ick       	   disabled          mcbsp@49026000            ti,omap3-mcbsp           I`            mpu                6   7        common tx rx                        mcbsp4                              tx rx                        fck                   	   disabled          mcbsp@48096000            ti,omap3-mcbsp           H	`            mpu                Q   R        common tx rx                        mcbsp5                              tx rx                        fck       	   disabled          sham@480c3000             ti,omap3-sham            sham             H0    d            1              E        rx        target-module@48318000            ti,sysc-omap2-timer ti,sysc          H1    H1   H1           rev sysc syss             '                                                     fck ick                      +                H1                      "   timer@0           ti,omap3430-timer                                        fck             %         -        <           L   B         target-module@49032000            ti,sysc-omap2-timer ti,sysc          I     I    I            rev sysc syss             '                                                     fck ick                      +                I        timer@0           ti,omap3430-timer                               &         timer@49034000            ti,omap3430-timer            I@                '         timer3        timer@49036000            ti,omap3430-timer            I`                (         timer4        timer@49038000            ti,omap3430-timer            I                )         timer5           c      timer@4903a000            ti,omap3430-timer            I                *         timer6           c      timer@4903c000            ti,omap3430-timer            I                +         timer7           c      timer@4903e000            ti,omap3430-timer            I                ,         timer8           p         c      timer@49040000            ti,omap3430-timer            I                 -         timer9           p      timer@48086000            ti,omap3430-timer            H`                .         timer10          p      timer@48088000            ti,omap3430-timer            H                /         timer11          p      target-module@48304000            ti,sysc-omap2-timer ti,sysc          H0@    H0@   H0@           rev sysc syss             '                                                     fck ick                      +                H0@       timer@0           ti,omap3430-timer                               _         -         }         usbhstll@48062000             ti,usbhs-tll             H                 N         usb_tll_hs        usbhshost@48064000            ti,usbhs-host            H@             usb_host_hs                      +                ohci@48064400             ti,ohci-omap3            HD                L               ehci@48064800             ti,ehci-omap             HH                M         gpmc@6e000000             ti,omap3430-gpmc             gpmc             n                                       rxtx                                               +                                #        3         usb_otg_hs@480ab000           ti,omap3-musb            H
                \   ]        mc dma           usb_otg_hs                                         dss@48050000              ti,omap3-dss             H           	   disabled          	   dss_core                         fck                      +                dispc@48050400            ti,omap3-dispc           H                      
   dss_dispc                        fck       encoder@4804fc00              ti,omap3-dsi             H    H    @H             proto phy pll                     	   disabled          	   dss_dsi1                            fck sys_clk                      +          encoder@48050800              ti,omap3-rfbi            H          	   disabled          	   dss_rfbi                            fck ick       encoder@48050c00              ti,omap3-venc            H          	   disabled          	   dss_venc                         fck          ssi-controller@48058000           ti,omap3-ssi             ssi          okay             H    H            sys gdd             G        gdd_mpu                      +                         s                ssi_ssr_fck ssi_sst_fck ssi_ick    ssi-port@4805a000             ti,omap3-ssi-port            H    H            tx rx               C   D      ssi-port@4805b000             ti,omap3-ssi-port            H    H            tx rx               E   F         pinmux@480025d8            ti,omap3-padconf pinctrl-single          H %   $                     +                                            '           E        isp@480bc000              ti,omap3-isp             H   H   |                               b      l                          ports                        +             bandgap@48002524             H %$             ti,omap34xx-bandgap                               target-module@480cb000            ti,sysc-omap3430-sr ti,sysc          smartreflex_core             H$           sysc                                    fck                      +                H       smartreflex@0             ti,omap3-smartreflex-core                                        target-module@480c9000            ti,sysc-omap3430-sr ti,sysc          smartreflex_mpu_iva          H$           sysc                                    fck                      +                H       smartreflex@480c9000              ti,omap3-smartreflex-mpu-iva                                         target-module@50000000            ti,sysc-omap2 ti,sysc            P             rev                         fck ick                      +                P     @          opp-table             operating-points-v2-ti-cpu          b                  opp1-125000000              sY@                            opp2-250000000              沀         g8 g8 g8                    .      opp3-500000000              e          O O O                 opp4-550000000               U         tx tx tx                 opp5-600000000              #F          p p p                 opp6-720000000              *T          p p p                    :         thermal-zones      cpu_thermal         E           [          i      N         v          trips      cpu_alert            8                   zpassive                   cpu_crit             _                	   zcritical             cooling-maps       map0                                         memory@80000000          smemory                          	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 mmc0 mmc1 mmc2 serial0 serial1 serial2 device_type reg clocks clock-names clock-latency operating-points-v2 #cooling-cells phandle interrupts ti,hwmods status ranges #pinctrl-cells #interrupt-cells interrupt-controller pinctrl-single,register-width pinctrl-single,function-mask syscon regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift reg-names ti,sysc-mask ti,sysc-sidle ti,syss-mask dmas dma-names clock-frequency ti,max-div ti,index-starts-at-one clock-mult clock-div ti,set-bit-to-disable ti,clock-mult ti,clock-div ti,set-rate-parent ti,index-power-of-two ti,low-power-stop ti,lock ti,low-power-bypass ti,dividers ti,sysc-midle #dma-cells dma-channels dma-requests ti,gpio-always-on gpio-controller #gpio-cells interrupts-extended #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,spi-num-cs ti,dual-volt pbias-supply #iommu-cells ti,#tlb-entries interrupt-names ti,buffer-size #sound-dai-cells ti,no-reset-on-init ti,no-idle ti,timer-alwon assigned-clocks assigned-clock-parents ti,timer-dsp ti,timer-pwm ti,timer-secure remote-wakeup-connected gpmc,num-cs gpmc,num-waitpins multipoint num-eps ram-bits iommus ti,phy-type #thermal-sensor-cells opp-hz opp-microvolt opp-supported-hw opp-suspend turbo-mode polling-delay-passive polling-delay coefficients thermal-sensors temperature hysteresis trip cooling-device 