 P   8      (            P                               ,    timll,omap3-devkit8000 ti,omap3430 ti,omap3                                  +         ,   7TimLL OMAP3 Devkit8000 with 4.3'' LCD panel    chosen        aliases          =/ocp@68000000/i2c@48070000           B/ocp@68000000/i2c@48072000           G/ocp@68000000/i2c@48060000           L/ocp@68000000/mmc@4809c000           Q/ocp@68000000/mmc@480b4000           V/ocp@68000000/mmc@480ad000           [/ocp@68000000/serial@4806a000            c/ocp@68000000/serial@4806c000            k/ocp@68000000/serial@49020000         	   s/display             |/connector0          /connector1       cpus                         +       cpu@0             arm,cortex-a8            cpu                                   cpu                                                       pmu@54000000              arm,cortex-a8-pmu            T                           debugss       soc           ti,omap-infra      mpu           ti,omap3-mpu             mpu       iva       
    ti,iva2.2            iva    dsp           ti,omap3-c64                ocp@68000000              ti,omap3-l3-smx simple-bus           h                  	   
                     +                      l3_main    l4@48000000           ti,omap3-l4-core simple-bus                      +                H         scm@2000              ti,omap3-scm simple-bus                                       +                           pinmux@30              ti,omap3-padconf pinctrl-single             0  8                     +                                   &        ;           Y     pinmux_twl4030_pins         v    A                  pinmux_dss_dpi_pins         v                                                                                                                                                                                                                         scm_conf@270              syscon simple-bus              p  0                     +                  p  0               pbias_regulator@2b0           ti,pbias-omap3 ti,pbias-omap                                pbias_mmc_omap2430          pbias_mmc_omap2430           w@         -                     clocks                       +       mcbsp5_mux_fck@68                         ti,composite-mux-clock                                        h                  mcbsp5_fck                        ti,composite-clock                                   mcbsp1_mux_fck@4                          ti,composite-mux-clock                                                    
      mcbsp1_fck                        ti,composite-clock              	   
                  mcbsp2_mux_fck@4                          ti,composite-mux-clock                                                          mcbsp2_fck                        ti,composite-clock                                   mcbsp3_mux_fck@68                         ti,composite-mux-clock                             h                  mcbsp3_fck                        ti,composite-clock                                   mcbsp4_mux_fck@68                         ti,composite-mux-clock                                        h                  mcbsp4_fck                        ti,composite-clock                                         clockdomains          pinmux@a00             ti,omap3-padconf pinctrl-single            
    \                     +                                   &        ;           Y     pinmux_twl4030_vpins             v                                                      target-module@480a6000            ti,sysc-omap2 ti,sysc            H
`D   H
`H   H
`L           rev sysc syss                                                                ick                      +                H
`        aes1@0            ti,omap3-aes                    P                           	      
        !tx rx            target-module@480c5000            ti,sysc-omap2 ti,sysc            HPD   HPH   HPL           rev sysc syss                                                                ick                      +                HP        aes2@0            ti,omap3-aes                    P                           A      B        !tx rx            prm@48306000              ti,omap3-prm             H0`   @                clocks                       +       virt_16_8m_ck                         fixed-clock         + Y                   osc_sys_ck@d40                        ti,mux-clock                                          @                  sys_ck@1270                       ti,divider-clock                                   ;              p         F                   sys_clkout1@d70                       ti,gate-clock                          p                 dpll3_x2_ck                       fixed-factor-clock                      ]           h         dpll3_m2x2_ck                         fixed-factor-clock                      ]           h                     dpll4_x2_ck                       fixed-factor-clock                      ]           h         corex2_fck                        fixed-factor-clock                      ]           h               !      wkup_l4_ick                       fixed-factor-clock                       ]           h               P      corex2_d3_fck                         fixed-factor-clock              !        ]           h                     corex2_d5_fck                         fixed-factor-clock              !        ]           h                        clockdomains             cm@48004000           ti,omap3-cm          H @   @    clocks                       +       dummy_apb_pclk                        fixed-clock         +          omap_32k_fck                          fixed-clock         +               B      virt_12m_ck                       fixed-clock         +                    virt_13m_ck                       fixed-clock         + ]@                  virt_19200000_ck                          fixed-clock         +$                   virt_26000000_ck                          fixed-clock         +                  virt_38_4m_ck                         fixed-clock         +I                   dpll4_ck@d00                          ti,omap3-dpll-per-clock                                   D  0                  dpll4_m2_ck@d48                       ti,divider-clock                        ;   ?           H         F            "      dpll4_m2x2_mul_ck                         fixed-factor-clock              "        ]           h               #      dpll4_m2x2_ck@d00                         ti,gate-clock               #                                r            $      omap_96m_alwon_fck                        fixed-factor-clock              $        ]           h               +      dpll3_ck@d00                          ti,omap3-dpll-core-clock                                      @  0                  dpll3_m3_ck@1140                          ti,divider-clock                                   ;              @         F            %      dpll3_m3x2_mul_ck                         fixed-factor-clock              %        ]           h               &      dpll3_m3x2_ck@d00                         ti,gate-clock               &                                r            '      emu_core_alwon_ck                         fixed-factor-clock              '        ]           h               d      sys_altclk                        fixed-clock         +                0      mcbsp_clks                        fixed-clock         +                      dpll3_m2_ck@d40                       ti,divider-clock                                   ;              @         F                  core_ck                       fixed-factor-clock                      ]           h               (      dpll1_fck@940                         ti,divider-clock                (                   ;              	@         F            )      dpll1_ck@904                          ti,omap3-dpll-clock                 )           	  	$  	@  	4                  dpll1_x2_ck                       fixed-factor-clock                      ]           h               *      dpll1_x2m2_ck@944                         ti,divider-clock                *        ;              	D         F            >      cm_96m_fck                        fixed-factor-clock              +        ]           h               ,      omap_96m_fck@d40                          ti,mux-clock                ,                          @            G      dpll4_m3_ck@e40                       ti,divider-clock                                   ;               @         F            -      dpll4_m3x2_mul_ck                         fixed-factor-clock              -        ]           h               .      dpll4_m3x2_ck@d00                         ti,gate-clock               .                                r            /      omap_54m_fck@d40                          ti,mux-clock                /   0                      @            :      cm_96m_d2_fck                         fixed-factor-clock              ,        ]           h               1      omap_48m_fck@d40                          ti,mux-clock                1   0                      @            2      omap_12m_fck                          fixed-factor-clock              2        ]           h               I      dpll4_m4_ck@e40                       ti,divider-clock                        ;              @         F            3      dpll4_m4x2_mul_ck                         ti,fixed-factor-clock               3                                           4      dpll4_m4x2_ck@d00                         ti,gate-clock               4                                r                           dpll4_m5_ck@f40                       ti,divider-clock                        ;   ?           @         F            5      dpll4_m5x2_mul_ck                         ti,fixed-factor-clock               5                                           6      dpll4_m5x2_ck@d00                         ti,gate-clock               6                                r                     l      dpll4_m6_ck@1140                          ti,divider-clock                                   ;   ?           @         F            7      dpll4_m6x2_mul_ck                         fixed-factor-clock              7        ]           h               8      dpll4_m6x2_ck@d00                         ti,gate-clock               8                                r            9      emu_per_alwon_ck                          fixed-factor-clock              9        ]           h               e      clkout2_src_gate_ck@d70                        ti,composite-no-wait-gate-clock             (                      p            ;      clkout2_src_mux_ck@d70                        ti,composite-mux-clock              (       ,   :           p            <      clkout2_src_ck                        ti,composite-clock              ;   <            =      sys_clkout2@d70                       ti,divider-clock                =                   ;   @           p               mpu_ck                        fixed-factor-clock              >        ]           h               ?      arm_fck@924                       ti,divider-clock                ?           	$        ;         emu_mpu_alwon_ck                          fixed-factor-clock              ?        ]           h               f      l3_ick@a40                        ti,divider-clock                (        ;              
@         F            @      l4_ick@a40                        ti,divider-clock                @                   ;              
@         F            A      rm_ick@c40                        ti,divider-clock                A                   ;              @         F      gpt10_gate_fck@a00                        ti,composite-gate-clock                                    
             C      gpt10_mux_fck@a40                         ti,composite-mux-clock              B                          
@            D      gpt10_fck                         ti,composite-clock              C   D      gpt11_gate_fck@a00                        ti,composite-gate-clock                                    
             E      gpt11_mux_fck@a40                         ti,composite-mux-clock              B                          
@            F      gpt11_fck                         ti,composite-clock              E   F      core_96m_fck                          fixed-factor-clock              G        ]           h                     mmchs2_fck@a00                        ti,wait-gate-clock                         
                              mmchs1_fck@a00                        ti,wait-gate-clock                         
                              i2c3_fck@a00                          ti,wait-gate-clock                         
                              i2c2_fck@a00                          ti,wait-gate-clock                         
                              i2c1_fck@a00                          ti,wait-gate-clock                         
                              mcbsp5_gate_fck@a00                       ti,composite-gate-clock                        
           
                   mcbsp1_gate_fck@a00                       ti,composite-gate-clock                        	           
             	      core_48m_fck                          fixed-factor-clock              2        ]           h               H      mcspi4_fck@a00                        ti,wait-gate-clock              H           
                              mcspi3_fck@a00                        ti,wait-gate-clock              H           
                              mcspi2_fck@a00                        ti,wait-gate-clock              H           
                              mcspi1_fck@a00                        ti,wait-gate-clock              H           
                              uart2_fck@a00                         ti,wait-gate-clock              H           
                              uart1_fck@a00                         ti,wait-gate-clock              H           
                              core_12m_fck                          fixed-factor-clock              I        ]           h               J      hdq_fck@a00                       ti,wait-gate-clock              J           
                              core_l3_ick                       fixed-factor-clock              @        ]           h               K      sdrc_ick@a10                          ti,wait-gate-clock              K           
                             gpmc_fck                          fixed-factor-clock              K        ]           h         core_l4_ick                       fixed-factor-clock              A        ]           h               L      mmchs2_ick@a10                        ti,omap3-interface-clock                L           
                             mmchs1_ick@a10                        ti,omap3-interface-clock                L           
                             hdq_ick@a10                       ti,omap3-interface-clock                L           
                             mcspi4_ick@a10                        ti,omap3-interface-clock                L           
                             mcspi3_ick@a10                        ti,omap3-interface-clock                L           
                             mcspi2_ick@a10                        ti,omap3-interface-clock                L           
                             mcspi1_ick@a10                        ti,omap3-interface-clock                L           
                             i2c3_ick@a10                          ti,omap3-interface-clock                L           
                             i2c2_ick@a10                          ti,omap3-interface-clock                L           
                             i2c1_ick@a10                          ti,omap3-interface-clock                L           
                             uart2_ick@a10                         ti,omap3-interface-clock                L           
                             uart1_ick@a10                         ti,omap3-interface-clock                L           
                             gpt11_ick@a10                         ti,omap3-interface-clock                L           
                             gpt10_ick@a10                         ti,omap3-interface-clock                L           
                             mcbsp5_ick@a10                        ti,omap3-interface-clock                L           
           
                  mcbsp1_ick@a10                        ti,omap3-interface-clock                L           
           	                  omapctrl_ick@a10                          ti,omap3-interface-clock                L           
                             dss_tv_fck@e00                        ti,gate-clock               :                                         dss_96m_fck@e00                       ti,gate-clock               G                                         dss2_alwon_fck@e00                        ti,gate-clock                                                         dummy_ck                          fixed-clock         +          gpt1_gate_fck@c00                         ti,composite-gate-clock                                                  M      gpt1_mux_fck@c40                          ti,composite-mux-clock              B               @            N      gpt1_fck                          ti,composite-clock              M   N                  aes2_ick@a10                          ti,omap3-interface-clock                L                      
                  wkup_32k_fck                          fixed-factor-clock              B        ]           h               O      gpio1_dbck@c00                        ti,gate-clock               O                                         sha12_ick@a10                         ti,omap3-interface-clock                L           
                             wdt2_fck@c00                          ti,wait-gate-clock              O                                         wdt2_ick@c10                          ti,omap3-interface-clock                P                                        wdt1_ick@c10                          ti,omap3-interface-clock                P                                        gpio1_ick@c10                         ti,omap3-interface-clock                P                                        omap_32ksync_ick@c10                          ti,omap3-interface-clock                P                                        gpt12_ick@c10                         ti,omap3-interface-clock                P                                        gpt1_ick@c10                          ti,omap3-interface-clock                P                                         per_96m_fck                       fixed-factor-clock              +        ]           h                     per_48m_fck                       fixed-factor-clock              2        ]           h               Q      uart3_fck@1000                        ti,wait-gate-clock              Q                                         gpt2_gate_fck@1000                        ti,composite-gate-clock                                                 R      gpt2_mux_fck@1040                         ti,composite-mux-clock              B               @            S      gpt2_fck                          ti,composite-clock              R   S                  gpt3_gate_fck@1000                        ti,composite-gate-clock                                                 T      gpt3_mux_fck@1040                         ti,composite-mux-clock              B                          @            U      gpt3_fck                          ti,composite-clock              T   U      gpt4_gate_fck@1000                        ti,composite-gate-clock                                                 V      gpt4_mux_fck@1040                         ti,composite-mux-clock              B                          @            W      gpt4_fck                          ti,composite-clock              V   W      gpt5_gate_fck@1000                        ti,composite-gate-clock                                                 X      gpt5_mux_fck@1040                         ti,composite-mux-clock              B                          @            Y      gpt5_fck                          ti,composite-clock              X   Y      gpt6_gate_fck@1000                        ti,composite-gate-clock                                                 Z      gpt6_mux_fck@1040                         ti,composite-mux-clock              B                          @            [      gpt6_fck                          ti,composite-clock              Z   [      gpt7_gate_fck@1000                        ti,composite-gate-clock                                                 \      gpt7_mux_fck@1040                         ti,composite-mux-clock              B                          @            ]      gpt7_fck                          ti,composite-clock              \   ]      gpt8_gate_fck@1000                        ti,composite-gate-clock                         	                        ^      gpt8_mux_fck@1040                         ti,composite-mux-clock              B                          @            _      gpt8_fck                          ti,composite-clock              ^   _      gpt9_gate_fck@1000                        ti,composite-gate-clock                         
                        `      gpt9_mux_fck@1040                         ti,composite-mux-clock              B                          @            a      gpt9_fck                          ti,composite-clock              `   a      per_32k_alwon_fck                         fixed-factor-clock              B        ]           h               b      gpio6_dbck@1000                       ti,gate-clock               b                                         gpio5_dbck@1000                       ti,gate-clock               b                                         gpio4_dbck@1000                       ti,gate-clock               b                                         gpio3_dbck@1000                       ti,gate-clock               b                                         gpio2_dbck@1000                       ti,gate-clock               b                                         wdt3_fck@1000                         ti,wait-gate-clock              b                                         per_l4_ick                        fixed-factor-clock              A        ]           h               c      gpio6_ick@1010                        ti,omap3-interface-clock                c                                        gpio5_ick@1010                        ti,omap3-interface-clock                c                                        gpio4_ick@1010                        ti,omap3-interface-clock                c                                        gpio3_ick@1010                        ti,omap3-interface-clock                c                                        gpio2_ick@1010                        ti,omap3-interface-clock                c                                        wdt3_ick@1010                         ti,omap3-interface-clock                c                                        uart3_ick@1010                        ti,omap3-interface-clock                c                                        uart4_ick@1010                        ti,omap3-interface-clock                c                                        gpt9_ick@1010                         ti,omap3-interface-clock                c                      
                  gpt8_ick@1010                         ti,omap3-interface-clock                c                      	                  gpt7_ick@1010                         ti,omap3-interface-clock                c                                        gpt6_ick@1010                         ti,omap3-interface-clock                c                                        gpt5_ick@1010                         ti,omap3-interface-clock                c                                        gpt4_ick@1010                         ti,omap3-interface-clock                c                                        gpt3_ick@1010                         ti,omap3-interface-clock                c                                        gpt2_ick@1010                         ti,omap3-interface-clock                c                                        mcbsp2_ick@1010                       ti,omap3-interface-clock                c                                         mcbsp3_ick@1010                       ti,omap3-interface-clock                c                                        mcbsp4_ick@1010                       ti,omap3-interface-clock                c                                        mcbsp2_gate_fck@1000                          ti,composite-gate-clock                                                       mcbsp3_gate_fck@1000                          ti,composite-gate-clock                                                      mcbsp4_gate_fck@1000                          ti,composite-gate-clock                                                      emu_src_mux_ck@1140                       ti,mux-clock                    d   e   f           @            g      emu_src_ck                        ti,clkdm-gate-clock             g            h      pclk_fck@1140                         ti,divider-clock                h                   ;              @         F      pclkx2_fck@1140                       ti,divider-clock                h                   ;              @         F      atclk_fck@1140                        ti,divider-clock                h                   ;              @         F      traceclk_src_fck@1140                         ti,mux-clock                    d   e   f                      @            i      traceclk_fck@1140                         ti,divider-clock                i                   ;              @         F      secure_32k_fck                        fixed-clock         +               j      gpt12_fck                         fixed-factor-clock              j        ]           h                     wdt1_fck                          fixed-factor-clock              j        ]           h         security_l4_ick2                          fixed-factor-clock              A        ]           h               k      aes1_ick@a14                          ti,omap3-interface-clock                k                      
                  rng_ick@a14                       ti,omap3-interface-clock                k           
                             sha11_ick@a14                         ti,omap3-interface-clock                k           
                 des1_ick@a14                          ti,omap3-interface-clock                k           
                  cam_mclk@f00                          ti,gate-clock               l                                       cam_ick@f10                   !    ti,omap3-no-wait-interface-clock                A                                         csi2_96m_fck@f00                          ti,gate-clock                                                        security_l3_ick                       fixed-factor-clock              @        ]           h               m      pka_ick@a14                       ti,omap3-interface-clock                m           
                 icr_ick@a10                       ti,omap3-interface-clock                L           
                 des2_ick@a10                          ti,omap3-interface-clock                L           
                 mspro_ick@a10                         ti,omap3-interface-clock                L           
                 mailboxes_ick@a10                         ti,omap3-interface-clock                L           
                 ssi_l4_ick                        fixed-factor-clock              A        ]           h               t      sr1_fck@c00                       ti,wait-gate-clock                                                       sr2_fck@c00                       ti,wait-gate-clock                                                       sr_l4_ick                         fixed-factor-clock              A        ]           h         dpll2_fck@40                          ti,divider-clock                (                   ;               @         F            n      dpll2_ck@4                        ti,omap3-dpll-clock                 n               $   @   4                                       o      dpll2_m2_ck@44                        ti,divider-clock                o        ;               D         F            p      iva2_ck@0                         ti,wait-gate-clock              p                                           modem_fck@a00                         ti,omap3-interface-clock                            
                              sad2d_ick@a10                         ti,omap3-interface-clock                @           
                             mad2d_ick@a18                         ti,omap3-interface-clock                @           
                             mspro_fck@a00                         ti,wait-gate-clock                         
                  ssi_ssr_gate_fck_3430es2@a00                           ti,composite-no-wait-gate-clock             !                       
             q      ssi_ssr_div_fck_3430es2@a40                       ti,composite-divider-clock              !                      
@      $                                            r      ssi_ssr_fck_3430es2                       ti,composite-clock              q   r            s      ssi_sst_fck_3430es2                       fixed-factor-clock              s        ]           h                     hsotgusb_ick_3430es2@a10                      "    ti,omap3-hsotgusb-interface-clock               K           
                             ssi_ick_3430es2@a10                       ti,omap3-ssi-interface-clock                t           
                              usim_gate_fck@c00                         ti,composite-gate-clock             G           	                              sys_d2_ck                         fixed-factor-clock                       ]           h               v      omap_96m_d2_fck                       fixed-factor-clock              G        ]           h               w      omap_96m_d4_fck                       fixed-factor-clock              G        ]           h               x      omap_96m_d8_fck                       fixed-factor-clock              G        ]           h               y      omap_96m_d10_fck                          fixed-factor-clock              G        ]           h   
            z      dpll5_m2_d4_ck                        fixed-factor-clock              u        ]           h               {      dpll5_m2_d8_ck                        fixed-factor-clock              u        ]           h               |      dpll5_m2_d16_ck                       fixed-factor-clock              u        ]           h               }      dpll5_m2_d20_ck                       fixed-factor-clock              u        ]           h               ~      usim_mux_fck@c40                          ti,composite-mux-clock        (          v   w   x   y   z   {   |   }   ~                      @         F                  usim_fck                          ti,composite-clock                       usim_ick@c10                          ti,omap3-interface-clock                P                      	                  dpll5_ck@d04                          ti,omap3-dpll-clock                               $  L  4                                    dpll5_m2_ck@d50                       ti,divider-clock                        ;              P         F            u      sgx_gate_fck@b00                          ti,composite-gate-clock             (                                         core_d3_ck                        fixed-factor-clock              (        ]           h                     core_d4_ck                        fixed-factor-clock              (        ]           h                     core_d6_ck                        fixed-factor-clock              (        ]           h                     omap_192m_alwon_fck                       fixed-factor-clock              $        ]           h                     core_d2_ck                        fixed-factor-clock              (        ]           h                     sgx_mux_fck@b40                       ti,composite-mux-clock                        ,                       @                  sgx_fck                       ti,composite-clock                                  sgx_ick@b10                       ti,wait-gate-clock              @                                         cpefuse_fck@a08                       ti,gate-clock                           
                              ts_fck@a08                        ti,gate-clock               B           
                             usbtll_fck@a08                        ti,wait-gate-clock              u           
                             usbtll_ick@a18                        ti,omap3-interface-clock                L           
                             mmchs3_ick@a10                        ti,omap3-interface-clock                L           
                             mmchs3_fck@a00                        ti,wait-gate-clock                         
                              dss1_alwon_fck_3430es2@e00                        ti,dss-gate-clock                                                                  dss_ick_3430es2@e10                       ti,omap3-dss-interface-clock                A                                         usbhost_120m_fck@1400                         ti,gate-clock               u                                         usbhost_48m_fck@1400                          ti,dss-gate-clock               2                                          usbhost_ick@1410                          ti,omap3-dss-interface-clock                A                                            clockdomains       core_l3_clkdm             ti,clockdomain                       dpll3_clkdm           ti,clockdomain                    dpll1_clkdm           ti,clockdomain                    per_clkdm             ti,clockdomain        h                                                                                       emu_clkdm             ti,clockdomain              h      dpll4_clkdm           ti,clockdomain                    wkup_clkdm            ti,clockdomain        $                                    dss_clkdm             ti,clockdomain                                core_l4_clkdm             ti,clockdomain                                                                                                                                cam_clkdm             ti,clockdomain                       iva2_clkdm            ti,clockdomain                    dpll2_clkdm           ti,clockdomain              o      d2d_clkdm             ti,clockdomain                          dpll5_clkdm           ti,clockdomain                    sgx_clkdm             ti,clockdomain                    usbhost_clkdm             ti,clockdomain                                target-module@48320000            ti,sysc-omap2 ti,sysc            H2     H2          	  rev sysc                               O            fck ick                      +                H2        counter@0             ti,omap-counter32k                            interrupt-controller@48200000             ti,omap3-intc            &                    H                        target-module@48056000            ti,sysc-omap2 ti,sysc            H`    H`,   H`(           rev sysc syss             #                                                           K         ick                      +                H`       dma-controller@0              ti,omap3430-sdma ti,omap-sdma                                                                       ,   `                     gpio@48310000             ti,omap3-gpio            H1                          gpio1            9         K        [            &                             gpio@49050000             ti,omap3-gpio            I                          gpio2            K        [            &                 gpio@49052000             ti,omap3-gpio            I                          gpio3            K        [            &                 gpio@49054000             ti,omap3-gpio            I@                          gpio4            K        [            &                 gpio@49056000             ti,omap3-gpio            I`                !         gpio5            K        [            &                 gpio@49058000             ti,omap3-gpio            I                "         gpio6            K        [            &                            serial@4806a000           ti,omap3-uart            H             g      H              1      2        !tx rx            uart1           +l       serial@4806c000           ti,omap3-uart            H            g      I              3      4        !tx rx            uart2           +l       serial@49020000           ti,omap3-uart            I             g      J              5      6        !tx rx            uart3           +l       i2c@48070000              ti,omap3-i2c             H                 8                            !tx rx                        +             i2c1            + '@   twl@48              H                      ti,twl4030           &                   {default                  audio             ti,twl4030-audio       codec            rtc           ti,twl4030-rtc                    bci           ti,twl4030-bci              	                                    vac       watchdog              ti,twl4030-wdt        regulator-vaux1           ti,twl4030-vaux1          regulator-vaux2           ti,twl4030-vaux2          regulator-vaux3           ti,twl4030-vaux3          regulator-vaux4           ti,twl4030-vaux4          regulator-vdd1            ti,twl4030-vdd1          	'                regulator-vdac            ti,twl4030-vdac          w@         w@                  regulator-vio             ti,twl4030-vio           w@         w@                  regulator-vintana1            ti,twl4030-vintana1       regulator-vintana2            ti,twl4030-vintana2       regulator-vintdig             ti,twl4030-vintdig        regulator-vmmc1           ti,twl4030-vmmc1             :         0                  regulator-vmmc2           ti,twl4030-vmmc2             :         0      regulator-vusb1v5             ti,twl4030-vusb1v5                    regulator-vusb1v8             ti,twl4030-vusb1v8                    regulator-vusb3v1             ti,twl4030-vusb3v1                    regulator-vpll1           ti,twl4030-vpll1          	  vdds_dsi             w@         w@                  regulator-vpll2           ti,twl4030-vpll2             w@         w@      regulator-vsim            ti,twl4030-vsim          w@         -                  gpio              ti,twl4030-gpio          K        [            &                                        	      twl4030-usb           ti,twl4030-usb              
                                                       
          pwm           ti,twl4030-pwm                   pwmled            ti,twl4030-pwmled                    pwrbutton             ti,twl4030-pwrbutton                      keypad            ti,twl4030-keypad                                   0         D  C            ?   	 
 @  A  B   s r      madc              ti,twl4030-madc                     P                           i2c@48072000              ti,omap3-i2c             H                 9                            !tx rx                        +             i2c2            +                  i2c@48060000              ti,omap3-i2c             H                 =                            !tx rx                        +             i2c3          	  bdisabled          mailbox@48094000              ti,omap3-mailbox             mailbox          H	@                        i           u                 dsp                                                 spi@48098000              ti,omap2-mcspi           H	                A                     +             mcspi1                   @        #      $      %      &      '      (      )      *         !tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3       spi@4809a000              ti,omap2-mcspi           H	                B                     +             mcspi2                            +      ,      -      .        !tx0 rx0 tx1 rx1    ads7846@0             ti,ads7846                                   `                                                                                                                        + 
          ;           K           [           k                     spi@480b8000              ti,omap2-mcspi           H                [                     +             mcspi3                                                      !tx0 rx0 tx1 rx1       spi@480ba000              ti,omap2-mcspi           H                0                     +             mcspi4                           F      G        !tx0 rx0       1w@480b2000           ti,omap3-1w          H                 :         hdq1w         mmc@4809c000              ti,omap3-hsmmc           H	                S         mmc1                           =      >        !tx rx                                                     mmc@480b4000              ti,omap3-hsmmc           H@                V         mmc2                  /      0        !tx rx         	  bdisabled          mmc@480ad000              ti,omap3-hsmmc           H
                ^         mmc3                  M      N        !tx rx         	  bdisabled          mmu@480bd400                          ti,omap2-iommu           H                         mmu_isp                             mmu@5d000000                          ti,omap2-iommu           ]                           mmu_iva       	  bdisabled          wdt@48314000              ti,omap3-wdt             H1@          
   wd_timer2         	  bdisabled          mcbsp@48074000            ti,omap3-mcbsp           H@            mpu                ;   <        common tx rx                        mcbsp1                               !tx rx                        fck       	  bdisabled          target-module@480a0000            ti,sysc-omap2 ti,sysc            H
 <   H
 @   H
 D           rev sysc syss                                                             ick                      +                H
         rng@0             ti,omap2-rng                                 4         mcbsp@49022000            ti,omap3-mcbsp           I     I            mpu sidetone                   >   ?           common tx rx sidetone                       mcbsp2 mcbsp2_sidetone                !      "        !tx rx                           fck ick         bokay               
      mcbsp@49024000            ti,omap3-mcbsp           I@    I            mpu sidetone                   Y   Z           common tx rx sidetone                       mcbsp3 mcbsp3_sidetone                              !tx rx                           fck ick       	  bdisabled          mcbsp@49026000            ti,omap3-mcbsp           I`            mpu                6   7        common tx rx                        mcbsp4                              !tx rx                        fck                   	  bdisabled          mcbsp@48096000            ti,omap3-mcbsp           H	`            mpu                Q   R        common tx rx                        mcbsp5                              !tx rx                        fck       	  bdisabled          sham@480c3000             ti,omap3-sham            sham             H0    d            1              E        !rx        target-module@48318000            ti,sysc-omap2-timer ti,sysc          H1    H1   H1           rev sysc syss             '                                                     fck ick                      +                H1       timer@0           ti,omap3430-timer                                        fck             %                   (   B         target-module@49032000            ti,sysc-omap2-timer ti,sysc          I     I    I            rev sysc syss             '                                                     fck ick                      +                I        timer@0           ti,omap3430-timer                               &         timer@49034000            ti,omap3430-timer            I@                '         timer3        timer@49036000            ti,omap3430-timer            I`                (         timer4        timer@49038000            ti,omap3430-timer            I                )         timer5           ?      timer@4903a000            ti,omap3430-timer            I                *         timer6           ?      timer@4903c000            ti,omap3430-timer            I                +         timer7           ?      timer@4903e000            ti,omap3430-timer            I                ,         timer8           L         ?      timer@49040000            ti,omap3430-timer            I                 -         timer9           L      timer@48086000            ti,omap3430-timer            H`                .         timer10          L      timer@48088000            ti,omap3430-timer            H                /         timer11          L      target-module@48304000            ti,sysc-omap2-timer ti,sysc          H0@    H0@   H0@           rev sysc syss             '                                                     fck ick                      +                H0@             Y         m   timer@0           ti,omap3430-timer                               _         x                  usbhstll@48062000             ti,usbhs-tll             H                 N         usb_tll_hs        usbhshost@48064000            ti,usbhs-host            H@             usb_host_hs                      +                ohci@48064400             ti,ohci-omap3            HD                L               ehci@48064800             ti,ehci-omap             HH                M         gpmc@6e000000             ti,omap3430-gpmc             gpmc             n                                       !rxtx                                               +            &                    K        [                     0             ,                     nand@0,0              ti,omap2-nand                                                                                         sw                                     ,        /   ,        A           P   "        c   ,        v   (           6           @           R           R           (                                 +      x-loader@0        	  X-Loader                          bootloaders@80000           U-Boot                       bootloaders_env@260000          U-Boot Env            &           kernel@280000           Kernel            (   @        filesystem@680000           File System           h             ethernet@6,0              davicom,dm9000                                                                                                             $            2           L                                 /           A            P           c   0        f   6                   t   6        v                                                          Z           Z                                                         usb_otg_hs@480ab000           ti,omap3-musb            H
                \   ]        mc dma           usb_otg_hs                     	           	         dss@48050000              ti,omap3-dss             H             bokay          	   dss_core                         fck                      +                     {default                    	           	(      dispc@48050400            ti,omap3-dispc           H                      
   dss_dispc                        fck       encoder@4804fc00              ti,omap3-dsi             H    H    @H             proto phy pll                     	  bdisabled          	   dss_dsi1                            fck sys_clk                      +          encoder@48050800              ti,omap3-rfbi            H          	  bdisabled          	   dss_rfbi                            fck ick       encoder@48050c00              ti,omap3-venc            H            bokay          	   dss_venc                         fck         	8      port       endpoint            	D           	T                          port                         +       endpoint@0                       	D           	`                    endpoint@1                      	D           	`                          ssi-controller@48058000           ti,omap3-ssi             ssi         bokay             H    H            sys gdd             G        gdd_mpu                      +                         s                ssi_ssr_fck ssi_sst_fck ssi_ick    ssi-port@4805a000             ti,omap3-ssi-port            H    H            tx rx               C   D      ssi-port@4805b000             ti,omap3-ssi-port            H    H            tx rx               E   F         pinmux@480025d8            ti,omap3-padconf pinctrl-single          H %   $                     +                                   &        ;           Y        isp@480bc000              ti,omap3-isp             H   H   |                    	k                l        	r                  ports                        +             bandgap@48002524             H %$             ti,omap34xx-bandgap         	~                     target-module@480cb000            ti,sysc-omap3430-sr ti,sysc          smartreflex_core             H$           sysc                                   fck                      +                H       smartreflex@0             ti,omap3-smartreflex-core                                        target-module@480c9000            ti,sysc-omap3430-sr ti,sysc          smartreflex_mpu_iva          H$           sysc                                   fck                      +                H       smartreflex@480c9000              ti,omap3-smartreflex-mpu-iva                                         target-module@50000000            ti,sysc-omap2 ti,sysc            P             rev                        fck ick                      +                P     @          opp-table             operating-points-v2-ti-cpu                            opp1-125000000          	    sY@        	           	         opp2-250000000          	    沀        	 g8 g8 g8        	            	      opp3-500000000          	    e         	 O O O        	         opp4-550000000          	     U        	 tx tx tx        	         opp5-600000000          	    #F         	 p p p        	         opp6-720000000          	    *T         	 p p p        	            	         thermal-zones      cpu_thermal         	           	          	      N         
         trips      cpu_alert           
 8        
           passive                  cpu_crit            
 _        
        	   critical             cooling-maps       map0            
)          
.                 memory@80000000          memory                       leds          
    gpio-leds      heartbeat           devkit8000::led1            
=                 
Con        
  
Qheartbeat         mmc         devkit8000::led2            
=                 
Con          
Qnone          usr         devkit8000::led3            
=                 
Con          
Qusr       pmu_stat            devkit8000::pmu_stat            
=  	                sound             ti,omap-twl4030         
gdevkit8000          
p  
      I  
yExt Spk PREDRIVEL Ext Spk PREDRIVER MAINMIC Main Mic Main Mic Mic Bias 1          gpio_keys         
    gpio-keys      user            user            
=                  
                    encoder0          
    ti,tfp410           
  	         ports                        +       port@0                  endpoint            	D                       port@1                 endpoint            	D                            connector0            dvi-connector           dvi          
        
     port       endpoint            	D                         connector1            svideo-connector            tv     port       endpoint            	D                          display       
    panel-dpi           lcd         
  	          port       endpoint            	D                       panel-timing            +         
          
          
           
           
   )        
                         
                    )            6           @               	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 mmc0 mmc1 mmc2 serial0 serial1 serial2 display0 display1 display2 device_type reg clocks clock-names clock-latency operating-points-v2 #cooling-cells phandle interrupts ti,hwmods ranges #pinctrl-cells #interrupt-cells interrupt-controller pinctrl-single,register-width pinctrl-single,function-mask pinctrl-single,pins syscon regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift reg-names ti,sysc-mask ti,sysc-sidle ti,syss-mask dmas dma-names clock-frequency ti,max-div ti,index-starts-at-one clock-mult clock-div ti,set-bit-to-disable ti,clock-mult ti,clock-div ti,set-rate-parent ti,index-power-of-two ti,low-power-stop ti,lock ti,low-power-bypass ti,dividers ti,sysc-midle #dma-cells dma-channels dma-requests ti,gpio-always-on gpio-controller #gpio-cells interrupts-extended pinctrl-names pinctrl-0 bci3v1-supply io-channels io-channel-names ti,use-leds ti,pulldowns usb1v5-supply usb1v8-supply usb3v1-supply usb_mode #phy-cells #pwm-cells keypad,num-rows keypad,num-columns linux,keymap #io-channel-cells status #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,spi-num-cs vcc-supply spi-max-frequency pendown-gpio ti,x-min ti,x-max ti,y-min ti,y-max ti,x-plate-ohms ti,pressure-max ti,debounce-max ti,debounce-tol ti,debounce-rep ti,keep-vref-on ti,settle-delay-usec wakeup-source ti,dual-volt pbias-supply vmmc-supply vqmmc-supply bus-width #iommu-cells ti,#tlb-entries interrupt-names ti,buffer-size #sound-dai-cells assigned-clocks assigned-clock-parents ti,timer-dsp ti,timer-pwm ti,no-reset-on-init ti,no-idle ti,timer-alwon ti,timer-secure remote-wakeup-connected gpmc,num-cs gpmc,num-waitpins nand-bus-width gpmc,device-width ti,nand-ecc-opt gpmc,sync-clk-ps gpmc,cs-on-ns gpmc,cs-rd-off-ns gpmc,cs-wr-off-ns gpmc,adv-on-ns gpmc,adv-rd-off-ns gpmc,adv-wr-off-ns gpmc,we-off-ns gpmc,oe-off-ns gpmc,access-ns gpmc,rd-cycle-ns gpmc,wr-cycle-ns gpmc,wr-access-ns gpmc,wr-data-mux-bus-ns label bank-width davicom,no-eeprom gpmc,mux-add-data gpmc,wait-pin gpmc,cycle2cycle-samecsen gpmc,cycle2cycle-diffcsen gpmc,oe-on-ns gpmc,we-on-ns gpmc,page-burst-access-ns gpmc,bus-turnaround-ns gpmc,cycle2cycle-delay-ns gpmc,wait-monitoring-ns gpmc,clk-activation-ns multipoint num-eps ram-bits vdds_dsi-supply vdda_dac-supply vdda-supply remote-endpoint ti,channels data-lines iommus ti,phy-type #thermal-sensor-cells opp-hz opp-microvolt opp-supported-hw opp-suspend turbo-mode polling-delay-passive polling-delay coefficients thermal-sensors temperature hysteresis trip cooling-device gpios default-state linux,default-trigger ti,model ti,mcbsp ti,audio-routing linux,code powerdown-gpios digital ddc-i2c-bus enable-gpios hactive vactive hfront-porch hback-porch hsync-len vback-porch vfront-porch vsync-len hsync-active vsync-active de-active pixelclk-active 