     8     (                                           '    amazon,omap3-echo ti,omap3630 ti,omap3                                   +            7Amazon Echo (first generation)     chosen        aliases          =/ocp@68000000/i2c@48070000           B/ocp@68000000/i2c@48072000           G/ocp@68000000/i2c@48060000           L/ocp@68000000/mmc@4809c000           Q/ocp@68000000/mmc@480b4000           V/ocp@68000000/mmc@480ad000           [/ocp@68000000/serial@4806a000            c/ocp@68000000/serial@4806c000            k/ocp@68000000/serial@49020000            s/ocp@68000000/serial@49042000         cpus                         +       cpu@0             arm,cortex-a8            {cpu                                   cpu                                                                               pmu@54000000              arm,cortex-a8-pmu            T                           debugss       soc           ti,omap-infra      mpu           ti,omap3-mpu             mpu       iva       
    ti,iva2.2            iva    dsp           ti,omap3-c64                ocp@68000000              ti,omap3-l3-smx simple-bus           h                  	   
                     +                     l3_main    l4@48000000           ti,omap3-l4-core simple-bus                      +               H         scm@2000              ti,omap3-scm simple-bus                                       +                          pinmux@30              ti,omap3-padconf pinctrl-single             0  8                     +            
                       *        ?           ]     pinmux_tps_pins         z    w                  pinmux_button_pins          z                           pinmux_mmc1_pins          0  z                                          pinmux_mmc2_pins          P  z  (    *    ,    .    0    2    4    6    8    :                       scm_conf@270              syscon simple-bus              p  0                     +                 p  0               pbias_regulator@2b0           ti,pbias-omap3 ti,pbias-omap                                pbias_mmc_omap2430          pbias_mmc_omap2430           w@         -                     clocks                       +       mcbsp5_mux_fck@68                         ti,composite-mux-clock                                        h            
      mcbsp5_fck                        ti,composite-clock              	   
                  mcbsp1_mux_fck@4                          ti,composite-mux-clock                                                          mcbsp1_fck                        ti,composite-clock                                   mcbsp2_mux_fck@4                          ti,composite-mux-clock                                                          mcbsp2_fck                        ti,composite-clock                                   mcbsp3_mux_fck@68                         ti,composite-mux-clock                             h                  mcbsp3_fck                        ti,composite-clock                                   mcbsp4_mux_fck@68                         ti,composite-mux-clock                                        h                  mcbsp4_fck                        ti,composite-clock                                         clockdomains          pinmux@a00             ti,omap3-padconf pinctrl-single            
    \                     +            
                       *        ?           ]              target-module@480a6000            ti,sysc-omap2 ti,sysc            H
`D   H
`H   H
`L           rev sysc syss                                                                ick                      +               H
`        aes1@0            ti,omap3-aes                    P                            	      
        %tx rx            target-module@480c5000            ti,sysc-omap2 ti,sysc            HPD   HPH   HPL           rev sysc syss                                                                ick                      +               HP        aes2@0            ti,omap3-aes                    P                            A      B        %tx rx            prm@48306000              ti,omap3-prm             H0`   @                clocks                       +       virt_16_8m_ck                         fixed-clock         / Y                   osc_sys_ck@d40                        ti,mux-clock                                          @                  sys_ck@1270                       ti,divider-clock                                   ?              p         J            "      sys_clkout1@d70                       ti,gate-clock                          p                 dpll3_x2_ck                       fixed-factor-clock                      a           l         dpll3_m2x2_ck                         fixed-factor-clock                      a           l               !      dpll4_x2_ck                       fixed-factor-clock                       a           l         corex2_fck                        fixed-factor-clock              !        a           l               #      wkup_l4_ick                       fixed-factor-clock              "        a           l               R      corex2_d3_fck                         fixed-factor-clock              #        a           l                     corex2_d5_fck                         fixed-factor-clock              #        a           l                        clockdomains             cm@48004000           ti,omap3-cm          H @   @    clocks                       +       dummy_apb_pclk                        fixed-clock         /          omap_32k_fck                          fixed-clock         /               D      virt_12m_ck                       fixed-clock         /                    virt_13m_ck                       fixed-clock         / ]@                  virt_19200000_ck                          fixed-clock         /$                   virt_26000000_ck                          fixed-clock         /                  virt_38_4m_ck                         fixed-clock         /I                   dpll4_ck@d00                          ti,omap3-dpll-per-j-type-clock              "   "                 D  0                   dpll4_m2_ck@d48                       ti,divider-clock                         ?   ?           H         J            $      dpll4_m2x2_mul_ck                         fixed-factor-clock              $        a           l               %      dpll4_m2x2_ck@d00                         ti,hsdiv-gate-clock             %                                v            &      omap_96m_alwon_fck                        fixed-factor-clock              &        a           l               -      dpll3_ck@d00                          ti,omap3-dpll-core-clock                "   "                 @  0                  dpll3_m3_ck@1140                          ti,divider-clock                                   ?              @         J            '      dpll3_m3x2_mul_ck                         fixed-factor-clock              '        a           l               (      dpll3_m3x2_ck@d00                         ti,hsdiv-gate-clock             (                                v            )      emu_core_alwon_ck                         fixed-factor-clock              )        a           l               f      sys_altclk                        fixed-clock         /                2      mcbsp_clks                        fixed-clock         /                      dpll3_m2_ck@d40                       ti,divider-clock                                   ?              @         J                  core_ck                       fixed-factor-clock                      a           l               *      dpll1_fck@940                         ti,divider-clock                *                   ?              	@         J            +      dpll1_ck@904                          ti,omap3-dpll-clock             "   +           	  	$  	@  	4                  dpll1_x2_ck                       fixed-factor-clock                      a           l               ,      dpll1_x2m2_ck@944                         ti,divider-clock                ,        ?              	D         J            @      cm_96m_fck                        fixed-factor-clock              -        a           l               .      omap_96m_fck@d40                          ti,mux-clock                .   "                      @            I      dpll4_m3_ck@e40                       ti,divider-clock                                    ?               @         J            /      dpll4_m3x2_mul_ck                         fixed-factor-clock              /        a           l               0      dpll4_m3x2_ck@d00                         ti,hsdiv-gate-clock             0                                v            1      omap_54m_fck@d40                          ti,mux-clock                1   2                      @            <      cm_96m_d2_fck                         fixed-factor-clock              .        a           l               3      omap_48m_fck@d40                          ti,mux-clock                3   2                      @            4      omap_12m_fck                          fixed-factor-clock              4        a           l               K      dpll4_m4_ck@e40                       ti,divider-clock                         ?              @         J            5      dpll4_m4x2_mul_ck                         ti,fixed-factor-clock               5                                           6      dpll4_m4x2_ck@d00                         ti,gate-clock               6                                v                           dpll4_m5_ck@f40                       ti,divider-clock                         ?   ?           @         J            7      dpll4_m5x2_mul_ck                         ti,fixed-factor-clock               7                                           8      dpll4_m5x2_ck@d00                         ti,hsdiv-gate-clock             8                                v                     n      dpll4_m6_ck@1140                          ti,divider-clock                                    ?   ?           @         J            9      dpll4_m6x2_mul_ck                         fixed-factor-clock              9        a           l               :      dpll4_m6x2_ck@d00                         ti,hsdiv-gate-clock             :                                v            ;      emu_per_alwon_ck                          fixed-factor-clock              ;        a           l               g      clkout2_src_gate_ck@d70                        ti,composite-no-wait-gate-clock             *                      p            =      clkout2_src_mux_ck@d70                        ti,composite-mux-clock              *   "   .   <           p            >      clkout2_src_ck                        ti,composite-clock              =   >            ?      sys_clkout2@d70                       ti,divider-clock                ?                   ?   @           p               mpu_ck                        fixed-factor-clock              @        a           l               A      arm_fck@924                       ti,divider-clock                A           	$        ?         emu_mpu_alwon_ck                          fixed-factor-clock              A        a           l               h      l3_ick@a40                        ti,divider-clock                *        ?              
@         J            B      l4_ick@a40                        ti,divider-clock                B                   ?              
@         J            C      rm_ick@c40                        ti,divider-clock                C                   ?              @         J      gpt10_gate_fck@a00                        ti,composite-gate-clock             "                      
             E      gpt10_mux_fck@a40                         ti,composite-mux-clock              D   "                      
@            F      gpt10_fck                         ti,composite-clock              E   F      gpt11_gate_fck@a00                        ti,composite-gate-clock             "                      
             G      gpt11_mux_fck@a40                         ti,composite-mux-clock              D   "                      
@            H      gpt11_fck                         ti,composite-clock              G   H      core_96m_fck                          fixed-factor-clock              I        a           l                     mmchs2_fck@a00                        ti,wait-gate-clock                         
                              mmchs1_fck@a00                        ti,wait-gate-clock                         
                              i2c3_fck@a00                          ti,wait-gate-clock                         
                              i2c2_fck@a00                          ti,wait-gate-clock                         
                              i2c1_fck@a00                          ti,wait-gate-clock                         
                              mcbsp5_gate_fck@a00                       ti,composite-gate-clock                        
           
             	      mcbsp1_gate_fck@a00                       ti,composite-gate-clock                        	           
                   core_48m_fck                          fixed-factor-clock              4        a           l               J      mcspi4_fck@a00                        ti,wait-gate-clock              J           
                              mcspi3_fck@a00                        ti,wait-gate-clock              J           
                              mcspi2_fck@a00                        ti,wait-gate-clock              J           
                              mcspi1_fck@a00                        ti,wait-gate-clock              J           
                              uart2_fck@a00                         ti,wait-gate-clock              J           
                              uart1_fck@a00                         ti,wait-gate-clock              J           
                              core_12m_fck                          fixed-factor-clock              K        a           l               L      hdq_fck@a00                       ti,wait-gate-clock              L           
                              core_l3_ick                       fixed-factor-clock              B        a           l               M      sdrc_ick@a10                          ti,wait-gate-clock              M           
                             gpmc_fck                          fixed-factor-clock              M        a           l         core_l4_ick                       fixed-factor-clock              C        a           l               N      mmchs2_ick@a10                        ti,omap3-interface-clock                N           
                             mmchs1_ick@a10                        ti,omap3-interface-clock                N           
                             hdq_ick@a10                       ti,omap3-interface-clock                N           
                             mcspi4_ick@a10                        ti,omap3-interface-clock                N           
                             mcspi3_ick@a10                        ti,omap3-interface-clock                N           
                             mcspi2_ick@a10                        ti,omap3-interface-clock                N           
                             mcspi1_ick@a10                        ti,omap3-interface-clock                N           
                             i2c3_ick@a10                          ti,omap3-interface-clock                N           
                             i2c2_ick@a10                          ti,omap3-interface-clock                N           
                             i2c1_ick@a10                          ti,omap3-interface-clock                N           
                             uart2_ick@a10                         ti,omap3-interface-clock                N           
                             uart1_ick@a10                         ti,omap3-interface-clock                N           
                             gpt11_ick@a10                         ti,omap3-interface-clock                N           
                             gpt10_ick@a10                         ti,omap3-interface-clock                N           
                             mcbsp5_ick@a10                        ti,omap3-interface-clock                N           
           
                  mcbsp1_ick@a10                        ti,omap3-interface-clock                N           
           	                  omapctrl_ick@a10                          ti,omap3-interface-clock                N           
                             dss_tv_fck@e00                        ti,gate-clock               <                                         dss_96m_fck@e00                       ti,gate-clock               I                                         dss2_alwon_fck@e00                        ti,gate-clock               "                                         dummy_ck                          fixed-clock         /          gpt1_gate_fck@c00                         ti,composite-gate-clock             "                                    O      gpt1_mux_fck@c40                          ti,composite-mux-clock              D   "           @            P      gpt1_fck                          ti,composite-clock              O   P                  aes2_ick@a10                          ti,omap3-interface-clock                N                      
                  wkup_32k_fck                          fixed-factor-clock              D        a           l               Q      gpio1_dbck@c00                        ti,gate-clock               Q                                         sha12_ick@a10                         ti,omap3-interface-clock                N           
                             wdt2_fck@c00                          ti,wait-gate-clock              Q                                         wdt2_ick@c10                          ti,omap3-interface-clock                R                                        wdt1_ick@c10                          ti,omap3-interface-clock                R                                        gpio1_ick@c10                         ti,omap3-interface-clock                R                                        omap_32ksync_ick@c10                          ti,omap3-interface-clock                R                                        gpt12_ick@c10                         ti,omap3-interface-clock                R                                        gpt1_ick@c10                          ti,omap3-interface-clock                R                                         per_96m_fck                       fixed-factor-clock              -        a           l                     per_48m_fck                       fixed-factor-clock              4        a           l               S      uart3_fck@1000                        ti,wait-gate-clock              S                                         gpt2_gate_fck@1000                        ti,composite-gate-clock             "                                   T      gpt2_mux_fck@1040                         ti,composite-mux-clock              D   "           @            U      gpt2_fck                          ti,composite-clock              T   U                  gpt3_gate_fck@1000                        ti,composite-gate-clock             "                                   V      gpt3_mux_fck@1040                         ti,composite-mux-clock              D   "                      @            W      gpt3_fck                          ti,composite-clock              V   W      gpt4_gate_fck@1000                        ti,composite-gate-clock             "                                   X      gpt4_mux_fck@1040                         ti,composite-mux-clock              D   "                      @            Y      gpt4_fck                          ti,composite-clock              X   Y      gpt5_gate_fck@1000                        ti,composite-gate-clock             "                                   Z      gpt5_mux_fck@1040                         ti,composite-mux-clock              D   "                      @            [      gpt5_fck                          ti,composite-clock              Z   [      gpt6_gate_fck@1000                        ti,composite-gate-clock             "                                   \      gpt6_mux_fck@1040                         ti,composite-mux-clock              D   "                      @            ]      gpt6_fck                          ti,composite-clock              \   ]      gpt7_gate_fck@1000                        ti,composite-gate-clock             "                                   ^      gpt7_mux_fck@1040                         ti,composite-mux-clock              D   "                      @            _      gpt7_fck                          ti,composite-clock              ^   _      gpt8_gate_fck@1000                        ti,composite-gate-clock             "           	                        `      gpt8_mux_fck@1040                         ti,composite-mux-clock              D   "                      @            a      gpt8_fck                          ti,composite-clock              `   a      gpt9_gate_fck@1000                        ti,composite-gate-clock             "           
                        b      gpt9_mux_fck@1040                         ti,composite-mux-clock              D   "                      @            c      gpt9_fck                          ti,composite-clock              b   c      per_32k_alwon_fck                         fixed-factor-clock              D        a           l               d      gpio6_dbck@1000                       ti,gate-clock               d                                         gpio5_dbck@1000                       ti,gate-clock               d                                         gpio4_dbck@1000                       ti,gate-clock               d                                         gpio3_dbck@1000                       ti,gate-clock               d                                         gpio2_dbck@1000                       ti,gate-clock               d                                         wdt3_fck@1000                         ti,wait-gate-clock              d                                         per_l4_ick                        fixed-factor-clock              C        a           l               e      gpio6_ick@1010                        ti,omap3-interface-clock                e                                        gpio5_ick@1010                        ti,omap3-interface-clock                e                                        gpio4_ick@1010                        ti,omap3-interface-clock                e                                        gpio3_ick@1010                        ti,omap3-interface-clock                e                                        gpio2_ick@1010                        ti,omap3-interface-clock                e                                        wdt3_ick@1010                         ti,omap3-interface-clock                e                                        uart3_ick@1010                        ti,omap3-interface-clock                e                                        uart4_ick@1010                        ti,omap3-interface-clock                e                                        gpt9_ick@1010                         ti,omap3-interface-clock                e                      
                  gpt8_ick@1010                         ti,omap3-interface-clock                e                      	                  gpt7_ick@1010                         ti,omap3-interface-clock                e                                        gpt6_ick@1010                         ti,omap3-interface-clock                e                                        gpt5_ick@1010                         ti,omap3-interface-clock                e                                        gpt4_ick@1010                         ti,omap3-interface-clock                e                                        gpt3_ick@1010                         ti,omap3-interface-clock                e                                        gpt2_ick@1010                         ti,omap3-interface-clock                e                                        mcbsp2_ick@1010                       ti,omap3-interface-clock                e                                         mcbsp3_ick@1010                       ti,omap3-interface-clock                e                                        mcbsp4_ick@1010                       ti,omap3-interface-clock                e                                        mcbsp2_gate_fck@1000                          ti,composite-gate-clock                                                       mcbsp3_gate_fck@1000                          ti,composite-gate-clock                                                      mcbsp4_gate_fck@1000                          ti,composite-gate-clock                                                      emu_src_mux_ck@1140                       ti,mux-clock                "   f   g   h           @            i      emu_src_ck                        ti,clkdm-gate-clock             i            j      pclk_fck@1140                         ti,divider-clock                j                   ?              @         J      pclkx2_fck@1140                       ti,divider-clock                j                   ?              @         J      atclk_fck@1140                        ti,divider-clock                j                   ?              @         J      traceclk_src_fck@1140                         ti,mux-clock                "   f   g   h                      @            k      traceclk_fck@1140                         ti,divider-clock                k                   ?              @         J      secure_32k_fck                        fixed-clock         /               l      gpt12_fck                         fixed-factor-clock              l        a           l                     wdt1_fck                          fixed-factor-clock              l        a           l         security_l4_ick2                          fixed-factor-clock              C        a           l               m      aes1_ick@a14                          ti,omap3-interface-clock                m                      
                  rng_ick@a14                       ti,omap3-interface-clock                m           
                             sha11_ick@a14                         ti,omap3-interface-clock                m           
                 des1_ick@a14                          ti,omap3-interface-clock                m           
                  cam_mclk@f00                          ti,gate-clock               n                                       cam_ick@f10                   !    ti,omap3-no-wait-interface-clock                C                                         csi2_96m_fck@f00                          ti,gate-clock                                                        security_l3_ick                       fixed-factor-clock              B        a           l               o      pka_ick@a14                       ti,omap3-interface-clock                o           
                 icr_ick@a10                       ti,omap3-interface-clock                N           
                 des2_ick@a10                          ti,omap3-interface-clock                N           
                 mspro_ick@a10                         ti,omap3-interface-clock                N           
                 mailboxes_ick@a10                         ti,omap3-interface-clock                N           
                 ssi_l4_ick                        fixed-factor-clock              C        a           l               v      sr1_fck@c00                       ti,wait-gate-clock              "                                         sr2_fck@c00                       ti,wait-gate-clock              "                                         sr_l4_ick                         fixed-factor-clock              C        a           l         dpll2_fck@40                          ti,divider-clock                *                   ?               @         J            p      dpll2_ck@4                        ti,omap3-dpll-clock             "   p               $   @   4                                       q      dpll2_m2_ck@44                        ti,divider-clock                q        ?               D         J            r      iva2_ck@0                         ti,wait-gate-clock              r                                           modem_fck@a00                         ti,omap3-interface-clock                "           
                              sad2d_ick@a10                         ti,omap3-interface-clock                B           
                             mad2d_ick@a18                         ti,omap3-interface-clock                B           
                             mspro_fck@a00                         ti,wait-gate-clock                         
                  ssi_ssr_gate_fck_3430es2@a00                           ti,composite-no-wait-gate-clock             #                       
             s      ssi_ssr_div_fck_3430es2@a40                       ti,composite-divider-clock              #                      
@      $                                            t      ssi_ssr_fck_3430es2                       ti,composite-clock              s   t            u      ssi_sst_fck_3430es2                       fixed-factor-clock              u        a           l                     hsotgusb_ick_3430es2@a10                      "    ti,omap3-hsotgusb-interface-clock               M           
                             ssi_ick_3430es2@a10                       ti,omap3-ssi-interface-clock                v           
                              usim_gate_fck@c00                         ti,composite-gate-clock             I           	                              sys_d2_ck                         fixed-factor-clock              "        a           l               x      omap_96m_d2_fck                       fixed-factor-clock              I        a           l               y      omap_96m_d4_fck                       fixed-factor-clock              I        a           l               z      omap_96m_d8_fck                       fixed-factor-clock              I        a           l               {      omap_96m_d10_fck                          fixed-factor-clock              I        a           l   
            |      dpll5_m2_d4_ck                        fixed-factor-clock              w        a           l               }      dpll5_m2_d8_ck                        fixed-factor-clock              w        a           l               ~      dpll5_m2_d16_ck                       fixed-factor-clock              w        a           l                     dpll5_m2_d20_ck                       fixed-factor-clock              w        a           l                     usim_mux_fck@c40                          ti,composite-mux-clock        (      "   x   y   z   {   |   }   ~                            @         J                  usim_fck                          ti,composite-clock                       usim_ick@c10                          ti,omap3-interface-clock                R                      	                  dpll5_ck@d04                          ti,omap3-dpll-clock             "   "             $  L  4                                    dpll5_m2_ck@d50                       ti,divider-clock                        ?              P         J            w      sgx_gate_fck@b00                          ti,composite-gate-clock             *                                         core_d3_ck                        fixed-factor-clock              *        a           l                     core_d4_ck                        fixed-factor-clock              *        a           l                     core_d6_ck                        fixed-factor-clock              *        a           l                     omap_192m_alwon_fck                       fixed-factor-clock              &        a           l                     core_d2_ck                        fixed-factor-clock              *        a           l                     sgx_mux_fck@b40                       ti,composite-mux-clock                        .                       @                  sgx_fck                       ti,composite-clock                                   sgx_ick@b10                       ti,wait-gate-clock              B                                         cpefuse_fck@a08                       ti,gate-clock               "           
                              ts_fck@a08                        ti,gate-clock               D           
                             usbtll_fck@a08                        ti,wait-gate-clock              w           
                             usbtll_ick@a18                        ti,omap3-interface-clock                N           
                             mmchs3_ick@a10                        ti,omap3-interface-clock                N           
                             mmchs3_fck@a00                        ti,wait-gate-clock                         
                              dss1_alwon_fck_3430es2@e00                        ti,dss-gate-clock                                                                  dss_ick_3430es2@e10                       ti,omap3-dss-interface-clock                C                                         usbhost_120m_fck@1400                         ti,gate-clock               w                                         usbhost_48m_fck@1400                          ti,dss-gate-clock               4                                          usbhost_ick@1410                          ti,omap3-dss-interface-clock                C                                         uart4_fck@1000                        ti,wait-gate-clock              S                                            clockdomains       core_l3_clkdm             ti,clockdomain                       dpll3_clkdm           ti,clockdomain                    dpll1_clkdm           ti,clockdomain                    per_clkdm             ti,clockdomain        l                                                                                          emu_clkdm             ti,clockdomain              j      dpll4_clkdm           ti,clockdomain                     wkup_clkdm            ti,clockdomain        $                                    dss_clkdm             ti,clockdomain                                core_l4_clkdm             ti,clockdomain                                                                                                                                cam_clkdm             ti,clockdomain                       iva2_clkdm            ti,clockdomain                    dpll2_clkdm           ti,clockdomain              q      d2d_clkdm             ti,clockdomain                          dpll5_clkdm           ti,clockdomain                    sgx_clkdm             ti,clockdomain                    usbhost_clkdm             ti,clockdomain                                target-module@48320000            ti,sysc-omap2 ti,sysc            H2     H2          	  rev sysc                               Q            fck ick                      +               H2        counter@0             ti,omap-counter32k                            interrupt-controller@48200000             ti,omap3-intc            *                    H                        target-module@48056000            ti,sysc-omap2 ti,sysc            H`    H`,   H`(           rev sysc syss             #        
                                                   M         ick                      +               H`       dma-controller@0              ti,omap3630-sdma ti,omap-sdma                                                           #            0   `                     gpio@48310000             ti,omap3-gpio            H1                          gpio1            =         O        _            *                            gpio@49050000             ti,omap3-gpio            I                          gpio2            O        _            *                 gpio@49052000             ti,omap3-gpio            I                          gpio3            O        _            *                            gpio@49054000             ti,omap3-gpio            I@                          gpio4            O        _            *                             gpio@49056000             ti,omap3-gpio            I`                !         gpio5            O        _            *                 gpio@49058000             ti,omap3-gpio            I                "         gpio6            O        _            *                 serial@4806a000           ti,omap3-uart            H             k      H               1      2        %tx rx            uart1           /l       serial@4806c000           ti,omap3-uart            H            k      I               3      4        %tx rx            uart2           /l       serial@49020000           ti,omap3-uart            I             k      J               5      6        %tx rx            uart3           /l       i2c@48070000              ti,omap3-i2c             H                 8                             %tx rx                        +             i2c1            /    tps@2d              -          ti,tps65910         default                                                                                                                                                 regulators                       +       regulator@0                      $vrtc          regulator@1                     $vio          w@         w@         9      regulator@2                     $vdd1            vdd_mpu          	'         `         M         9                  regulator@3                     $vdd2            vdd_dsp          	'         `         9      regulator@4                     $vdd3          	  vdd_core             LK@         LK@         9      regulator@5                     $vdig1            O         )2         9      regulator@6                     $vdig2            B@         w@         9      regulator@7                     $vpll             B@         &%         9      regulator@8                     $vdac                      2Z         9      regulator@9             	        $vaux1            w@         +|         9      regulator@10                
        $vaux2            w@         2Z         9      regulator@11                        $vaux33           w@         2Z         9      regulator@12                        $vmmc             w@         -         9                  regulator@13                        $vbb                i2c@48072000              ti,omap3-i2c             H                 9                             %tx rx                        +             i2c2            /    lp5523A@32            national,lp5523         _q1              2        e            p             chan0           |                    chan1           |                    chan2           |                    chan3           |                    chan4           |                    chan5           |                    chan6           |                    chan7           |                    chan8           |                       lp5523B@33            national,lp5523         _q3              3        e       chan0           |                    chan1           |                    chan2           |                    chan3           |                    chan4           |                    chan5           |                    chan6           |                    chan7           |                    chan8           |                       lp5523C@34            national,lp5523         _q4              4        e       chan0           |                    chan1           |                    chan2           |                    chan3           |                    chan4           |                    chan5           |                    chan6           |                    chan7           |                    chan8           |                       lp552D@35             national,lp5523         _q2              5        e       chan0           |                    chan1           |                    chan2           |                    chan3           |                    chan4           |                    chan5           |                    chan6           |                    chan7           |                    chan8           |                          i2c@48060000              ti,omap3-i2c             H                 =                             %tx rx                        +             i2c3          mailbox@48094000              ti,omap3-mailbox             mailbox          H	@                                                    dsp                                                 spi@48098000              ti,omap2-mcspi           H	                A                     +             mcspi1                   @         #      $      %      &      '      (      )      *         %tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3       spi@4809a000              ti,omap2-mcspi           H	                B                     +             mcspi2                             +      ,      -      .        %tx0 rx0 tx1 rx1       spi@480b8000              ti,omap2-mcspi           H                [                     +             mcspi3                                                       %tx0 rx0 tx1 rx1       spi@480ba000              ti,omap2-mcspi           H                0                     +             mcspi4                            F      G        %tx0 rx0       1w@480b2000           ti,omap3-1w          H                 :         hdq1w         mmc@4809c000              ti,omap3-hsmmc           H	                S         mmc1                            =      >        %tx rx                      okay                       default                             mmc@480b4000              ti,omap3-hsmmc           H@                V         mmc2                   /      0        %tx rx           okay                       default                             mmc@480ad000              ti,omap3-hsmmc           H
                ^         mmc3                   M      N        %tx rx           okay                       default                              %        0                      ;         mmu@480bd400            H              ti,omap2-iommu           H                         mmu_isp         U                     mmu@5d000000            H              ti,omap2-iommu           ]                           mmu_iva       	  disabled          wdt@48314000              ti,omap3-wdt             H1@          
   wd_timer2         mcbsp@48074000            ti,omap3-mcbsp           H@            mpu                ;   <        ecommon tx rx            u            mcbsp1                                %tx rx                        fck       	  disabled          target-module@480a0000            ti,sysc-omap2 ti,sysc            H
 <   H
 @   H
 D           rev sysc syss                                                             ick                      +               H
         rng@0             ti,omap2-rng                                 4         mcbsp@49022000            ti,omap3-mcbsp           I     I            mpu sidetone                   >   ?           ecommon tx rx sidetone           u            mcbsp2 mcbsp2_sidetone                 !      "        %tx rx                           fck ick       	  disabled          mcbsp@49024000            ti,omap3-mcbsp           I@    I            mpu sidetone                   Y   Z           ecommon tx rx sidetone           u            mcbsp3 mcbsp3_sidetone                               %tx rx                           fck ick       	  disabled          mcbsp@49026000            ti,omap3-mcbsp           I`            mpu                6   7        ecommon tx rx            u            mcbsp4                               %tx rx                        fck                   	  disabled          mcbsp@48096000            ti,omap3-mcbsp           H	`            mpu                Q   R        ecommon tx rx            u            mcbsp5                               %tx rx                        fck       	  disabled          sham@480c3000             ti,omap3-sham            sham             H0    d            1               E        %rx        target-module@48318000            ti,sysc-omap2-timer ti,sysc          H1    H1   H1           rev sysc syss             '                                                     fck ick                      +               H1                         timer@0           ti,omap3430-timer                                        fck             %                               D         target-module@49032000            ti,sysc-omap2-timer ti,sysc          I     I    I            rev sysc syss             '                                                     fck ick                      +               I        timer@0           ti,omap3430-timer                               &         timer@49034000            ti,omap3430-timer            I@                '         timer3        timer@49036000            ti,omap3430-timer            I`                (         timer4        timer@49038000            ti,omap3430-timer            I                )         timer5                 timer@4903a000            ti,omap3430-timer            I                *         timer6                 timer@4903c000            ti,omap3430-timer            I                +         timer7                 timer@4903e000            ti,omap3430-timer            I                ,         timer8                          timer@49040000            ti,omap3430-timer            I                 -         timer9                 timer@48086000            ti,omap3430-timer            H`                .         timer10                timer@48088000            ti,omap3430-timer            H                /         timer11                target-module@48304000            ti,sysc-omap2-timer ti,sysc          H0@    H0@   H0@           rev sysc syss             '                                                     fck ick                      +               H0@       timer@0           ti,omap3430-timer                               _                           usbhstll@48062000             ti,usbhs-tll             H                 N         usb_tll_hs        usbhshost@48064000            ti,usbhs-host            H@             usb_host_hs                      +               ohci@48064400             ti,ohci-omap3            HD                L               ehci@48064800             ti,ehci-omap             HH                M         gpmc@6e000000             ti,omap3430-gpmc             gpmc             n                                        %rxtx            ,           8                        +            *                    O        _         usb_otg_hs@480ab000           ti,omap3-musb            H
                \   ]        emc dma           usb_otg_hs          J           U           ]         dss@48050000              ti,omap3-dss             H           	  disabled          	   dss_core                         fck                      +               dispc@48050400            ti,omap3-dispc           H                      
   dss_dispc                        fck       encoder@4804fc00              ti,omap3-dsi             H    H    @H             proto phy pll                     	  disabled          	   dss_dsi1                            fck sys_clk                      +          encoder@48050800              ti,omap3-rfbi            H          	  disabled          	   dss_rfbi                            fck ick       encoder@48050c00              ti,omap3-venc            H          	  disabled          	   dss_venc                            fck tv_dac_clk           ssi-controller@48058000           ti,omap3-ssi             ssi         okay             H    H            sys gdd             G        egdd_mpu                      +                        u                ssi_ssr_fck ssi_sst_fck ssi_ick    ssi-port@4805a000             ti,omap3-ssi-port            H    H            tx rx               C   D      ssi-port@4805b000             ti,omap3-ssi-port            H    H            tx rx               E   F         serial@49042000           ti,omap3-uart            I                 P               Q      R        %tx rx            uart4           /l       regulator-abb-mpu         
    ti,abb-v1           abb_mpu_iva                       +             H0r   H0h           base-address int-address            f               "                            `   s                     O                     7                                                          pinmux@480025a0            ti,omap3-padconf pinctrl-single          H %   \                     +            
                       *        ?           ]     pinmux_mmc3_pins          0  z   8     :     B     D     F     H                       isp@480bc000              ti,omap3-isp             H   H                                                                 ports                        +             bandgap@48002524             H %$             ti,omap36xx-bandgap                              target-module@480cb000            ti,sysc-omap3630-sr ti,sysc          smartreflex_core             H8           sysc                                                      fck                      +               H       smartreflex@0             ti,omap3-smartreflex-core                                        target-module@480c9000            ti,sysc-omap3630-sr ti,sysc          smartreflex_mpu_iva          H8           sysc                                                      fck                      +               H       smartreflex@480c9000              ti,omap3-smartreflex-mpu-iva                                         target-module@50000000            ti,sysc-omap4 ti,sysc            P     P          	  rev sysc            
                                                    fck ick                      +               P            	  disabled             opp-table             operating-points-v2-ti-cpu                            opp50-300000000                       s s s s s s                          opp100-600000000                #F          O O O O O O                 opp130-800000000                /          7 7 7 7 7 7                 opp1g-1000000000                ;                                            opp_supply            ti,omap-opp-supply                 thermal-zones      cpu_thermal         -           C          Q      N         ^         trips      cpu_alert           n 8        z           passive                  cpu_crit            n _        z        	   critical             cooling-maps       map0                                       memory@80000000          {memory              `        fixedregulator0           regulator-fixed         vcc5v            LK@         LK@         M         9                  fixedregulator1           regulator-fixed         vcc3v3           2Z         2Z         M         9                  fixedregulator2           regulator-fixed         vcc1v8           w@         w@         M         9                  sdio-pwrseq           mmc-pwrseq-simple                              (                  gpio-keys         
    gpio-keys           default              mute-button         _mute               q                               help-button         _help                                                 rotary-encoder            rotary-encoder                                                          	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 device_type reg clocks clock-names clock-latency operating-points-v2 vbb-supply #cooling-cells cpu0-supply phandle interrupts ti,hwmods ranges #pinctrl-cells #interrupt-cells interrupt-controller pinctrl-single,register-width pinctrl-single,function-mask pinctrl-single,pins syscon regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift reg-names ti,sysc-mask ti,sysc-sidle ti,syss-mask dmas dma-names clock-frequency ti,max-div ti,index-starts-at-one clock-mult clock-div ti,set-bit-to-disable ti,clock-mult ti,clock-div ti,set-rate-parent ti,index-power-of-two ti,low-power-stop ti,lock ti,low-power-bypass ti,dividers ti,sysc-midle #dma-cells dma-channels dma-requests ti,gpio-always-on gpio-controller #gpio-cells interrupts-extended pinctrl-names pinctrl-0 ti,en-ck32k-xtal ti,system-power-controller vcc1-supply vcc2-supply vcc3-supply vcc4-supply vcc5-supply vcc6-supply vcc7-supply vccio-supply regulator-compatible regulator-always-on regulator-boot-on label clock-mode enable-gpio led-cur max-cur #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,spi-num-cs ti,dual-volt pbias-supply status bus-width vmmc-supply non-removable disable-wp mmc-pwrseq vqmmc-supply #iommu-cells ti,#tlb-entries interrupt-names ti,buffer-size #sound-dai-cells ti,no-reset-on-init ti,no-idle ti,timer-alwon assigned-clocks assigned-clock-parents ti,timer-dsp ti,timer-pwm ti,timer-secure remote-wakeup-connected gpmc,num-cs gpmc,num-waitpins multipoint num-eps ram-bits ti,tranxdone-status-mask ti,settling-time ti,clock-cycles ti,abb_info iommus ti,phy-type #thermal-sensor-cells opp-hz opp-microvolt opp-supported-hw opp-suspend turbo-mode ti,absolute-max-voltage-uv polling-delay-passive polling-delay coefficients thermal-sensors temperature hysteresis trip cooling-device reset-gpios post-power-on-delay-ms linux,code wakeup-source linux,axis rotary-encoder,relative-axis 