 
   8  $   (                                           '    ti,omap3-evm-37xx ti,omap3630 ti,omap3                                   +            7TI OMAP37XX EVM (TMDSEVM3730)      chosen        aliases          =/ocp@68000000/i2c@48070000           B/ocp@68000000/i2c@48072000           G/ocp@68000000/i2c@48060000           L/ocp@68000000/mmc@4809c000           Q/ocp@68000000/mmc@480b4000           V/ocp@68000000/mmc@480ad000           [/ocp@68000000/serial@4806a000            c/ocp@68000000/serial@4806c000            k/ocp@68000000/serial@49020000            s/ocp@68000000/serial@49042000         	   {/display          cpus                         +       cpu@0             arm,cortex-a8            cpu                                   cpu                                                                               pmu@54000000              arm,cortex-a8-pmu            T                          debugss       soc           ti,omap-infra      mpu           ti,omap3-mpu            mpu       iva       
    ti,iva2.2           iva    dsp           ti,omap3-c64                ocp@68000000              ti,omap3-l3-smx simple-bus           h                  	   
                     +                    l3_main    l4@48000000           ti,omap3-l4-core simple-bus                      +               H         scm@2000              ti,omap3-scm simple-bus                                       +                          pinmux@30              ti,omap3-padconf pinctrl-single             0  8                     +                       "            3        H           f          default                              pinmux_twl4030_pins             A                  pinmux_dss_dpi_pins2                                                                                                                                                                           
      pinmux_mmc1_pins          P                                  "    $    &                    pinmux_mmc2_pins          P    (    *    ,    .    0    2    4     6     8     :                    pinmux_uart3_pins             n  A   p                      pinmux_ehci_port_select_pins                                    pinmux_hsusb2_pins        0                                            pinmux_wl12xx_gpio            P    N                   pinmux_smsc911x_pins                                    scm_conf@270              syscon simple-bus              p  0                     +                 p  0               pbias_regulator@2b0           ti,pbias-omap3 ti,pbias-omap                                pbias_mmc_omap2430          pbias_mmc_omap2430           w@         -                     clocks                       +       mcbsp5_mux_fck@68                         ti,composite-mux-clock              	   
                       h                  mcbsp5_fck                        ti,composite-clock                                   mcbsp1_mux_fck@4                          ti,composite-mux-clock              	   
                                         mcbsp1_fck                        ti,composite-clock                                   mcbsp2_mux_fck@4                          ti,composite-mux-clock                 
                                         mcbsp2_fck                        ti,composite-clock                                   mcbsp3_mux_fck@68                         ti,composite-mux-clock                 
            h                  mcbsp3_fck                        ti,composite-clock                                   mcbsp4_mux_fck@68                         ti,composite-mux-clock                 
                       h                  mcbsp4_fck                        ti,composite-clock                                         clockdomains          pinmux@a00             ti,omap3-padconf pinctrl-single            
    \                     +                       "            3        H           f     pinmux_twl4030_vpins                                                          pinmux_dss_dpi_pins1          0     
                                                           target-module@480a6000            ti,sysc-omap2 ti,sysc            H
`D   H
`H   H
`L           rev sysc syss                      &                  4                        ick                      +               H
`        aes1@0            ti,omap3-aes                    P                     A      	      
        Ftx rx            target-module@480c5000            ti,sysc-omap2 ti,sysc            HPD   HPH   HPL           rev sysc syss                      &                  4                        ick                      +               HP        aes2@0            ti,omap3-aes                    P                     A      A      B        Ftx rx            prm@48306000              ti,omap3-prm             H0`   @                clocks                       +       virt_16_8m_ck                         fixed-clock         P Y                   osc_sys_ck@d40                        ti,mux-clock                                          @                  sys_ck@1270                       ti,divider-clock                                   `              p         k            $      sys_clkout1@d70                       ti,gate-clock                          p                 dpll3_x2_ck                       fixed-factor-clock                                           dpll3_m2x2_ck                         fixed-factor-clock              !                                  #      dpll4_x2_ck                       fixed-factor-clock              "                            corex2_fck                        fixed-factor-clock              #                                  %      wkup_l4_ick                       fixed-factor-clock              $                                  T      corex2_d3_fck                         fixed-factor-clock              %                                        corex2_d5_fck                         fixed-factor-clock              %                                           clockdomains             cm@48004000           ti,omap3-cm          H @   @    clocks                       +       dummy_apb_pclk                        fixed-clock         P          omap_32k_fck                          fixed-clock         P               F      virt_12m_ck                       fixed-clock         P                    virt_13m_ck                       fixed-clock         P ]@                  virt_19200000_ck                          fixed-clock         P$                   virt_26000000_ck                          fixed-clock         P                  virt_38_4m_ck                         fixed-clock         PI                   dpll4_ck@d00                          ti,omap3-dpll-per-j-type-clock              $   $                 D  0            "      dpll4_m2_ck@d48                       ti,divider-clock                "        `   ?           H         k            &      dpll4_m2x2_mul_ck                         fixed-factor-clock              &                                  '      dpll4_m2x2_ck@d00                         ti,hsdiv-gate-clock             '                                            (      omap_96m_alwon_fck                        fixed-factor-clock              (                                  /      dpll3_ck@d00                          ti,omap3-dpll-core-clock                $   $                 @  0                   dpll3_m3_ck@1140                          ti,divider-clock                                    `              @         k            )      dpll3_m3x2_mul_ck                         fixed-factor-clock              )                                  *      dpll3_m3x2_ck@d00                         ti,hsdiv-gate-clock             *                                            +      emu_core_alwon_ck                         fixed-factor-clock              +                                  h      sys_altclk                        fixed-clock         P                4      mcbsp_clks                        fixed-clock         P                
      dpll3_m2_ck@d40                       ti,divider-clock                                    `              @         k            !      core_ck                       fixed-factor-clock              !                                  ,      dpll1_fck@940                         ti,divider-clock                ,                   `              	@         k            -      dpll1_ck@904                          ti,omap3-dpll-clock             $   -           	  	$  	@  	4                  dpll1_x2_ck                       fixed-factor-clock                                                .      dpll1_x2m2_ck@944                         ti,divider-clock                .        `              	D         k            B      cm_96m_fck                        fixed-factor-clock              /                                  0      omap_96m_fck@d40                          ti,mux-clock                0   $                      @            K      dpll4_m3_ck@e40                       ti,divider-clock                "                   `               @         k            1      dpll4_m3x2_mul_ck                         fixed-factor-clock              1                                  2      dpll4_m3x2_ck@d00                         ti,hsdiv-gate-clock             2                                            3      omap_54m_fck@d40                          ti,mux-clock                3   4                      @            >      cm_96m_d2_fck                         fixed-factor-clock              0                                  5      omap_48m_fck@d40                          ti,mux-clock                5   4                      @            6      omap_12m_fck                          fixed-factor-clock              6                                  M      dpll4_m4_ck@e40                       ti,divider-clock                "        `              @         k            7      dpll4_m4x2_mul_ck                         ti,fixed-factor-clock               7                                           8      dpll4_m4x2_ck@d00                         ti,gate-clock               8                                                           dpll4_m5_ck@f40                       ti,divider-clock                "        `   ?           @         k            9      dpll4_m5x2_mul_ck                         ti,fixed-factor-clock               9                                           :      dpll4_m5x2_ck@d00                         ti,hsdiv-gate-clock             :                                                     p      dpll4_m6_ck@1140                          ti,divider-clock                "                   `   ?           @         k            ;      dpll4_m6x2_mul_ck                         fixed-factor-clock              ;                                  <      dpll4_m6x2_ck@d00                         ti,hsdiv-gate-clock             <                                            =      emu_per_alwon_ck                          fixed-factor-clock              =                                  i      clkout2_src_gate_ck@d70                        ti,composite-no-wait-gate-clock             ,                      p            ?      clkout2_src_mux_ck@d70                        ti,composite-mux-clock              ,   $   0   >           p            @      clkout2_src_ck                        ti,composite-clock              ?   @            A      sys_clkout2@d70                       ti,divider-clock                A                   `   @           p               mpu_ck                        fixed-factor-clock              B                                  C      arm_fck@924                       ti,divider-clock                C           	$        `         emu_mpu_alwon_ck                          fixed-factor-clock              C                                  j      l3_ick@a40                        ti,divider-clock                ,        `              
@         k            D      l4_ick@a40                        ti,divider-clock                D                   `              
@         k            E      rm_ick@c40                        ti,divider-clock                E                   `              @         k      gpt10_gate_fck@a00                        ti,composite-gate-clock             $                      
             G      gpt10_mux_fck@a40                         ti,composite-mux-clock              F   $                      
@            H      gpt10_fck                         ti,composite-clock              G   H      gpt11_gate_fck@a00                        ti,composite-gate-clock             $                      
             I      gpt11_mux_fck@a40                         ti,composite-mux-clock              F   $                      
@            J      gpt11_fck                         ti,composite-clock              I   J      core_96m_fck                          fixed-factor-clock              K                                  	      mmchs2_fck@a00                        ti,wait-gate-clock              	           
                              mmchs1_fck@a00                        ti,wait-gate-clock              	           
                              i2c3_fck@a00                          ti,wait-gate-clock              	           
                              i2c2_fck@a00                          ti,wait-gate-clock              	           
                              i2c1_fck@a00                          ti,wait-gate-clock              	           
                              mcbsp5_gate_fck@a00                       ti,composite-gate-clock             
           
           
                   mcbsp1_gate_fck@a00                       ti,composite-gate-clock             
           	           
                   core_48m_fck                          fixed-factor-clock              6                                  L      mcspi4_fck@a00                        ti,wait-gate-clock              L           
                              mcspi3_fck@a00                        ti,wait-gate-clock              L           
                              mcspi2_fck@a00                        ti,wait-gate-clock              L           
                              mcspi1_fck@a00                        ti,wait-gate-clock              L           
                              uart2_fck@a00                         ti,wait-gate-clock              L           
                              uart1_fck@a00                         ti,wait-gate-clock              L           
                              core_12m_fck                          fixed-factor-clock              M                                  N      hdq_fck@a00                       ti,wait-gate-clock              N           
                              core_l3_ick                       fixed-factor-clock              D                                  O      sdrc_ick@a10                          ti,wait-gate-clock              O           
                             gpmc_fck                          fixed-factor-clock              O                            core_l4_ick                       fixed-factor-clock              E                                  P      mmchs2_ick@a10                        ti,omap3-interface-clock                P           
                             mmchs1_ick@a10                        ti,omap3-interface-clock                P           
                             hdq_ick@a10                       ti,omap3-interface-clock                P           
                             mcspi4_ick@a10                        ti,omap3-interface-clock                P           
                             mcspi3_ick@a10                        ti,omap3-interface-clock                P           
                             mcspi2_ick@a10                        ti,omap3-interface-clock                P           
                             mcspi1_ick@a10                        ti,omap3-interface-clock                P           
                             i2c3_ick@a10                          ti,omap3-interface-clock                P           
                             i2c2_ick@a10                          ti,omap3-interface-clock                P           
                             i2c1_ick@a10                          ti,omap3-interface-clock                P           
                             uart2_ick@a10                         ti,omap3-interface-clock                P           
                             uart1_ick@a10                         ti,omap3-interface-clock                P           
                             gpt11_ick@a10                         ti,omap3-interface-clock                P           
                             gpt10_ick@a10                         ti,omap3-interface-clock                P           
                             mcbsp5_ick@a10                        ti,omap3-interface-clock                P           
           
                  mcbsp1_ick@a10                        ti,omap3-interface-clock                P           
           	                  omapctrl_ick@a10                          ti,omap3-interface-clock                P           
                             dss_tv_fck@e00                        ti,gate-clock               >                                         dss_96m_fck@e00                       ti,gate-clock               K                                         dss2_alwon_fck@e00                        ti,gate-clock               $                                         dummy_ck                          fixed-clock         P          gpt1_gate_fck@c00                         ti,composite-gate-clock             $                                    Q      gpt1_mux_fck@c40                          ti,composite-mux-clock              F   $           @            R      gpt1_fck                          ti,composite-clock              Q   R                  aes2_ick@a10                          ti,omap3-interface-clock                P                      
                  wkup_32k_fck                          fixed-factor-clock              F                                  S      gpio1_dbck@c00                        ti,gate-clock               S                                         sha12_ick@a10                         ti,omap3-interface-clock                P           
                             wdt2_fck@c00                          ti,wait-gate-clock              S                                         wdt2_ick@c10                          ti,omap3-interface-clock                T                                        wdt1_ick@c10                          ti,omap3-interface-clock                T                                        gpio1_ick@c10                         ti,omap3-interface-clock                T                                        omap_32ksync_ick@c10                          ti,omap3-interface-clock                T                                        gpt12_ick@c10                         ti,omap3-interface-clock                T                                        gpt1_ick@c10                          ti,omap3-interface-clock                T                                         per_96m_fck                       fixed-factor-clock              /                                        per_48m_fck                       fixed-factor-clock              6                                  U      uart3_fck@1000                        ti,wait-gate-clock              U                                         gpt2_gate_fck@1000                        ti,composite-gate-clock             $                                   V      gpt2_mux_fck@1040                         ti,composite-mux-clock              F   $           @            W      gpt2_fck                          ti,composite-clock              V   W                 gpt3_gate_fck@1000                        ti,composite-gate-clock             $                                   X      gpt3_mux_fck@1040                         ti,composite-mux-clock              F   $                      @            Y      gpt3_fck                          ti,composite-clock              X   Y      gpt4_gate_fck@1000                        ti,composite-gate-clock             $                                   Z      gpt4_mux_fck@1040                         ti,composite-mux-clock              F   $                      @            [      gpt4_fck                          ti,composite-clock              Z   [      gpt5_gate_fck@1000                        ti,composite-gate-clock             $                                   \      gpt5_mux_fck@1040                         ti,composite-mux-clock              F   $                      @            ]      gpt5_fck                          ti,composite-clock              \   ]      gpt6_gate_fck@1000                        ti,composite-gate-clock             $                                   ^      gpt6_mux_fck@1040                         ti,composite-mux-clock              F   $                      @            _      gpt6_fck                          ti,composite-clock              ^   _      gpt7_gate_fck@1000                        ti,composite-gate-clock             $                                   `      gpt7_mux_fck@1040                         ti,composite-mux-clock              F   $                      @            a      gpt7_fck                          ti,composite-clock              `   a      gpt8_gate_fck@1000                        ti,composite-gate-clock             $           	                        b      gpt8_mux_fck@1040                         ti,composite-mux-clock              F   $                      @            c      gpt8_fck                          ti,composite-clock              b   c      gpt9_gate_fck@1000                        ti,composite-gate-clock             $           
                        d      gpt9_mux_fck@1040                         ti,composite-mux-clock              F   $                      @            e      gpt9_fck                          ti,composite-clock              d   e      per_32k_alwon_fck                         fixed-factor-clock              F                                  f      gpio6_dbck@1000                       ti,gate-clock               f                                         gpio5_dbck@1000                       ti,gate-clock               f                                         gpio4_dbck@1000                       ti,gate-clock               f                                         gpio3_dbck@1000                       ti,gate-clock               f                                         gpio2_dbck@1000                       ti,gate-clock               f                                         wdt3_fck@1000                         ti,wait-gate-clock              f                                         per_l4_ick                        fixed-factor-clock              E                                  g      gpio6_ick@1010                        ti,omap3-interface-clock                g                                        gpio5_ick@1010                        ti,omap3-interface-clock                g                                        gpio4_ick@1010                        ti,omap3-interface-clock                g                                        gpio3_ick@1010                        ti,omap3-interface-clock                g                                        gpio2_ick@1010                        ti,omap3-interface-clock                g                                        wdt3_ick@1010                         ti,omap3-interface-clock                g                                        uart3_ick@1010                        ti,omap3-interface-clock                g                                        uart4_ick@1010                        ti,omap3-interface-clock                g                                        gpt9_ick@1010                         ti,omap3-interface-clock                g                      
                  gpt8_ick@1010                         ti,omap3-interface-clock                g                      	                  gpt7_ick@1010                         ti,omap3-interface-clock                g                                        gpt6_ick@1010                         ti,omap3-interface-clock                g                                        gpt5_ick@1010                         ti,omap3-interface-clock                g                                        gpt4_ick@1010                         ti,omap3-interface-clock                g                                        gpt3_ick@1010                         ti,omap3-interface-clock                g                                        gpt2_ick@1010                         ti,omap3-interface-clock                g                                        mcbsp2_ick@1010                       ti,omap3-interface-clock                g                                         mcbsp3_ick@1010                       ti,omap3-interface-clock                g                                        mcbsp4_ick@1010                       ti,omap3-interface-clock                g                                        mcbsp2_gate_fck@1000                          ti,composite-gate-clock             
                                          mcbsp3_gate_fck@1000                          ti,composite-gate-clock             
                                         mcbsp4_gate_fck@1000                          ti,composite-gate-clock             
                                         emu_src_mux_ck@1140                       ti,mux-clock                $   h   i   j           @            k      emu_src_ck                        ti,clkdm-gate-clock             k            l      pclk_fck@1140                         ti,divider-clock                l                   `              @         k      pclkx2_fck@1140                       ti,divider-clock                l                   `              @         k      atclk_fck@1140                        ti,divider-clock                l                   `              @         k      traceclk_src_fck@1140                         ti,mux-clock                $   h   i   j                      @            m      traceclk_fck@1140                         ti,divider-clock                m                   `              @         k      secure_32k_fck                        fixed-clock         P               n      gpt12_fck                         fixed-factor-clock              n                                       wdt1_fck                          fixed-factor-clock              n                            security_l4_ick2                          fixed-factor-clock              E                                  o      aes1_ick@a14                          ti,omap3-interface-clock                o                      
                  rng_ick@a14                       ti,omap3-interface-clock                o           
                             sha11_ick@a14                         ti,omap3-interface-clock                o           
                 des1_ick@a14                          ti,omap3-interface-clock                o           
                  cam_mclk@f00                          ti,gate-clock               p                                       cam_ick@f10                   !    ti,omap3-no-wait-interface-clock                E                                         csi2_96m_fck@f00                          ti,gate-clock               	                                         security_l3_ick                       fixed-factor-clock              D                                  q      pka_ick@a14                       ti,omap3-interface-clock                q           
                 icr_ick@a10                       ti,omap3-interface-clock                P           
                 des2_ick@a10                          ti,omap3-interface-clock                P           
                 mspro_ick@a10                         ti,omap3-interface-clock                P           
                 mailboxes_ick@a10                         ti,omap3-interface-clock                P           
                 ssi_l4_ick                        fixed-factor-clock              E                                  x      sr1_fck@c00                       ti,wait-gate-clock              $                                        sr2_fck@c00                       ti,wait-gate-clock              $                                        sr_l4_ick                         fixed-factor-clock              E                            dpll2_fck@40                          ti,divider-clock                ,                   `               @         k            r      dpll2_ck@4                        ti,omap3-dpll-clock             $   r               $   @   4                                       s      dpll2_m2_ck@44                        ti,divider-clock                s        `               D         k            t      iva2_ck@0                         ti,wait-gate-clock              t                                           modem_fck@a00                         ti,omap3-interface-clock                $           
                              sad2d_ick@a10                         ti,omap3-interface-clock                D           
                             mad2d_ick@a18                         ti,omap3-interface-clock                D           
                             mspro_fck@a00                         ti,wait-gate-clock              	           
                  ssi_ssr_gate_fck_3430es2@a00                           ti,composite-no-wait-gate-clock             %                       
             u      ssi_ssr_div_fck_3430es2@a40                       ti,composite-divider-clock              %                      
@      $                                            v      ssi_ssr_fck_3430es2                       ti,composite-clock              u   v            w      ssi_sst_fck_3430es2                       fixed-factor-clock              w                                       hsotgusb_ick_3430es2@a10                      "    ti,omap3-hsotgusb-interface-clock               O           
                             ssi_ick_3430es2@a10                       ti,omap3-ssi-interface-clock                x           
                             usim_gate_fck@c00                         ti,composite-gate-clock             K           	                              sys_d2_ck                         fixed-factor-clock              $                                  z      omap_96m_d2_fck                       fixed-factor-clock              K                                  {      omap_96m_d4_fck                       fixed-factor-clock              K                                  |      omap_96m_d8_fck                       fixed-factor-clock              K                                  }      omap_96m_d10_fck                          fixed-factor-clock              K                      
            ~      dpll5_m2_d4_ck                        fixed-factor-clock              y                                        dpll5_m2_d8_ck                        fixed-factor-clock              y                                        dpll5_m2_d16_ck                       fixed-factor-clock              y                                        dpll5_m2_d20_ck                       fixed-factor-clock              y                                        usim_mux_fck@c40                          ti,composite-mux-clock        (      $   z   {   |   }   ~                                  @         k                  usim_fck                          ti,composite-clock                       usim_ick@c10                          ti,omap3-interface-clock                T                      	                  dpll5_ck@d04                          ti,omap3-dpll-clock             $   $             $  L  4                                    dpll5_m2_ck@d50                       ti,divider-clock                        `              P         k            y      sgx_gate_fck@b00                          ti,composite-gate-clock             ,                                         core_d3_ck                        fixed-factor-clock              ,                                        core_d4_ck                        fixed-factor-clock              ,                                        core_d6_ck                        fixed-factor-clock              ,                                        omap_192m_alwon_fck                       fixed-factor-clock              (                                        core_d2_ck                        fixed-factor-clock              ,                                        sgx_mux_fck@b40                       ti,composite-mux-clock                        0                       @                  sgx_fck                       ti,composite-clock                                  sgx_ick@b10                       ti,wait-gate-clock              D                                         cpefuse_fck@a08                       ti,gate-clock               $           
                              ts_fck@a08                        ti,gate-clock               F           
                             usbtll_fck@a08                        ti,wait-gate-clock              y           
                             usbtll_ick@a18                        ti,omap3-interface-clock                P           
                             mmchs3_ick@a10                        ti,omap3-interface-clock                P           
                             mmchs3_fck@a00                        ti,wait-gate-clock              	           
                              dss1_alwon_fck_3430es2@e00                        ti,dss-gate-clock                                                                  dss_ick_3430es2@e10                       ti,omap3-dss-interface-clock                E                                         usbhost_120m_fck@1400                         ti,gate-clock               y                                         usbhost_48m_fck@1400                          ti,dss-gate-clock               6                                          usbhost_ick@1410                          ti,omap3-dss-interface-clock                E                                         uart4_fck@1000                        ti,wait-gate-clock              U                                            clockdomains       core_l3_clkdm             ti,clockdomain                       dpll3_clkdm           ti,clockdomain                     dpll1_clkdm           ti,clockdomain                    per_clkdm             ti,clockdomain        l                                                                                          emu_clkdm             ti,clockdomain              l      dpll4_clkdm           ti,clockdomain              "      wkup_clkdm            ti,clockdomain        $                                    dss_clkdm             ti,clockdomain                                core_l4_clkdm             ti,clockdomain                                                                                                                                cam_clkdm             ti,clockdomain                       iva2_clkdm            ti,clockdomain                    dpll2_clkdm           ti,clockdomain              s      d2d_clkdm             ti,clockdomain                          dpll5_clkdm           ti,clockdomain                    sgx_clkdm             ti,clockdomain                    usbhost_clkdm             ti,clockdomain                                target-module@48320000            ti,sysc-omap2 ti,sysc            H2     H2          	  rev sysc            &                   S            fck ick                      +               H2        counter@0             ti,omap-counter32k                            interrupt-controller@48200000             ti,omap3-intc            3        "            H                        target-module@48056000            ti,sysc-omap2 ti,sysc            H`    H`,   H`(           rev sysc syss             #        +                  &                  4               O         ick                      +               H`       dma-controller@0              ti,omap3630-sdma ti,omap-sdma                                                9           D            Q   `                     gpio@48310000             ti,omap3-gpio            H1                         gpio1            ^         p                    3        "                    gpio@49050000             ti,omap3-gpio            I                         gpio2            p                    3        "      en_usb2_port                                             enable usb2 port             gpio@49052000             ti,omap3-gpio            I                         gpio3            p                    3        "         gpio@49054000             ti,omap3-gpio            I@                         gpio4            p                    3        "         gpio@49056000             ti,omap3-gpio            I`                !        gpio5            p                    3        "                     gpio@49058000             ti,omap3-gpio            I                "        gpio6            p                    3        "                     serial@4806a000           ti,omap3-uart            H                   H     R        A      1      2        Ftx rx           uart1           Pl       serial@4806c000           ti,omap3-uart            H                  I     J        A      3      4        Ftx rx           uart2           Pl       serial@49020000           ti,omap3-uart            I                   J     n        A      5      6        Ftx rx           uart3           Pl         default                  i2c@48070000              ti,omap3-i2c             H                 8        A                    Ftx rx                        +            i2c1            P '@   twl@48              H                                  ti,twl4030           3        "           default                  rtc           ti,twl4030-rtc                    bci           ti,twl4030-bci              	                                    vac       watchdog              ti,twl4030-wdt        regulator-vaux1           ti,twl4030-vaux1          regulator-vaux2           ti,twl4030-vaux2            usb_1v8          w@         w@               regulator-vaux3           ti,twl4030-vaux3          regulator-vaux4           ti,twl4030-vaux4          regulator-vdd1            ti,twl4030-vdd1          	'                            regulator-vdac            ti,twl4030-vdac          w@         w@      regulator-vio             ti,twl4030-vio        regulator-vintana1            ti,twl4030-vintana1       regulator-vintana2            ti,twl4030-vintana2       regulator-vintdig             ti,twl4030-vintdig        regulator-vmmc1           ti,twl4030-vmmc1             :         0                  regulator-vmmc2           ti,twl4030-vmmc2             :         0                 regulator-vusb1v5             ti,twl4030-vusb1v5                    regulator-vusb1v8             ti,twl4030-vusb1v8                    regulator-vusb3v1             ti,twl4030-vusb3v1                    regulator-vpll1           ti,twl4030-vpll1          regulator-vpll2           ti,twl4030-vpll2             w@         w@                    	      regulator-vsim            ti,twl4030-vsim          w@         -                  gpio              ti,twl4030-gpio          p                    3        "                          en_on_board_gpio_61                                          en_hsusb2_clk            twl4030-usb           ti,twl4030-usb              
                                 +           9           B                     pwm           ti,twl4030-pwm          M         pwmled            ti,twl4030-pwmled           M         pwrbutton             ti,twl4030-pwrbutton                      keypad            ti,twl4030-keypad                       X           h         8  {           	  
 7    S         madc              ti,twl4030-madc                                          power         1    ti,twl4030-power-omap3-evm ti,twl4030-power-idle                         i2c@48072000              ti,omap3-i2c             H                 9        A                    Ftx rx                        +            i2c2            P       i2c@48060000              ti,omap3-i2c             H                 =        A                    Ftx rx                        +            i2c3            P    tvp5146@5c            ti,tvp5146m2                \         mailbox@48094000              ti,omap3-mailbox            mailbox          H	@                                                    dsp                                                 spi@48098000              ti,omap2-mcspi           H	                A                     +            mcspi1                   @  A      #      $      %      &      '      (      )      *         Ftx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3    tsc2046@0                          ti,tsc2046           B@                               $@          -            6          ? (          O            _         j                                    x                   spi@4809a000              ti,omap2-mcspi           H	                B                     +            mcspi2                      A      +      ,      -      .        Ftx0 rx0 tx1 rx1       spi@480b8000              ti,omap2-mcspi           H                [                     +            mcspi3                      A                                Ftx0 rx0 tx1 rx1       spi@480ba000              ti,omap2-mcspi           H                0                     +            mcspi4                     A      F      G        Ftx0 rx0       1w@480b2000           ti,omap3-1w          H                 :        hdq1w         mmc@4809c000              ti,omap3-hsmmc           H	                S        mmc1                     A      =      >        Ftx rx                            S                                              default                  mmc@480b4000              ti,omap3-hsmmc           H@                V        mmc2            A      /      0        Ftx rx                 V     .                                                             +            default               wlcore@2          
    ti,wl1271                                     N        irq wakeup          I          mmc@480ad000              ti,omap3-hsmmc           H
                ^        mmc3            A      M      N        Ftx rx         	  disabled          mmu@480bd400                          ti,omap2-iommu           H                        mmu_isp                             mmu@5d000000                          ti,omap2-iommu           ]                          mmu_iva       	  disabled          wdt@48314000              ti,omap3-wdt             H1@          
  wd_timer2         mcbsp@48074000            ti,omap3-mcbsp           H@            mpu                ;   <        common tx rx            +           mcbsp1          A                     Ftx rx                        fck       	  disabled          target-module@480a0000            ti,sysc-omap2 ti,sysc            H
 <   H
 @   H
 D           rev sysc syss                      &               4                        ick                      +               H
         rng@0             ti,omap2-rng                                 4         mcbsp@49022000            ti,omap3-mcbsp           I     I            mpu sidetone                   >   ?           common tx rx sidetone           +           mcbsp2 mcbsp2_sidetone          A      !      "        Ftx rx                           fck ick       	  disabled          mcbsp@49024000            ti,omap3-mcbsp           I@    I            mpu sidetone                   Y   Z           common tx rx sidetone           +           mcbsp3 mcbsp3_sidetone          A                    Ftx rx                           fck ick       	  disabled          mcbsp@49026000            ti,omap3-mcbsp           I`            mpu                6   7        common tx rx            +           mcbsp4          A                    Ftx rx                        fck         :          	  disabled          mcbsp@48096000            ti,omap3-mcbsp           H	`            mpu                Q   R        common tx rx            +           mcbsp5          A                    Ftx rx                        fck       	  disabled          sham@480c3000             ti,omap3-sham           sham             H0    d            1        A      E        Frx        target-module@48318000            ti,sysc-omap2-timer ti,sysc          H1    H1   H1           rev sysc syss             '        &                  4                           fck ick                      +               H1             K         _   timer@0           ti,omap3430-timer                                        fck             %         j        y              F         target-module@49032000            ti,sysc-omap2-timer ti,sysc          I     I    I            rev sysc syss             '        &                  4                          fck ick                      +               I        timer@0           ti,omap3430-timer                               &         timer@49034000            ti,omap3430-timer            I@                '        timer3        timer@49036000            ti,omap3430-timer            I`                (        timer4        timer@49038000            ti,omap3430-timer            I                )        timer5                 timer@4903a000            ti,omap3430-timer            I                *        timer6                 timer@4903c000            ti,omap3430-timer            I                +        timer7                 timer@4903e000            ti,omap3430-timer            I                ,        timer8                          timer@49040000            ti,omap3430-timer            I                 -        timer9                 timer@48086000            ti,omap3430-timer            H`                .        timer10                timer@48088000            ti,omap3430-timer            H                /        timer11                target-module@48304000            ti,sysc-omap2-timer ti,sysc          H0@    H0@   H0@           rev sysc syss             '        &                  4                          fck ick                      +               H0@       timer@0           ti,omap3430-timer                               _         j                  usbhstll@48062000             ti,usbhs-tll             H                 N        usb_tll_hs        usbhshost@48064000            ti,usbhs-host            H@            usb_host_hs                      +                  	  ehci-phy       ohci@48064400             ti,ohci-omap3            HD                L               ehci@48064800             ti,ehci-omap             HH                M                       gpmc@6e000000             ti,omap3430-gpmc            gpmc             n                         A              Frxtx                                               +            3        "            p                            0             ,                    ethernet@gpmc             smsc,lan9221 smsc,lan9115                                 -           G           a           o                                                (           -                      -                                         $   x        3           M   K        d   K        ~                                                                                	                                                      default                 nand@0,0              ti,omap2-nand                                                                  	hynix,h8kds0un0mer-4em          	'                      	6bch8            	F            a            o   ,           ,                      "           ,           (           6        $   @           R           R           (                                 +      partition@0       	  	WX-Loader                          partition@80000         	WU-Boot                       partition@1c0000            	WEnvironment           $           partition@280000            	WKernel            (   P        partition@780000            	WFilesystem            x                usb_otg_hs@480ab000           ti,omap3-musb            H
                \   ]        mc dma          usb_otg_hs          	]           	h           	p           	y            	                  	  	usb2-phy            =           	   2      dss@48050000              ti,omap3-dss             H             okay          	  dss_core                         fck                      +                    	  	        	           default           
     dispc@48050400            ti,omap3-dispc           H                      
  dss_dispc                        fck       encoder@4804fc00              ti,omap3-dsi             H    H    @H             proto phy pll                     	  disabled          	  dss_dsi1                            fck sys_clk                      +          encoder@48050800              ti,omap3-rfbi            H          	  disabled          	  dss_rfbi                            fck ick       encoder@48050c00              ti,omap3-venc            H          	  disabled          	  dss_venc                            fck tv_dac_clk        port       endpoint            	          	                          ssi-controller@48058000           ti,omap3-ssi            ssi         okay             H    H            sys gdd             G        gdd_mpu                      +                        w              ssi_ssr_fck ssi_sst_fck ssi_ick    ssi-port@4805a000             ti,omap3-ssi-port            H    H            tx rx               C   D      ssi-port@4805b000             ti,omap3-ssi-port            H    H            tx rx               E   F         serial@49042000           ti,omap3-uart            I                 P        A      Q      R        Ftx rx           uart4           Pl       regulator-abb-mpu         
    ti,abb-v1           abb_mpu_iva                       +             H0r   H0h           base-address int-address            	               $        	           
         `  
 s                     O                     7                                                          pinmux@480025a0            ti,omap3-padconf pinctrl-single          H %   \                     +                       "            3        H           f          default              pinmux_ehci_phy_pins               J      L                    pinmux_hsusb2_2_pins          0     P      R      T     V     X     Z                      isp@480bc000              ti,omap3-isp             H   H                        
#                       
*                 ports                        +             bandgap@48002524             H %$             ti,omap36xx-bandgap         
6                     target-module@480cb000            ti,sysc-omap3630-sr ti,sysc         smartreflex_core             H8           sysc                       &                              fck                      +               H       smartreflex@0             ti,omap3-smartreflex-core                                        target-module@480c9000            ti,sysc-omap3630-sr ti,sysc         smartreflex_mpu_iva          H8           sysc                       &                              fck                      +               H       smartreflex@480c9000              ti,omap3-smartreflex-mpu-iva                                         target-module@50000000            ti,sysc-omap4 ti,sysc            P     P          	  rev sysc            +                  &                                 fck ick                      +               P               opp-table             operating-points-v2-ti-cpu                            opp50-300000000         
L             
S s s s s s s        
a            
r      opp100-600000000            
L    #F         
S O O O O O O        
a         opp130-800000000            
L    /         
S 7 7 7 7 7 7        
a         opp1g-1000000000            
L    ;         
S              
a            
~         opp_supply            ti,omap-opp-supply          
       thermal-zones      cpu_thermal         
           
          
      N         
         trips      cpu_alert           
 8        
           passive                  cpu_crit            
 _        
        	   critical             cooling-maps       map0            
                           regulator-vddvario            regulator-fixed       	  vddvario                              regulator-vdd33a              regulator-fixed         vdd33a                            hsusb2_power_reg              regulator-fixed         hsusb2_vbus          2Z         2Z                          p         !                 hsusb2_phy            usb-nop-xceiv           4                          B            default                            leds          
    gpio-leds      ledb            	Womap3evm::ledb                           @default-on           wl12xx_vmmc           regulator-fixed         vwl1271          w@         w@                           p         !        V          default                             backlight             gpio-backlight           a                      regulator-lcd-3v3             regulator-fixed         lcd_3v3          2Z         2Z         p                                   display           sharp,ls037v7dw01           	Wlcd         l           y                             4                $                                 port       endpoint            	                         memory@80000000          memory                          	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 display0 device_type reg clocks clock-names clock-latency operating-points-v2 vbb-supply #cooling-cells cpu0-supply phandle interrupts ti,hwmods ranges #pinctrl-cells #interrupt-cells interrupt-controller pinctrl-single,register-width pinctrl-single,function-mask pinctrl-names pinctrl-0 pinctrl-single,pins syscon regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift reg-names ti,sysc-mask ti,sysc-sidle ti,syss-mask dmas dma-names clock-frequency ti,max-div ti,index-starts-at-one clock-mult clock-div ti,set-bit-to-disable ti,clock-mult ti,clock-div ti,set-rate-parent ti,index-power-of-two ti,low-power-stop ti,lock ti,low-power-bypass ti,dividers ti,sysc-midle #dma-cells dma-channels dma-requests ti,gpio-always-on gpio-controller #gpio-cells gpio-hog gpios output-low line-name interrupts-extended bci3v1-supply io-channels io-channel-names regulator-always-on ti,use-leds usb1v5-supply usb1v8-supply usb3v1-supply usb_mode #phy-cells #pwm-cells keypad,num-rows keypad,num-columns linux,keymap #io-channel-cells ti,use_poweroff #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,spi-num-cs spi-max-frequency vcc-supply ti,x-min ti,x-max ti,y-min ti,y-max ti,x-plate-ohms ti,pressure-max ti,swap-xy wakeup-source pendown-gpio ti,dual-volt pbias-supply vmmc-supply vqmmc-supply bus-width non-removable cap-power-off-card interrupt-names ref-clock-frequency status #iommu-cells ti,#tlb-entries ti,buffer-size #sound-dai-cells ti,no-reset-on-init ti,no-idle ti,timer-alwon assigned-clocks assigned-clock-parents ti,timer-dsp ti,timer-pwm ti,timer-secure port2-mode remote-wakeup-connected phys gpmc,num-cs gpmc,num-waitpins bank-width gpmc,device-width gpmc,cycle2cycle-samecsen gpmc,cycle2cycle-diffcsen gpmc,cs-on-ns gpmc,cs-rd-off-ns gpmc,cs-wr-off-ns gpmc,adv-on-ns gpmc,adv-rd-off-ns gpmc,adv-wr-off-ns gpmc,oe-on-ns gpmc,oe-off-ns gpmc,we-on-ns gpmc,we-off-ns gpmc,rd-cycle-ns gpmc,wr-cycle-ns gpmc,access-ns gpmc,page-burst-access-ns gpmc,bus-turnaround-ns gpmc,cycle2cycle-delay-ns gpmc,wait-monitoring-ns gpmc,clk-activation-ns gpmc,wr-data-mux-bus-ns gpmc,wr-access-ns vddvario-supply vdd33a-supply reg-io-width smsc,save-mac-address linux,mtd-name nand-bus-width ti,nand-ecc-opt gpmc,sync-clk-ps label multipoint num-eps ram-bits interface-type usb-phy phy-names power vdds_dsi-supply vdda_video-supply remote-endpoint data-lines ti,tranxdone-status-mask ti,settling-time ti,clock-cycles ti,abb_info iommus ti,phy-type #thermal-sensor-cells opp-hz opp-microvolt opp-supported-hw opp-suspend turbo-mode ti,absolute-max-voltage-uv polling-delay-passive polling-delay coefficients thermal-sensors temperature hysteresis trip cooling-device startup-delay-us enable-active-high reset-gpios linux,default-trigger vin-supply default-on power-supply envdd-supply enable-gpios mode-gpios 