    8     (            *  H                             "    ti,omap3-evm ti,omap3430 ti,omap3                                    +            7TI OMAP35XX EVM (TMDSEVM3530)      chosen        aliases          =/ocp@68000000/i2c@48070000           B/ocp@68000000/i2c@48072000           G/ocp@68000000/i2c@48060000           L/ocp@68000000/mmc@4809c000           Q/ocp@68000000/mmc@480b4000           V/ocp@68000000/mmc@480ad000           [/ocp@68000000/serial@4806a000            c/ocp@68000000/serial@4806c000            k/ocp@68000000/serial@49020000         	   s/display          cpus                         +       cpu@0             arm,cortex-a8            |cpu                                   cpu                                                                   pmu@54000000              arm,cortex-a8-pmu            T                           debugss       soc           ti,omap-infra      mpu           ti,omap3-mpu             mpu       iva       
    ti,iva2.2            iva    dsp           ti,omap3-c64                ocp@68000000              ti,omap3-l3-smx simple-bus           h                  	   
                     +                      l3_main    l4@48000000           ti,omap3-l4-core simple-bus                      +                H         scm@2000              ti,omap3-scm simple-bus                                       +                           pinmux@30              ti,omap3-padconf pinctrl-single             0  8                     +                                             5           S          pdefault         ~                     pinmux_twl4030_pins             A                  pinmux_dss_dpi_pins2                                                                                                                                                                                 pinmux_mmc1_pins          P                                  "    $    &                    pinmux_mmc2_pins          P    (    *    ,    .    0    2    4     6     8     :                    pinmux_uart3_pins             n  A   p                      pinmux_ehci_port_select_pins                                    pinmux_hsusb2_pins        0                                            pinmux_wl12xx_gpio            P    N                   pinmux_smsc911x_pins                                    scm_conf@270              syscon simple-bus              p  0                     +                  p  0               pbias_regulator@2b0           ti,pbias-omap3 ti,pbias-omap                                pbias_mmc_omap2430          pbias_mmc_omap2430           w@         -                     clocks                       +       mcbsp5_mux_fck@68                         ti,composite-mux-clock                 	                       h                  mcbsp5_fck                        ti,composite-clock              
                     mcbsp1_mux_fck@4                          ti,composite-mux-clock                 	                                         mcbsp1_fck                        ti,composite-clock                                   mcbsp2_mux_fck@4                          ti,composite-mux-clock                 	                                         mcbsp2_fck                        ti,composite-clock                                   mcbsp3_mux_fck@68                         ti,composite-mux-clock                 	            h                  mcbsp3_fck                        ti,composite-clock                                   mcbsp4_mux_fck@68                         ti,composite-mux-clock                 	                       h                  mcbsp4_fck                        ti,composite-clock                                         clockdomains          pinmux@a00             ti,omap3-padconf pinctrl-single            
    \                     +                                             5           S     pinmux_twl4030_vpins                                                          pinmux_dss_dpi_pins1          0     
                                            	               target-module@480a6000            ti,sysc-omap2 ti,sysc            H
`D   H
`H   H
`L           rev sysc syss                                        !                        ick                      +                H
`        aes1@0            ti,omap3-aes                    P                     .      	      
        3tx rx            target-module@480c5000            ti,sysc-omap2 ti,sysc            HPD   HPH   HPL           rev sysc syss                                        !                        ick                      +                HP        aes2@0            ti,omap3-aes                    P                     .      A      B        3tx rx            prm@48306000              ti,omap3-prm             H0`   @                clocks                       +       virt_16_8m_ck                         fixed-clock         = Y                   osc_sys_ck@d40                        ti,mux-clock                                          @                  sys_ck@1270                       ti,divider-clock                                   M              p         X            #      sys_clkout1@d70                       ti,gate-clock                          p                 dpll3_x2_ck                       fixed-factor-clock                      o           z         dpll3_m2x2_ck                         fixed-factor-clock                       o           z               "      dpll4_x2_ck                       fixed-factor-clock              !        o           z         corex2_fck                        fixed-factor-clock              "        o           z               $      wkup_l4_ick                       fixed-factor-clock              #        o           z               S      corex2_d3_fck                         fixed-factor-clock              $        o           z                     corex2_d5_fck                         fixed-factor-clock              $        o           z                        clockdomains             cm@48004000           ti,omap3-cm          H @   @    clocks                       +       dummy_apb_pclk                        fixed-clock         =          omap_32k_fck                          fixed-clock         =               E      virt_12m_ck                       fixed-clock         =                    virt_13m_ck                       fixed-clock         = ]@                  virt_19200000_ck                          fixed-clock         =$                   virt_26000000_ck                          fixed-clock         =                  virt_38_4m_ck                         fixed-clock         =I                   dpll4_ck@d00                          ti,omap3-dpll-per-clock             #   #                 D  0            !      dpll4_m2_ck@d48                       ti,divider-clock                !        M   ?           H         X            %      dpll4_m2x2_mul_ck                         fixed-factor-clock              %        o           z               &      dpll4_m2x2_ck@d00                         ti,gate-clock               &                                            '      omap_96m_alwon_fck                        fixed-factor-clock              '        o           z               .      dpll3_ck@d00                          ti,omap3-dpll-core-clock                #   #                 @  0                  dpll3_m3_ck@1140                          ti,divider-clock                                   M              @         X            (      dpll3_m3x2_mul_ck                         fixed-factor-clock              (        o           z               )      dpll3_m3x2_ck@d00                         ti,gate-clock               )                                            *      emu_core_alwon_ck                         fixed-factor-clock              *        o           z               g      sys_altclk                        fixed-clock         =                3      mcbsp_clks                        fixed-clock         =                	      dpll3_m2_ck@d40                       ti,divider-clock                                   M              @         X                   core_ck                       fixed-factor-clock                       o           z               +      dpll1_fck@940                         ti,divider-clock                +                   M              	@         X            ,      dpll1_ck@904                          ti,omap3-dpll-clock             #   ,           	  	$  	@  	4                  dpll1_x2_ck                       fixed-factor-clock                      o           z               -      dpll1_x2m2_ck@944                         ti,divider-clock                -        M              	D         X            A      cm_96m_fck                        fixed-factor-clock              .        o           z               /      omap_96m_fck@d40                          ti,mux-clock                /   #                      @            J      dpll4_m3_ck@e40                       ti,divider-clock                !                   M               @         X            0      dpll4_m3x2_mul_ck                         fixed-factor-clock              0        o           z               1      dpll4_m3x2_ck@d00                         ti,gate-clock               1                                            2      omap_54m_fck@d40                          ti,mux-clock                2   3                      @            =      cm_96m_d2_fck                         fixed-factor-clock              /        o           z               4      omap_48m_fck@d40                          ti,mux-clock                4   3                      @            5      omap_12m_fck                          fixed-factor-clock              5        o           z               L      dpll4_m4_ck@e40                       ti,divider-clock                !        M              @         X            6      dpll4_m4x2_mul_ck                         ti,fixed-factor-clock               6                                           7      dpll4_m4x2_ck@d00                         ti,gate-clock               7                                                           dpll4_m5_ck@f40                       ti,divider-clock                !        M   ?           @         X            8      dpll4_m5x2_mul_ck                         ti,fixed-factor-clock               8                                           9      dpll4_m5x2_ck@d00                         ti,gate-clock               9                                                     o      dpll4_m6_ck@1140                          ti,divider-clock                !                   M   ?           @         X            :      dpll4_m6x2_mul_ck                         fixed-factor-clock              :        o           z               ;      dpll4_m6x2_ck@d00                         ti,gate-clock               ;                                            <      emu_per_alwon_ck                          fixed-factor-clock              <        o           z               h      clkout2_src_gate_ck@d70                        ti,composite-no-wait-gate-clock             +                      p            >      clkout2_src_mux_ck@d70                        ti,composite-mux-clock              +   #   /   =           p            ?      clkout2_src_ck                        ti,composite-clock              >   ?            @      sys_clkout2@d70                       ti,divider-clock                @                   M   @           p               mpu_ck                        fixed-factor-clock              A        o           z               B      arm_fck@924                       ti,divider-clock                B           	$        M         emu_mpu_alwon_ck                          fixed-factor-clock              B        o           z               i      l3_ick@a40                        ti,divider-clock                +        M              
@         X            C      l4_ick@a40                        ti,divider-clock                C                   M              
@         X            D      rm_ick@c40                        ti,divider-clock                D                   M              @         X      gpt10_gate_fck@a00                        ti,composite-gate-clock             #                      
             F      gpt10_mux_fck@a40                         ti,composite-mux-clock              E   #                      
@            G      gpt10_fck                         ti,composite-clock              F   G      gpt11_gate_fck@a00                        ti,composite-gate-clock             #                      
             H      gpt11_mux_fck@a40                         ti,composite-mux-clock              E   #                      
@            I      gpt11_fck                         ti,composite-clock              H   I      core_96m_fck                          fixed-factor-clock              J        o           z                     mmchs2_fck@a00                        ti,wait-gate-clock                         
                              mmchs1_fck@a00                        ti,wait-gate-clock                         
                              i2c3_fck@a00                          ti,wait-gate-clock                         
                              i2c2_fck@a00                          ti,wait-gate-clock                         
                              i2c1_fck@a00                          ti,wait-gate-clock                         
                              mcbsp5_gate_fck@a00                       ti,composite-gate-clock             	           
           
             
      mcbsp1_gate_fck@a00                       ti,composite-gate-clock             	           	           
                   core_48m_fck                          fixed-factor-clock              5        o           z               K      mcspi4_fck@a00                        ti,wait-gate-clock              K           
                              mcspi3_fck@a00                        ti,wait-gate-clock              K           
                              mcspi2_fck@a00                        ti,wait-gate-clock              K           
                              mcspi1_fck@a00                        ti,wait-gate-clock              K           
                              uart2_fck@a00                         ti,wait-gate-clock              K           
                              uart1_fck@a00                         ti,wait-gate-clock              K           
                              core_12m_fck                          fixed-factor-clock              L        o           z               M      hdq_fck@a00                       ti,wait-gate-clock              M           
                              core_l3_ick                       fixed-factor-clock              C        o           z               N      sdrc_ick@a10                          ti,wait-gate-clock              N           
                             gpmc_fck                          fixed-factor-clock              N        o           z         core_l4_ick                       fixed-factor-clock              D        o           z               O      mmchs2_ick@a10                        ti,omap3-interface-clock                O           
                             mmchs1_ick@a10                        ti,omap3-interface-clock                O           
                             hdq_ick@a10                       ti,omap3-interface-clock                O           
                             mcspi4_ick@a10                        ti,omap3-interface-clock                O           
                             mcspi3_ick@a10                        ti,omap3-interface-clock                O           
                             mcspi2_ick@a10                        ti,omap3-interface-clock                O           
                             mcspi1_ick@a10                        ti,omap3-interface-clock                O           
                             i2c3_ick@a10                          ti,omap3-interface-clock                O           
                             i2c2_ick@a10                          ti,omap3-interface-clock                O           
                             i2c1_ick@a10                          ti,omap3-interface-clock                O           
                             uart2_ick@a10                         ti,omap3-interface-clock                O           
                             uart1_ick@a10                         ti,omap3-interface-clock                O           
                             gpt11_ick@a10                         ti,omap3-interface-clock                O           
                             gpt10_ick@a10                         ti,omap3-interface-clock                O           
                             mcbsp5_ick@a10                        ti,omap3-interface-clock                O           
           
                  mcbsp1_ick@a10                        ti,omap3-interface-clock                O           
           	                  omapctrl_ick@a10                          ti,omap3-interface-clock                O           
                             dss_tv_fck@e00                        ti,gate-clock               =                                         dss_96m_fck@e00                       ti,gate-clock               J                                         dss2_alwon_fck@e00                        ti,gate-clock               #                                         dummy_ck                          fixed-clock         =          gpt1_gate_fck@c00                         ti,composite-gate-clock             #                                    P      gpt1_mux_fck@c40                          ti,composite-mux-clock              E   #           @            Q      gpt1_fck                          ti,composite-clock              P   Q                  aes2_ick@a10                          ti,omap3-interface-clock                O                      
                  wkup_32k_fck                          fixed-factor-clock              E        o           z               R      gpio1_dbck@c00                        ti,gate-clock               R                                         sha12_ick@a10                         ti,omap3-interface-clock                O           
                             wdt2_fck@c00                          ti,wait-gate-clock              R                                         wdt2_ick@c10                          ti,omap3-interface-clock                S                                        wdt1_ick@c10                          ti,omap3-interface-clock                S                                        gpio1_ick@c10                         ti,omap3-interface-clock                S                                        omap_32ksync_ick@c10                          ti,omap3-interface-clock                S                                        gpt12_ick@c10                         ti,omap3-interface-clock                S                                        gpt1_ick@c10                          ti,omap3-interface-clock                S                                         per_96m_fck                       fixed-factor-clock              .        o           z                     per_48m_fck                       fixed-factor-clock              5        o           z               T      uart3_fck@1000                        ti,wait-gate-clock              T                                         gpt2_gate_fck@1000                        ti,composite-gate-clock             #                                   U      gpt2_mux_fck@1040                         ti,composite-mux-clock              E   #           @            V      gpt2_fck                          ti,composite-clock              U   V                  gpt3_gate_fck@1000                        ti,composite-gate-clock             #                                   W      gpt3_mux_fck@1040                         ti,composite-mux-clock              E   #                      @            X      gpt3_fck                          ti,composite-clock              W   X      gpt4_gate_fck@1000                        ti,composite-gate-clock             #                                   Y      gpt4_mux_fck@1040                         ti,composite-mux-clock              E   #                      @            Z      gpt4_fck                          ti,composite-clock              Y   Z      gpt5_gate_fck@1000                        ti,composite-gate-clock             #                                   [      gpt5_mux_fck@1040                         ti,composite-mux-clock              E   #                      @            \      gpt5_fck                          ti,composite-clock              [   \      gpt6_gate_fck@1000                        ti,composite-gate-clock             #                                   ]      gpt6_mux_fck@1040                         ti,composite-mux-clock              E   #                      @            ^      gpt6_fck                          ti,composite-clock              ]   ^      gpt7_gate_fck@1000                        ti,composite-gate-clock             #                                   _      gpt7_mux_fck@1040                         ti,composite-mux-clock              E   #                      @            `      gpt7_fck                          ti,composite-clock              _   `      gpt8_gate_fck@1000                        ti,composite-gate-clock             #           	                        a      gpt8_mux_fck@1040                         ti,composite-mux-clock              E   #                      @            b      gpt8_fck                          ti,composite-clock              a   b      gpt9_gate_fck@1000                        ti,composite-gate-clock             #           
                        c      gpt9_mux_fck@1040                         ti,composite-mux-clock              E   #                      @            d      gpt9_fck                          ti,composite-clock              c   d      per_32k_alwon_fck                         fixed-factor-clock              E        o           z               e      gpio6_dbck@1000                       ti,gate-clock               e                                         gpio5_dbck@1000                       ti,gate-clock               e                                         gpio4_dbck@1000                       ti,gate-clock               e                                         gpio3_dbck@1000                       ti,gate-clock               e                                         gpio2_dbck@1000                       ti,gate-clock               e                                         wdt3_fck@1000                         ti,wait-gate-clock              e                                         per_l4_ick                        fixed-factor-clock              D        o           z               f      gpio6_ick@1010                        ti,omap3-interface-clock                f                                        gpio5_ick@1010                        ti,omap3-interface-clock                f                                        gpio4_ick@1010                        ti,omap3-interface-clock                f                                        gpio3_ick@1010                        ti,omap3-interface-clock                f                                        gpio2_ick@1010                        ti,omap3-interface-clock                f                                        wdt3_ick@1010                         ti,omap3-interface-clock                f                                        uart3_ick@1010                        ti,omap3-interface-clock                f                                        uart4_ick@1010                        ti,omap3-interface-clock                f                                        gpt9_ick@1010                         ti,omap3-interface-clock                f                      
                  gpt8_ick@1010                         ti,omap3-interface-clock                f                      	                  gpt7_ick@1010                         ti,omap3-interface-clock                f                                        gpt6_ick@1010                         ti,omap3-interface-clock                f                                        gpt5_ick@1010                         ti,omap3-interface-clock                f                                        gpt4_ick@1010                         ti,omap3-interface-clock                f                                        gpt3_ick@1010                         ti,omap3-interface-clock                f                                        gpt2_ick@1010                         ti,omap3-interface-clock                f                                        mcbsp2_ick@1010                       ti,omap3-interface-clock                f                                         mcbsp3_ick@1010                       ti,omap3-interface-clock                f                                        mcbsp4_ick@1010                       ti,omap3-interface-clock                f                                        mcbsp2_gate_fck@1000                          ti,composite-gate-clock             	                                          mcbsp3_gate_fck@1000                          ti,composite-gate-clock             	                                         mcbsp4_gate_fck@1000                          ti,composite-gate-clock             	                                         emu_src_mux_ck@1140                       ti,mux-clock                #   g   h   i           @            j      emu_src_ck                        ti,clkdm-gate-clock             j            k      pclk_fck@1140                         ti,divider-clock                k                   M              @         X      pclkx2_fck@1140                       ti,divider-clock                k                   M              @         X      atclk_fck@1140                        ti,divider-clock                k                   M              @         X      traceclk_src_fck@1140                         ti,mux-clock                #   g   h   i                      @            l      traceclk_fck@1140                         ti,divider-clock                l                   M              @         X      secure_32k_fck                        fixed-clock         =               m      gpt12_fck                         fixed-factor-clock              m        o           z                     wdt1_fck                          fixed-factor-clock              m        o           z         security_l4_ick2                          fixed-factor-clock              D        o           z               n      aes1_ick@a14                          ti,omap3-interface-clock                n                      
                  rng_ick@a14                       ti,omap3-interface-clock                n           
                             sha11_ick@a14                         ti,omap3-interface-clock                n           
                 des1_ick@a14                          ti,omap3-interface-clock                n           
                  cam_mclk@f00                          ti,gate-clock               o                                       cam_ick@f10                   !    ti,omap3-no-wait-interface-clock                D                                         csi2_96m_fck@f00                          ti,gate-clock                                                        security_l3_ick                       fixed-factor-clock              C        o           z               p      pka_ick@a14                       ti,omap3-interface-clock                p           
                 icr_ick@a10                       ti,omap3-interface-clock                O           
                 des2_ick@a10                          ti,omap3-interface-clock                O           
                 mspro_ick@a10                         ti,omap3-interface-clock                O           
                 mailboxes_ick@a10                         ti,omap3-interface-clock                O           
                 ssi_l4_ick                        fixed-factor-clock              D        o           z               w      sr1_fck@c00                       ti,wait-gate-clock              #                                        sr2_fck@c00                       ti,wait-gate-clock              #                                        sr_l4_ick                         fixed-factor-clock              D        o           z         dpll2_fck@40                          ti,divider-clock                +                   M               @         X            q      dpll2_ck@4                        ti,omap3-dpll-clock             #   q               $   @   4                                       r      dpll2_m2_ck@44                        ti,divider-clock                r        M               D         X            s      iva2_ck@0                         ti,wait-gate-clock              s                                           modem_fck@a00                         ti,omap3-interface-clock                #           
                              sad2d_ick@a10                         ti,omap3-interface-clock                C           
                             mad2d_ick@a18                         ti,omap3-interface-clock                C           
                             mspro_fck@a00                         ti,wait-gate-clock                         
                  ssi_ssr_gate_fck_3430es2@a00                           ti,composite-no-wait-gate-clock             $                       
             t      ssi_ssr_div_fck_3430es2@a40                       ti,composite-divider-clock              $                      
@      $                                            u      ssi_ssr_fck_3430es2                       ti,composite-clock              t   u            v      ssi_sst_fck_3430es2                       fixed-factor-clock              v        o           z                    hsotgusb_ick_3430es2@a10                      "    ti,omap3-hsotgusb-interface-clock               N           
                             ssi_ick_3430es2@a10                       ti,omap3-ssi-interface-clock                w           
                             usim_gate_fck@c00                         ti,composite-gate-clock             J           	                              sys_d2_ck                         fixed-factor-clock              #        o           z               y      omap_96m_d2_fck                       fixed-factor-clock              J        o           z               z      omap_96m_d4_fck                       fixed-factor-clock              J        o           z               {      omap_96m_d8_fck                       fixed-factor-clock              J        o           z               |      omap_96m_d10_fck                          fixed-factor-clock              J        o           z   
            }      dpll5_m2_d4_ck                        fixed-factor-clock              x        o           z               ~      dpll5_m2_d8_ck                        fixed-factor-clock              x        o           z                     dpll5_m2_d16_ck                       fixed-factor-clock              x        o           z                     dpll5_m2_d20_ck                       fixed-factor-clock              x        o           z                     usim_mux_fck@c40                          ti,composite-mux-clock        (      #   y   z   {   |   }   ~                               @         X                  usim_fck                          ti,composite-clock                       usim_ick@c10                          ti,omap3-interface-clock                S                      	                  dpll5_ck@d04                          ti,omap3-dpll-clock             #   #             $  L  4                                    dpll5_m2_ck@d50                       ti,divider-clock                        M              P         X            x      sgx_gate_fck@b00                          ti,composite-gate-clock             +                                         core_d3_ck                        fixed-factor-clock              +        o           z                     core_d4_ck                        fixed-factor-clock              +        o           z                     core_d6_ck                        fixed-factor-clock              +        o           z                     omap_192m_alwon_fck                       fixed-factor-clock              '        o           z                     core_d2_ck                        fixed-factor-clock              +        o           z                     sgx_mux_fck@b40                       ti,composite-mux-clock                        /                       @                  sgx_fck                       ti,composite-clock                                  sgx_ick@b10                       ti,wait-gate-clock              C                                         cpefuse_fck@a08                       ti,gate-clock               #           
                              ts_fck@a08                        ti,gate-clock               E           
                             usbtll_fck@a08                        ti,wait-gate-clock              x           
                             usbtll_ick@a18                        ti,omap3-interface-clock                O           
                             mmchs3_ick@a10                        ti,omap3-interface-clock                O           
                             mmchs3_fck@a00                        ti,wait-gate-clock                         
                              dss1_alwon_fck_3430es2@e00                        ti,dss-gate-clock                                                                  dss_ick_3430es2@e10                       ti,omap3-dss-interface-clock                D                                         usbhost_120m_fck@1400                         ti,gate-clock               x                                         usbhost_48m_fck@1400                          ti,dss-gate-clock               5                                          usbhost_ick@1410                          ti,omap3-dss-interface-clock                D                                            clockdomains       core_l3_clkdm             ti,clockdomain                       dpll3_clkdm           ti,clockdomain                    dpll1_clkdm           ti,clockdomain                    per_clkdm             ti,clockdomain        h                                                                                       emu_clkdm             ti,clockdomain              k      dpll4_clkdm           ti,clockdomain              !      wkup_clkdm            ti,clockdomain        $                                    dss_clkdm             ti,clockdomain                                core_l4_clkdm             ti,clockdomain                                                                                                                                cam_clkdm             ti,clockdomain                       iva2_clkdm            ti,clockdomain                    dpll2_clkdm           ti,clockdomain              r      d2d_clkdm             ti,clockdomain                          dpll5_clkdm           ti,clockdomain                    sgx_clkdm             ti,clockdomain                    usbhost_clkdm             ti,clockdomain                                target-module@48320000            ti,sysc-omap2 ti,sysc            H2     H2          	  rev sysc                               R            fck ick                      +                H2        counter@0             ti,omap-counter32k                            interrupt-controller@48200000             ti,omap3-intc                                 H                        target-module@48056000            ti,sysc-omap2 ti,sysc            H`    H`,   H`(           rev sysc syss             #                                            !               N         ick                      +                H`       dma-controller@0              ti,omap3430-sdma ti,omap-sdma                                                &           1            >   `                     gpio@48310000             ti,omap3-gpio            H1                          gpio1            K         ]        m                                         gpio@49050000             ti,omap3-gpio            I                          gpio2            ]        m                           en_usb2_port             y                                enable usb2 port             gpio@49052000             ti,omap3-gpio            I                          gpio3            ]        m                              gpio@49054000             ti,omap3-gpio            I@                          gpio4            ]        m                              gpio@49056000             ti,omap3-gpio            I`                !         gpio5            ]        m                                          gpio@49058000             ti,omap3-gpio            I                "         gpio6            ]        m                                          serial@4806a000           ti,omap3-uart            H                   H     R        .      1      2        3tx rx            uart1           =l       serial@4806c000           ti,omap3-uart            H                  I     J        .      3      4        3tx rx            uart2           =l       serial@49020000           ti,omap3-uart            I                   J     n        .      5      6        3tx rx            uart3           =l         pdefault         ~         i2c@48070000              ti,omap3-i2c             H                 8        .                    3tx rx                        +             i2c1            = '@   twl@48              H                                  ti,twl4030                               pdefault         ~         rtc           ti,twl4030-rtc                    bci           ti,twl4030-bci              	                                    vac       watchdog              ti,twl4030-wdt        regulator-vaux1           ti,twl4030-vaux1          regulator-vaux2           ti,twl4030-vaux2            usb_1v8          w@         w@               regulator-vaux3           ti,twl4030-vaux3          regulator-vaux4           ti,twl4030-vaux4          regulator-vdd1            ti,twl4030-vdd1          	'                            regulator-vdac            ti,twl4030-vdac          w@         w@      regulator-vio             ti,twl4030-vio        regulator-vintana1            ti,twl4030-vintana1       regulator-vintana2            ti,twl4030-vintana2       regulator-vintdig             ti,twl4030-vintdig        regulator-vmmc1           ti,twl4030-vmmc1             :         0                  regulator-vmmc2           ti,twl4030-vmmc2             :         0                 regulator-vusb1v5             ti,twl4030-vusb1v5                    regulator-vusb1v8             ti,twl4030-vusb1v8                    regulator-vusb3v1             ti,twl4030-vusb3v1                    regulator-vpll1           ti,twl4030-vpll1          regulator-vpll2           ti,twl4030-vpll2             w@         w@                          regulator-vsim            ti,twl4030-vsim          w@         -                  gpio              ti,twl4030-gpio          ]        m                                               en_on_board_gpio_61          y                                en_hsusb2_clk            twl4030-usb           ti,twl4030-usb              
                      
                      &           /                     pwm           ti,twl4030-pwm          :         pwmled            ti,twl4030-pwmled           :         pwrbutton             ti,twl4030-pwrbutton                      keypad            ti,twl4030-keypad                       E           U         8  h           	  
 7    S         madc              ti,twl4030-madc                     u                     power         1    ti,twl4030-power-omap3-evm ti,twl4030-power-idle                         i2c@48072000              ti,omap3-i2c             H                 9        .                    3tx rx                        +             i2c2            =       i2c@48060000              ti,omap3-i2c             H                 =        .                    3tx rx                        +             i2c3            =    tvp5146@5c            ti,tvp5146m2                \         mailbox@48094000              ti,omap3-mailbox             mailbox          H	@                                                    dsp                                                 spi@48098000              ti,omap2-mcspi           H	                A                     +             mcspi1                   @  .      #      $      %      &      '      (      )      *         3tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3    tsc2046@0                          ti,tsc2046           B@                               @                      #          , (          <            L         W                                    e                   spi@4809a000              ti,omap2-mcspi           H	                B                     +             mcspi2                      .      +      ,      -      .        3tx0 rx0 tx1 rx1       spi@480b8000              ti,omap2-mcspi           H                [                     +             mcspi3                      .                                3tx0 rx0 tx1 rx1       spi@480ba000              ti,omap2-mcspi           H                0                     +             mcspi4                     .      F      G        3tx0 rx0       1w@480b2000           ti,omap3-1w          H                 :         hdq1w         mmc@4809c000              ti,omap3-hsmmc           H	                S         mmc1             r        .      =      >        3tx rx                            S                                              pdefault         ~         mmc@480b4000              ti,omap3-hsmmc           H@                V         mmc2            .      /      0        3tx rx                 V     .                                                             +            pdefault         ~      wlcore@2          
    ti,wl1271                                     N        irq wakeup          I          mmc@480ad000              ti,omap3-hsmmc           H
                ^         mmc3            .      M      N        3tx rx         	  disabled          mmu@480bd400                          ti,omap2-iommu           H                         mmu_isp                             mmu@5d000000                          ti,omap2-iommu           ]                           mmu_iva       	  disabled          wdt@48314000              ti,omap3-wdt             H1@          
   wd_timer2         mcbsp@48074000            ti,omap3-mcbsp           H@            mpu                ;   <        common tx rx                        mcbsp1          .                     3tx rx                        fck       	  disabled          target-module@480a0000            ti,sysc-omap2 ti,sysc            H
 <   H
 @   H
 D           rev sysc syss                                     !                        ick                      +                H
         rng@0             ti,omap2-rng                                 4         mcbsp@49022000            ti,omap3-mcbsp           I     I            mpu sidetone                   >   ?           common tx rx sidetone                       mcbsp2 mcbsp2_sidetone          .      !      "        3tx rx                           fck ick       	  disabled          mcbsp@49024000            ti,omap3-mcbsp           I@    I            mpu sidetone                   Y   Z           common tx rx sidetone                       mcbsp3 mcbsp3_sidetone          .                    3tx rx                           fck ick       	  disabled          mcbsp@49026000            ti,omap3-mcbsp           I`            mpu                6   7        common tx rx                        mcbsp4          .                    3tx rx                        fck         '          	  disabled          mcbsp@48096000            ti,omap3-mcbsp           H	`            mpu                Q   R        common tx rx                        mcbsp5          .                    3tx rx                        fck       	  disabled          sham@480c3000             ti,omap3-sham            sham             H0    d            1        .      E        3rx        target-module@48318000            ti,sysc-omap2-timer ti,sysc          H1    H1   H1           rev sysc syss             '                          !                           fck ick                      +                H1             8         L   timer@0           ti,omap3430-timer                                        fck             %         W        f           v   E         target-module@49032000            ti,sysc-omap2-timer ti,sysc          I     I    I            rev sysc syss             '                          !                           fck ick                      +                I        timer@0           ti,omap3430-timer                               &         timer@49034000            ti,omap3430-timer            I@                '         timer3        timer@49036000            ti,omap3430-timer            I`                (         timer4        timer@49038000            ti,omap3430-timer            I                )         timer5                 timer@4903a000            ti,omap3430-timer            I                *         timer6                 timer@4903c000            ti,omap3430-timer            I                +         timer7                 timer@4903e000            ti,omap3430-timer            I                ,         timer8                          timer@49040000            ti,omap3430-timer            I                 -         timer9                 timer@48086000            ti,omap3430-timer            H`                .         timer10                timer@48088000            ti,omap3430-timer            H                /         timer11                target-module@48304000            ti,sysc-omap2-timer ti,sysc          H0@    H0@   H0@           rev sysc syss             '                          !                           fck ick                      +                H0@       timer@0           ti,omap3430-timer                               _         W                  usbhstll@48062000             ti,usbhs-tll             H                 N         usb_tll_hs        usbhshost@48064000            ti,usbhs-host            H@             usb_host_hs                      +                   	  ehci-phy       ohci@48064400             ti,ohci-omap3            HD                L               ehci@48064800             ti,ehci-omap             HH                M                       gpmc@6e000000             ti,omap3430-gpmc             gpmc             n                         .              3rxtx                                               +                                 ]        m                     0             ,                    ethernet@gpmc             smsc,lan9221 smsc,lan9115                                            4           N           \           n                                     (           -                      -                                             x                    :   K        Q   K        k                                                                                                                                      pdefault         ~        nand@0,0              ti,omap2-nand                                                                  	micron,mt29f2g16abdhc           	                      	#bch8            	3            N            \   ,        n   ,                      "           ,           (           6           @           R            R           (                                 +            usb_otg_hs@480ab000           ti,omap3-musb            H
                \   ]        mc dma           usb_otg_hs          	D           	O           	W           	`            	o                  	  	wusb2-phy            *           	   2      dss@48050000              ti,omap3-dss             H             okay          	   dss_core                         fck                      +                     	          	           pdefault         ~    	   dispc@48050400            ti,omap3-dispc           H                      
   dss_dispc                        fck       encoder@4804fc00              ti,omap3-dsi             H    H    @H             proto phy pll                     	  disabled          	   dss_dsi1                            fck sys_clk                      +          encoder@48050800              ti,omap3-rfbi            H          	  disabled          	   dss_rfbi                            fck ick       encoder@48050c00              ti,omap3-venc            H          	  disabled          	   dss_venc                         fck       port       endpoint            	  
        	                          ssi-controller@48058000           ti,omap3-ssi             ssi         okay             H    H            sys gdd             G        gdd_mpu                      +                         v              ssi_ssr_fck ssi_sst_fck ssi_ick    ssi-port@4805a000             ti,omap3-ssi-port            H    H            tx rx               C   D      ssi-port@4805b000             ti,omap3-ssi-port            H    H            tx rx               E   F         pinmux@480025d8            ti,omap3-padconf pinctrl-single          H %   $                     +                                             5           S          pdefault         ~     pinmux_ehci_phy_pins                                         pinmux_hsusb2_2_pins          0                                 "                      isp@480bc000              ti,omap3-isp             H   H   |                    	                l        	                  ports                        +             bandgap@48002524             H %$             ti,omap34xx-bandgap         	                     target-module@480cb000            ti,sysc-omap3430-sr ti,sysc          smartreflex_core             H$           sysc                                   fck                      +                H       smartreflex@0             ti,omap3-smartreflex-core                                        target-module@480c9000            ti,sysc-omap3430-sr ti,sysc          smartreflex_mpu_iva          H$           sysc                                   fck                      +                H       smartreflex@480c9000              ti,omap3-smartreflex-mpu-iva                                         target-module@50000000            ti,sysc-omap2 ti,sysc            P             rev                        fck ick                      +                P     @          opp-table             operating-points-v2-ti-cpu                            opp1-125000000          	    sY@        	           
         opp2-250000000          	    沀        	 g8 g8 g8        
            
      opp3-500000000          	    e         	 O O O        
         opp4-550000000          	     U        	 tx tx tx        
         opp5-600000000          	    #F         	 p p p        
         opp6-720000000          	    *T         	 p p p        
            
         thermal-zones      cpu_thermal         
*           
@          
N      N         
[         trips      cpu_alert           
k 8        
w           passive                  cpu_crit            
k _        
w        	   critical             cooling-maps       map0            
          
                 regulator-vddvario            regulator-fixed       	  vddvario                              regulator-vdd33a              regulator-fixed         vdd33a                            hsusb2_power_reg              regulator-fixed         hsusb2_vbus          2Z         2Z        m                 
 p         
                 hsusb2_phy            usb-nop-xceiv           
                          /            pdefault         ~                   leds          
    gpio-leds      ledb            
omap3evm::ledb                           
default-on           wl12xx_vmmc           regulator-fixed         vwl1271          w@         w@        m                  
 p         
        
          pdefault         ~                    backlight             gpio-backlight           
                      regulator-lcd-3v3             regulator-fixed         lcd_3v3          2Z         2Z        
 p        m                           display           sharp,ls037v7dw01           
lcd         
                                        
                $                                 port       endpoint            	             
            memory@80000000          |memory                          	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 mmc0 mmc1 mmc2 serial0 serial1 serial2 display0 device_type reg clocks clock-names clock-latency operating-points-v2 #cooling-cells cpu0-supply phandle interrupts ti,hwmods ranges #pinctrl-cells #interrupt-cells interrupt-controller pinctrl-single,register-width pinctrl-single,function-mask pinctrl-names pinctrl-0 pinctrl-single,pins syscon regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift reg-names ti,sysc-mask ti,sysc-sidle ti,syss-mask dmas dma-names clock-frequency ti,max-div ti,index-starts-at-one clock-mult clock-div ti,set-bit-to-disable ti,clock-mult ti,clock-div ti,set-rate-parent ti,index-power-of-two ti,low-power-stop ti,lock ti,low-power-bypass ti,dividers ti,sysc-midle #dma-cells dma-channels dma-requests ti,gpio-always-on gpio-controller #gpio-cells gpio-hog gpios output-low line-name interrupts-extended bci3v1-supply io-channels io-channel-names regulator-always-on ti,use-leds usb1v5-supply usb1v8-supply usb3v1-supply usb_mode #phy-cells #pwm-cells keypad,num-rows keypad,num-columns linux,keymap #io-channel-cells ti,use_poweroff #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,spi-num-cs spi-max-frequency vcc-supply ti,x-min ti,x-max ti,y-min ti,y-max ti,x-plate-ohms ti,pressure-max ti,swap-xy wakeup-source pendown-gpio ti,dual-volt pbias-supply vmmc-supply vqmmc-supply bus-width non-removable cap-power-off-card interrupt-names ref-clock-frequency status #iommu-cells ti,#tlb-entries ti,buffer-size #sound-dai-cells ti,no-reset-on-init ti,no-idle ti,timer-alwon assigned-clocks assigned-clock-parents ti,timer-dsp ti,timer-pwm ti,timer-secure port2-mode remote-wakeup-connected phys gpmc,num-cs gpmc,num-waitpins bank-width gpmc,device-width gpmc,cycle2cycle-samecsen gpmc,cycle2cycle-diffcsen gpmc,cs-on-ns gpmc,cs-rd-off-ns gpmc,cs-wr-off-ns gpmc,adv-on-ns gpmc,adv-rd-off-ns gpmc,adv-wr-off-ns gpmc,oe-on-ns gpmc,oe-off-ns gpmc,we-on-ns gpmc,we-off-ns gpmc,rd-cycle-ns gpmc,wr-cycle-ns gpmc,access-ns gpmc,page-burst-access-ns gpmc,bus-turnaround-ns gpmc,cycle2cycle-delay-ns gpmc,wait-monitoring-ns gpmc,clk-activation-ns gpmc,wr-data-mux-bus-ns gpmc,wr-access-ns vddvario-supply vdd33a-supply reg-io-width smsc,save-mac-address linux,mtd-name nand-bus-width ti,nand-ecc-opt gpmc,sync-clk-ps multipoint num-eps ram-bits interface-type usb-phy phy-names power vdds_dsi-supply vdda_video-supply remote-endpoint data-lines iommus ti,phy-type #thermal-sensor-cells opp-hz opp-microvolt opp-supported-hw opp-suspend turbo-mode polling-delay-passive polling-delay coefficients thermal-sensors temperature hysteresis trip cooling-device startup-delay-us enable-active-high reset-gpios label linux,default-trigger vin-supply default-on power-supply envdd-supply enable-gpios mode-gpios 