     8     (                                           Q    headacoustics,omap3-ha technexion,omap3-tao3530 ti,omap3430 ti,omap34xx ti,omap3                                     +         3   7TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM     chosen        aliases          =/ocp@68000000/i2c@48070000           B/ocp@68000000/i2c@48072000           G/ocp@68000000/i2c@48060000           L/ocp@68000000/mmc@4809c000           Q/ocp@68000000/mmc@480b4000           V/ocp@68000000/mmc@480ad000           [/ocp@68000000/serial@4806a000            c/ocp@68000000/serial@4806c000            k/ocp@68000000/serial@49020000         cpus                         +       cpu@0             arm,cortex-a8            scpu                                   cpu                                                                   pmu@54000000              arm,cortex-a8-pmu            T                           debugss       soc           ti,omap-infra      mpu           ti,omap3-mpu             mpu       iva       
    ti,iva2.2            iva    dsp           ti,omap3-c64                ocp@68000000              ti,omap3-l3-smx simple-bus           h                  	   
                     +                      l3_main    l4@48000000           ti,omap3-l4-core simple-bus                      +                H         scm@2000              ti,omap3-scm simple-bus                                       +                           pinmux@30              ti,omap3-padconf pinctrl-single             0  8                     +                                            ,           J          gdefault         u               	   
      pinmux_hsusbb2_pins       `                                                                      pinmux_mmc1_pins          P                                 "    $    &                    pinmux_mmc2_pins          0    (    *    ,    .    0    2                    pinmux_wlan_gpio              ^         pinmux_uart3_pins             n  A   p                      pinmux_i2c3_pins                                      pinmux_mcspi1_pins                                                  pinmux_mcspi3_pins                                               pinmux_mcbsp3_pins             <      >     @     B                    pinmux_twl4030_pins             A                  pinmux_sound2_pins             n         pinmux_led_blue_pins                              	      pinmux_led_green_pins                             
      pinmux_led_red_pins                                 pinmux_poweroff_pins                                  pinmux_powerdown_input_pins                               fpga_boot0_pins                                                  fpga_boot1_pins             r     t      v      x                       scm_conf@270              syscon simple-bus              p  0                     +                  p  0               pbias_regulator@2b0           ti,pbias-omap3 ti,pbias-omap                                pbias_mmc_omap2430          pbias_mmc_omap2430           w@         -                     clocks                       +       mcbsp5_mux_fck@68                         ti,composite-mux-clock                                        h                  mcbsp5_fck                        ti,composite-clock                                  mcbsp1_mux_fck@4                          ti,composite-mux-clock                                                          mcbsp1_fck                        ti,composite-clock                                   mcbsp2_mux_fck@4                          ti,composite-mux-clock                                                          mcbsp2_fck                        ti,composite-clock                                   mcbsp3_mux_fck@68                         ti,composite-mux-clock                             h                  mcbsp3_fck                        ti,composite-clock                                   mcbsp4_mux_fck@68                         ti,composite-mux-clock                                        h                  mcbsp4_fck                        ti,composite-clock                                        clockdomains          pinmux@a00             ti,omap3-padconf pinctrl-single            
    \                     +                                            ,           J     pinmux_twl4030_vpins                                                                   target-module@480a6000            ti,sysc-omap2 ti,sysc            H
`D   H
`H   H
`L           rev sysc syss                      
                                          ick                      +                H
`           	  %disabled       aes1@0            ti,omap3-aes                    P                     ,      	      
        1tx rx            target-module@480c5000            ti,sysc-omap2 ti,sysc            HPD   HPH   HPL           rev sysc syss                      
                                          ick                      +                HP           	  %disabled       aes2@0            ti,omap3-aes                    P                     ,      A      B        1tx rx            prm@48306000              ti,omap3-prm             H0`   @                clocks                       +       virt_16_8m_ck                         fixed-clock         ; Y             "      osc_sys_ck@d40                        ti,mux-clock                             !   "           @            #      sys_ck@1270                       ti,divider-clock                #                   K              p         V            (      sys_clkout1@d70                       ti,gate-clock               #           p                 dpll3_x2_ck                       fixed-factor-clock              $        m           x         dpll3_m2x2_ck                         fixed-factor-clock              %        m           x               '      dpll4_x2_ck                       fixed-factor-clock              &        m           x         corex2_fck                        fixed-factor-clock              '        m           x               )      wkup_l4_ick                       fixed-factor-clock              (        m           x               X      corex2_d3_fck                         fixed-factor-clock              )        m           x                     corex2_d5_fck                         fixed-factor-clock              )        m           x                        clockdomains             cm@48004000           ti,omap3-cm          H @   @    clocks                       +       dummy_apb_pclk                        fixed-clock         ;          omap_32k_fck                          fixed-clock         ;               J      virt_12m_ck                       fixed-clock         ;                    virt_13m_ck                       fixed-clock         ; ]@                  virt_19200000_ck                          fixed-clock         ;$                   virt_26000000_ck                          fixed-clock         ;                   virt_38_4m_ck                         fixed-clock         ;I             !      dpll4_ck@d00                          ti,omap3-dpll-per-clock             (   (                 D  0            &      dpll4_m2_ck@d48                       ti,divider-clock                &        K   ?           H         V            *      dpll4_m2x2_mul_ck                         fixed-factor-clock              *        m           x               +      dpll4_m2x2_ck@d00                         ti,gate-clock               +                                            ,      omap_96m_alwon_fck                        fixed-factor-clock              ,        m           x               3      dpll3_ck@d00                          ti,omap3-dpll-core-clock                (   (                 @  0            $      dpll3_m3_ck@1140                          ti,divider-clock                $                   K              @         V            -      dpll3_m3x2_mul_ck                         fixed-factor-clock              -        m           x               .      dpll3_m3x2_ck@d00                         ti,gate-clock               .                                            /      emu_core_alwon_ck                         fixed-factor-clock              /        m           x               l      sys_altclk                        fixed-clock         ;                8      mcbsp_clks                        fixed-clock         ;                      dpll3_m2_ck@d40                       ti,divider-clock                $                   K              @         V            %      core_ck                       fixed-factor-clock              %        m           x               0      dpll1_fck@940                         ti,divider-clock                0                   K              	@         V            1      dpll1_ck@904                          ti,omap3-dpll-clock             (   1           	  	$  	@  	4                  dpll1_x2_ck                       fixed-factor-clock                      m           x               2      dpll1_x2m2_ck@944                         ti,divider-clock                2        K              	D         V            F      cm_96m_fck                        fixed-factor-clock              3        m           x               4      omap_96m_fck@d40                          ti,mux-clock                4   (                      @            O      dpll4_m3_ck@e40                       ti,divider-clock                &                   K               @         V            5      dpll4_m3x2_mul_ck                         fixed-factor-clock              5        m           x               6      dpll4_m3x2_ck@d00                         ti,gate-clock               6                                            7      omap_54m_fck@d40                          ti,mux-clock                7   8                      @            B      cm_96m_d2_fck                         fixed-factor-clock              4        m           x               9      omap_48m_fck@d40                          ti,mux-clock                9   8                      @            :      omap_12m_fck                          fixed-factor-clock              :        m           x               Q      dpll4_m4_ck@e40                       ti,divider-clock                &        K              @         V            ;      dpll4_m4x2_mul_ck                         ti,fixed-factor-clock               ;                                           <      dpll4_m4x2_ck@d00                         ti,gate-clock               <                                                           dpll4_m5_ck@f40                       ti,divider-clock                &        K   ?           @         V            =      dpll4_m5x2_mul_ck                         ti,fixed-factor-clock               =                                           >      dpll4_m5x2_ck@d00                         ti,gate-clock               >                                                     t      dpll4_m6_ck@1140                          ti,divider-clock                &                   K   ?           @         V            ?      dpll4_m6x2_mul_ck                         fixed-factor-clock              ?        m           x               @      dpll4_m6x2_ck@d00                         ti,gate-clock               @                                            A      emu_per_alwon_ck                          fixed-factor-clock              A        m           x               m      clkout2_src_gate_ck@d70                        ti,composite-no-wait-gate-clock             0                      p            C      clkout2_src_mux_ck@d70                        ti,composite-mux-clock              0   (   4   B           p            D      clkout2_src_ck                        ti,composite-clock              C   D            E      sys_clkout2@d70                       ti,divider-clock                E                   K   @           p               mpu_ck                        fixed-factor-clock              F        m           x               G      arm_fck@924                       ti,divider-clock                G           	$        K         emu_mpu_alwon_ck                          fixed-factor-clock              G        m           x               n      l3_ick@a40                        ti,divider-clock                0        K              
@         V            H      l4_ick@a40                        ti,divider-clock                H                   K              
@         V            I      rm_ick@c40                        ti,divider-clock                I                   K              @         V      gpt10_gate_fck@a00                        ti,composite-gate-clock             (                      
             K      gpt10_mux_fck@a40                         ti,composite-mux-clock              J   (                      
@            L      gpt10_fck                         ti,composite-clock              K   L      gpt11_gate_fck@a00                        ti,composite-gate-clock             (                      
             M      gpt11_mux_fck@a40                         ti,composite-mux-clock              J   (                      
@            N      gpt11_fck                         ti,composite-clock              M   N      core_96m_fck                          fixed-factor-clock              O        m           x                     mmchs2_fck@a00                        ti,wait-gate-clock                         
                              mmchs1_fck@a00                        ti,wait-gate-clock                         
                              i2c3_fck@a00                          ti,wait-gate-clock                         
                              i2c2_fck@a00                          ti,wait-gate-clock                         
                              i2c1_fck@a00                          ti,wait-gate-clock                         
                              mcbsp5_gate_fck@a00                       ti,composite-gate-clock                        
           
                   mcbsp1_gate_fck@a00                       ti,composite-gate-clock                        	           
                   core_48m_fck                          fixed-factor-clock              :        m           x               P      mcspi4_fck@a00                        ti,wait-gate-clock              P           
                              mcspi3_fck@a00                        ti,wait-gate-clock              P           
                              mcspi2_fck@a00                        ti,wait-gate-clock              P           
                              mcspi1_fck@a00                        ti,wait-gate-clock              P           
                              uart2_fck@a00                         ti,wait-gate-clock              P           
                              uart1_fck@a00                         ti,wait-gate-clock              P           
                              core_12m_fck                          fixed-factor-clock              Q        m           x               R      hdq_fck@a00                       ti,wait-gate-clock              R           
                              core_l3_ick                       fixed-factor-clock              H        m           x               S      sdrc_ick@a10                          ti,wait-gate-clock              S           
                             gpmc_fck                          fixed-factor-clock              S        m           x         core_l4_ick                       fixed-factor-clock              I        m           x               T      mmchs2_ick@a10                        ti,omap3-interface-clock                T           
                             mmchs1_ick@a10                        ti,omap3-interface-clock                T           
                             hdq_ick@a10                       ti,omap3-interface-clock                T           
                             mcspi4_ick@a10                        ti,omap3-interface-clock                T           
                             mcspi3_ick@a10                        ti,omap3-interface-clock                T           
                             mcspi2_ick@a10                        ti,omap3-interface-clock                T           
                             mcspi1_ick@a10                        ti,omap3-interface-clock                T           
                             i2c3_ick@a10                          ti,omap3-interface-clock                T           
                             i2c2_ick@a10                          ti,omap3-interface-clock                T           
                             i2c1_ick@a10                          ti,omap3-interface-clock                T           
                             uart2_ick@a10                         ti,omap3-interface-clock                T           
                             uart1_ick@a10                         ti,omap3-interface-clock                T           
                             gpt11_ick@a10                         ti,omap3-interface-clock                T           
                             gpt10_ick@a10                         ti,omap3-interface-clock                T           
                             mcbsp5_ick@a10                        ti,omap3-interface-clock                T           
           
                  mcbsp1_ick@a10                        ti,omap3-interface-clock                T           
           	                  omapctrl_ick@a10                          ti,omap3-interface-clock                T           
                             dss_tv_fck@e00                        ti,gate-clock               B                                         dss_96m_fck@e00                       ti,gate-clock               O                                         dss2_alwon_fck@e00                        ti,gate-clock               (                                         dummy_ck                          fixed-clock         ;          gpt1_gate_fck@c00                         ti,composite-gate-clock             (                                    U      gpt1_mux_fck@c40                          ti,composite-mux-clock              J   (           @            V      gpt1_fck                          ti,composite-clock              U   V                 aes2_ick@a10                          ti,omap3-interface-clock                T                      
                  wkup_32k_fck                          fixed-factor-clock              J        m           x               W      gpio1_dbck@c00                        ti,gate-clock               W                                         sha12_ick@a10                         ti,omap3-interface-clock                T           
                             wdt2_fck@c00                          ti,wait-gate-clock              W                                         wdt2_ick@c10                          ti,omap3-interface-clock                X                                        wdt1_ick@c10                          ti,omap3-interface-clock                X                                        gpio1_ick@c10                         ti,omap3-interface-clock                X                                        omap_32ksync_ick@c10                          ti,omap3-interface-clock                X                                        gpt12_ick@c10                         ti,omap3-interface-clock                X                                        gpt1_ick@c10                          ti,omap3-interface-clock                X                                         per_96m_fck                       fixed-factor-clock              3        m           x                     per_48m_fck                       fixed-factor-clock              :        m           x               Y      uart3_fck@1000                        ti,wait-gate-clock              Y                                         gpt2_gate_fck@1000                        ti,composite-gate-clock             (                                   Z      gpt2_mux_fck@1040                         ti,composite-mux-clock              J   (           @            [      gpt2_fck                          ti,composite-clock              Z   [                 gpt3_gate_fck@1000                        ti,composite-gate-clock             (                                   \      gpt3_mux_fck@1040                         ti,composite-mux-clock              J   (                      @            ]      gpt3_fck                          ti,composite-clock              \   ]      gpt4_gate_fck@1000                        ti,composite-gate-clock             (                                   ^      gpt4_mux_fck@1040                         ti,composite-mux-clock              J   (                      @            _      gpt4_fck                          ti,composite-clock              ^   _      gpt5_gate_fck@1000                        ti,composite-gate-clock             (                                   `      gpt5_mux_fck@1040                         ti,composite-mux-clock              J   (                      @            a      gpt5_fck                          ti,composite-clock              `   a      gpt6_gate_fck@1000                        ti,composite-gate-clock             (                                   b      gpt6_mux_fck@1040                         ti,composite-mux-clock              J   (                      @            c      gpt6_fck                          ti,composite-clock              b   c      gpt7_gate_fck@1000                        ti,composite-gate-clock             (                                   d      gpt7_mux_fck@1040                         ti,composite-mux-clock              J   (                      @            e      gpt7_fck                          ti,composite-clock              d   e      gpt8_gate_fck@1000                        ti,composite-gate-clock             (           	                        f      gpt8_mux_fck@1040                         ti,composite-mux-clock              J   (                      @            g      gpt8_fck                          ti,composite-clock              f   g      gpt9_gate_fck@1000                        ti,composite-gate-clock             (           
                        h      gpt9_mux_fck@1040                         ti,composite-mux-clock              J   (                      @            i      gpt9_fck                          ti,composite-clock              h   i      per_32k_alwon_fck                         fixed-factor-clock              J        m           x               j      gpio6_dbck@1000                       ti,gate-clock               j                                         gpio5_dbck@1000                       ti,gate-clock               j                                         gpio4_dbck@1000                       ti,gate-clock               j                                         gpio3_dbck@1000                       ti,gate-clock               j                                         gpio2_dbck@1000                       ti,gate-clock               j                                         wdt3_fck@1000                         ti,wait-gate-clock              j                                         per_l4_ick                        fixed-factor-clock              I        m           x               k      gpio6_ick@1010                        ti,omap3-interface-clock                k                                        gpio5_ick@1010                        ti,omap3-interface-clock                k                                        gpio4_ick@1010                        ti,omap3-interface-clock                k                                        gpio3_ick@1010                        ti,omap3-interface-clock                k                                        gpio2_ick@1010                        ti,omap3-interface-clock                k                                        wdt3_ick@1010                         ti,omap3-interface-clock                k                                        uart3_ick@1010                        ti,omap3-interface-clock                k                                        uart4_ick@1010                        ti,omap3-interface-clock                k                                        gpt9_ick@1010                         ti,omap3-interface-clock                k                      
                  gpt8_ick@1010                         ti,omap3-interface-clock                k                      	                  gpt7_ick@1010                         ti,omap3-interface-clock                k                                        gpt6_ick@1010                         ti,omap3-interface-clock                k                                        gpt5_ick@1010                         ti,omap3-interface-clock                k                                        gpt4_ick@1010                         ti,omap3-interface-clock                k                                        gpt3_ick@1010                         ti,omap3-interface-clock                k                                        gpt2_ick@1010                         ti,omap3-interface-clock                k                                        mcbsp2_ick@1010                       ti,omap3-interface-clock                k                                         mcbsp3_ick@1010                       ti,omap3-interface-clock                k                                        mcbsp4_ick@1010                       ti,omap3-interface-clock                k                                        mcbsp2_gate_fck@1000                          ti,composite-gate-clock                                                       mcbsp3_gate_fck@1000                          ti,composite-gate-clock                                                      mcbsp4_gate_fck@1000                          ti,composite-gate-clock                                                      emu_src_mux_ck@1140                       ti,mux-clock                (   l   m   n           @            o      emu_src_ck                        ti,clkdm-gate-clock             o            p      pclk_fck@1140                         ti,divider-clock                p                   K              @         V      pclkx2_fck@1140                       ti,divider-clock                p                   K              @         V      atclk_fck@1140                        ti,divider-clock                p                   K              @         V      traceclk_src_fck@1140                         ti,mux-clock                (   l   m   n                      @            q      traceclk_fck@1140                         ti,divider-clock                q                   K              @         V      secure_32k_fck                        fixed-clock         ;               r      gpt12_fck                         fixed-factor-clock              r        m           x                    wdt1_fck                          fixed-factor-clock              r        m           x         security_l4_ick2                          fixed-factor-clock              I        m           x               s      aes1_ick@a14                          ti,omap3-interface-clock                s                      
                  rng_ick@a14                       ti,omap3-interface-clock                s           
                             sha11_ick@a14                         ti,omap3-interface-clock                s           
                 des1_ick@a14                          ti,omap3-interface-clock                s           
                  cam_mclk@f00                          ti,gate-clock               t                                       cam_ick@f10                   !    ti,omap3-no-wait-interface-clock                I                                         csi2_96m_fck@f00                          ti,gate-clock                                                        security_l3_ick                       fixed-factor-clock              H        m           x               u      pka_ick@a14                       ti,omap3-interface-clock                u           
                 icr_ick@a10                       ti,omap3-interface-clock                T           
                 des2_ick@a10                          ti,omap3-interface-clock                T           
                 mspro_ick@a10                         ti,omap3-interface-clock                T           
                 mailboxes_ick@a10                         ti,omap3-interface-clock                T           
                 ssi_l4_ick                        fixed-factor-clock              I        m           x               |      sr1_fck@c00                       ti,wait-gate-clock              (                                        sr2_fck@c00                       ti,wait-gate-clock              (                                        sr_l4_ick                         fixed-factor-clock              I        m           x         dpll2_fck@40                          ti,divider-clock                0                   K               @         V            v      dpll2_ck@4                        ti,omap3-dpll-clock             (   v               $   @   4                                       w      dpll2_m2_ck@44                        ti,divider-clock                w        K               D         V            x      iva2_ck@0                         ti,wait-gate-clock              x                                           modem_fck@a00                         ti,omap3-interface-clock                (           
                              sad2d_ick@a10                         ti,omap3-interface-clock                H           
                             mad2d_ick@a18                         ti,omap3-interface-clock                H           
                             mspro_fck@a00                         ti,wait-gate-clock                         
                  ssi_ssr_gate_fck_3430es2@a00                           ti,composite-no-wait-gate-clock             )                       
             y      ssi_ssr_div_fck_3430es2@a40                       ti,composite-divider-clock              )                      
@      $  
                                          z      ssi_ssr_fck_3430es2                       ti,composite-clock              y   z            {      ssi_sst_fck_3430es2                       fixed-factor-clock              {        m           x              
      hsotgusb_ick_3430es2@a10                      "    ti,omap3-hsotgusb-interface-clock               S           
                             ssi_ick_3430es2@a10                       ti,omap3-ssi-interface-clock                |           
                             usim_gate_fck@c00                         ti,composite-gate-clock             O           	                              sys_d2_ck                         fixed-factor-clock              (        m           x               ~      omap_96m_d2_fck                       fixed-factor-clock              O        m           x                     omap_96m_d4_fck                       fixed-factor-clock              O        m           x                     omap_96m_d8_fck                       fixed-factor-clock              O        m           x                     omap_96m_d10_fck                          fixed-factor-clock              O        m           x   
                  dpll5_m2_d4_ck                        fixed-factor-clock              }        m           x                     dpll5_m2_d8_ck                        fixed-factor-clock              }        m           x                     dpll5_m2_d16_ck                       fixed-factor-clock              }        m           x                     dpll5_m2_d20_ck                       fixed-factor-clock              }        m           x                     usim_mux_fck@c40                          ti,composite-mux-clock        (      (   ~                                              @         V                  usim_fck                          ti,composite-clock                       usim_ick@c10                          ti,omap3-interface-clock                X                      	                  dpll5_ck@d04                          ti,omap3-dpll-clock             (   (             $  L  4                                    dpll5_m2_ck@d50                       ti,divider-clock                        K              P         V            }      sgx_gate_fck@b00                          ti,composite-gate-clock             0                                         core_d3_ck                        fixed-factor-clock              0        m           x                     core_d4_ck                        fixed-factor-clock              0        m           x                     core_d6_ck                        fixed-factor-clock              0        m           x                     omap_192m_alwon_fck                       fixed-factor-clock              ,        m           x                     core_d2_ck                        fixed-factor-clock              0        m           x                     sgx_mux_fck@b40                       ti,composite-mux-clock                        4                       @                  sgx_fck                       ti,composite-clock                                  sgx_ick@b10                       ti,wait-gate-clock              H                                         cpefuse_fck@a08                       ti,gate-clock               (           
                              ts_fck@a08                        ti,gate-clock               J           
                             usbtll_fck@a08                        ti,wait-gate-clock              }           
                             usbtll_ick@a18                        ti,omap3-interface-clock                T           
                             mmchs3_ick@a10                        ti,omap3-interface-clock                T           
                             mmchs3_fck@a00                        ti,wait-gate-clock                         
                              dss1_alwon_fck_3430es2@e00                        ti,dss-gate-clock                                                                  dss_ick_3430es2@e10                       ti,omap3-dss-interface-clock                I                                         usbhost_120m_fck@1400                         ti,gate-clock               }                                         usbhost_48m_fck@1400                          ti,dss-gate-clock               :                                          usbhost_ick@1410                          ti,omap3-dss-interface-clock                I                                            clockdomains       core_l3_clkdm             ti,clockdomain                       dpll3_clkdm           ti,clockdomain              $      dpll1_clkdm           ti,clockdomain                    per_clkdm             ti,clockdomain        h                                                                                       emu_clkdm             ti,clockdomain              p      dpll4_clkdm           ti,clockdomain              &      wkup_clkdm            ti,clockdomain        $                                    dss_clkdm             ti,clockdomain                                core_l4_clkdm             ti,clockdomain                                                                                                                                cam_clkdm             ti,clockdomain                       iva2_clkdm            ti,clockdomain                    dpll2_clkdm           ti,clockdomain              w      d2d_clkdm             ti,clockdomain                          dpll5_clkdm           ti,clockdomain                    sgx_clkdm             ti,clockdomain                    usbhost_clkdm             ti,clockdomain                                target-module@48320000            ti,sysc-omap2 ti,sysc            H2     H2          	  rev sysc            
                   W            fck ick                      +                H2        counter@0             ti,omap-counter32k                            interrupt-controller@48200000             ti,omap3-intc                                H                        target-module@48056000            ti,sysc-omap2 ti,sysc            H`    H`,   H`(           rev sysc syss             #                          
                                 S         ick                      +                H`       dma-controller@0              ti,omap3430-sdma ti,omap-sdma                                                $           /            <   `                     gpio@48310000             ti,omap3-gpio            H1                          gpio1            I         [        k                             gpio@49050000             ti,omap3-gpio            I                          gpio2            [        k                             gpio@49052000             ti,omap3-gpio            I                          gpio3            [        k                             gpio@49054000             ti,omap3-gpio            I@                          gpio4            [        k                             gpio@49056000             ti,omap3-gpio            I`                !         gpio5            [        k                                        gpio@49058000             ti,omap3-gpio            I                "         gpio6            [        k                                        serial@4806a000           ti,omap3-uart            H             w      H        ,      1      2        1tx rx            uart1           ;l       serial@4806c000           ti,omap3-uart            H            w      I        ,      3      4        1tx rx            uart2           ;l       serial@49020000           ti,omap3-uart            I             w      J        ,      5      6        1tx rx            uart3           ;l         gdefault         u         i2c@48070000              ti,omap3-i2c             H                 8        ,                    1tx rx                        +             i2c1            ; '@   twl@48              H                                  ti,twl4030                              gdefault         u         audio             ti,twl4030-audio       codec            rtc           ti,twl4030-rtc                    bci           ti,twl4030-bci              	                                    vac       watchdog              ti,twl4030-wdt        regulator-vaux1           ti,twl4030-vaux1          regulator-vaux2           ti,twl4030-vaux2          	  vdd_ehci             w@         w@               regulator-vaux3           ti,twl4030-vaux3          regulator-vaux4           ti,twl4030-vaux4          regulator-vdd1            ti,twl4030-vdd1          	'                            regulator-vdac            ti,twl4030-vdac          w@         w@      regulator-vio             ti,twl4030-vio        regulator-vintana1            ti,twl4030-vintana1       regulator-vintana2            ti,twl4030-vintana2       regulator-vintdig             ti,twl4030-vintdig        regulator-vmmc1           ti,twl4030-vmmc1             :         0                  regulator-vmmc2           ti,twl4030-vmmc2             :         0      regulator-vusb1v5             ti,twl4030-vusb1v5                    regulator-vusb1v8             ti,twl4030-vusb1v8                    regulator-vusb3v1             ti,twl4030-vusb3v1                    regulator-vpll1           ti,twl4030-vpll1          regulator-vpll2           ti,twl4030-vpll2             w@         w@      regulator-vsim            ti,twl4030-vsim          w@         -                  gpio              ti,twl4030-gpio          [        k                                                                      twl4030-usb           ti,twl4030-usb              
                                 
                      !               	      pwm           ti,twl4030-pwm          ,         pwmled            ti,twl4030-pwmled           ,         pwrbutton             ti,twl4030-pwrbutton                      keypad            ti,twl4030-keypad                       7           G         madc              ti,twl4030-madc                     Z                           i2c@48072000              ti,omap3-i2c             H                 9        ,                    1tx rx                        +             i2c2          	  %disabled          i2c@48060000              ti,omap3-i2c             H                 =        ,                    1tx rx                        +             i2c3            ;         gdefault         u         mailbox@48094000              ti,omap3-mailbox             mailbox          H	@                        l           x                 dsp                                                 spi@48098000              ti,omap2-mcspi           H	                A                     +             mcspi1                   @  ,      #      $      %      &      '      (      )      *         1tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3         gdefault         u      spidev@0              spidev          l                                spi@4809a000              ti,omap2-mcspi           H	                B                     +             mcspi2                      ,      +      ,      -      .        1tx0 rx0 tx1 rx1       spi@480b8000              ti,omap2-mcspi           H                [                     +             mcspi3                      ,                                1tx0 rx0 tx1 rx1         gdefault         u      spidev@0              spidev          l                                spi@480ba000              ti,omap2-mcspi           H                0                     +             mcspi4                     ,      F      G        1tx0 rx0       1w@480b2000           ti,omap3-1w          H                 :         hdq1w         mmc@4809c000              ti,omap3-hsmmc           H	                S         mmc1                     ,      =      >        1tx rx                      gdefault         u                                                            mmc@480b4000              ti,omap3-hsmmc           H@                V         mmc2            ,      /      0        1tx rx           gdefault         u                       !                    /      mmc@480ad000              ti,omap3-hsmmc           H
                ^         mmc3            ,      M      N        1tx rx         	  %disabled          mmu@480bd400            B              ti,omap2-iommu           H                         mmu_isp         O                    mmu@5d000000            B              ti,omap2-iommu           ]                           mmu_iva       	  %disabled          wdt@48314000              ti,omap3-wdt             H1@          
   wd_timer2         mcbsp@48074000            ti,omap3-mcbsp           H@            mpu                ;   <        _common tx rx            o            mcbsp1          ,                     1tx rx                        fck       	  %disabled          target-module@480a0000            ti,sysc-omap2 ti,sysc            H
 <   H
 @   H
 D           rev sysc syss                      
                                       ick                      +                H
         rng@0             ti,omap2-rng                                 4         mcbsp@49022000            ti,omap3-mcbsp           I     I            mpu sidetone                   >   ?           _common tx rx sidetone           o            mcbsp2 mcbsp2_sidetone          ,      !      "        1tx rx                           fck ick         %okay                     mcbsp@49024000            ti,omap3-mcbsp           I@    I            mpu sidetone                   Y   Z           _common tx rx sidetone           o            mcbsp3 mcbsp3_sidetone          ,                    1tx rx                           fck ick         %okay            gdefault         u        mcbsp@49026000            ti,omap3-mcbsp           I`            mpu                6   7        _common tx rx            o            mcbsp4          ,                    1tx rx                       fck         ~          	  %disabled          mcbsp@48096000            ti,omap3-mcbsp           H	`            mpu                Q   R        _common tx rx            o            mcbsp5          ,                    1tx rx                       fck       	  %disabled          sham@480c3000             ti,omap3-sham            sham             H0    d            1        ,      E        1rx        	  %disabled          target-module@48318000            ti,sysc-omap2-timer ti,sysc          H1    H1   H1           rev sysc syss             '        
                                            fck ick                      +                H1                         timer@0           ti,omap3430-timer                                       fck             %                              J         target-module@49032000            ti,sysc-omap2-timer ti,sysc          I     I    I            rev sysc syss             '        
                                            fck ick                      +                I        timer@0           ti,omap3430-timer                               &         timer@49034000            ti,omap3430-timer            I@                '         timer3        timer@49036000            ti,omap3430-timer            I`                (         timer4        timer@49038000            ti,omap3430-timer            I                )         timer5                 timer@4903a000            ti,omap3430-timer            I                *         timer6                 timer@4903c000            ti,omap3430-timer            I                +         timer7                 timer@4903e000            ti,omap3430-timer            I                ,         timer8                          timer@49040000            ti,omap3430-timer            I                 -         timer9                 timer@48086000            ti,omap3430-timer            H`                .         timer10                timer@48088000            ti,omap3430-timer            H                /         timer11                target-module@48304000            ti,sysc-omap2-timer ti,sysc          H0@    H0@   H0@           rev sysc syss             '        
                                            fck ick                      +                H0@       timer@0           ti,omap3430-timer                               _                           usbhstll@48062000             ti,usbhs-tll             H                 N         usb_tll_hs        usbhshost@48064000            ti,usbhs-host            H@             usb_host_hs                      +                   	  ehci-phy       ohci@48064400             ti,ohci-omap3            HD                L               ehci@48064800             ti,ehci-omap             HH                M        1               gpmc@6e000000             ti,omap3430-gpmc             gpmc             n                         ,              1rxtx            6           B                        +                                [        k                    0                    nand@0,0              ti,omap2-nand                                                                  T           c           usw                         $           $                                 $                      0        	                      &   H        7   H        H   6        W                        +      x-loader@0        	  iX-Loader                          bootloaders@80000           iU-Boot                       bootloaders_env@260000          iU-Boot Env            &           kernel@280000           iKernel            (   @        filesystem@680000           iFile System           h                usb_otg_hs@480ab000           ti,omap3-musb            H
                \   ]        _mc dma           usb_otg_hs          o           z                                    	        1  	      	  usb2-phy                          2      dss@48050000              ti,omap3-dss             H           	  %disabled          	   dss_core                         fck                      +                dispc@48050400            ti,omap3-dispc           H                      
   dss_dispc                        fck       encoder@4804fc00              ti,omap3-dsi             H    H    @H             proto phy pll                     	  %disabled          	   dss_dsi1                            fck sys_clk                      +          encoder@48050800              ti,omap3-rfbi            H          	  %disabled          	   dss_rfbi                            fck ick       encoder@48050c00              ti,omap3-venc            H          	  %disabled          	   dss_venc                         fck          ssi-controller@48058000           ti,omap3-ssi             ssi         %okay             H    H            sys gdd             G        _gdd_mpu                      +                         {  
            ssi_ssr_fck ssi_sst_fck ssi_ick    ssi-port@4805a000             ti,omap3-ssi-port            H    H            tx rx               C   D      ssi-port@4805b000             ti,omap3-ssi-port            H    H            tx rx               E   F         pinmux@480025d8            ti,omap3-padconf pinctrl-single          H %   $                     +                                            ,           J        isp@480bc000              ti,omap3-isp             H   H   |                                    l                          ports                        +             bandgap@48002524             H %$             ti,omap34xx-bandgap                              target-module@480cb000            ti,sysc-omap3430-sr ti,sysc          smartreflex_core             H$           sysc                                   fck                      +                H       smartreflex@0             ti,omap3-smartreflex-core                                        target-module@480c9000            ti,sysc-omap3430-sr ti,sysc          smartreflex_mpu_iva          H$           sysc                                   fck                      +                H       smartreflex@480c9000              ti,omap3-smartreflex-mpu-iva                                         target-module@50000000            ti,sysc-omap2 ti,sysc            P             rev                        fck ick                      +                P     @          opp-table             operating-points-v2-ti-cpu                            opp1-125000000              sY@                            opp2-250000000              沀         g8 g8 g8                          opp3-500000000              e          O O O                 opp4-550000000               U         tx tx tx                 opp5-600000000              #F          p p p                 opp6-720000000              *T          p p p                             thermal-zones      cpu_thermal                    .          <      N         I         trips      cpu_alert           Y 8        e           zpassive                  cpu_crit            Y _        e        	   zcritical             cooling-maps       map0            p          u                 memory@80000000          smemory                       hsusb2_power_reg              regulator-fixed         hsusb2_vbus          2Z         2Z                           p                 hsusb2_phy            usb-nop-xceiv                                     !                     sound             ti,omap-twl4030         omap3beagle                 regulator-mmc2-sdio-poweron           regulator-fixed         regulator-mmc2-sdio-poweron          0         0                          '                  gpio_poweroff           gdefault         u            gpio-poweroff                            	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 mmc0 mmc1 mmc2 serial0 serial1 serial2 device_type reg clocks clock-names clock-latency operating-points-v2 #cooling-cells cpu0-supply phandle interrupts ti,hwmods ranges #pinctrl-cells #interrupt-cells interrupt-controller pinctrl-single,register-width pinctrl-single,function-mask pinctrl-names pinctrl-0 pinctrl-single,pins syscon regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift reg-names ti,sysc-mask ti,sysc-sidle ti,syss-mask status dmas dma-names clock-frequency ti,max-div ti,index-starts-at-one clock-mult clock-div ti,set-bit-to-disable ti,clock-mult ti,clock-div ti,set-rate-parent ti,index-power-of-two ti,low-power-stop ti,lock ti,low-power-bypass ti,dividers ti,sysc-midle #dma-cells dma-channels dma-requests ti,gpio-always-on gpio-controller #gpio-cells interrupts-extended bci3v1-supply io-channels io-channel-names regulator-always-on ti,use-leds ti,pullups ti,pulldowns usb1v5-supply usb1v8-supply usb3v1-supply usb_mode #phy-cells #pwm-cells keypad,num-rows keypad,num-columns #io-channel-cells #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,spi-num-cs spi-max-frequency spi-cpha ti,dual-volt pbias-supply vmmc-supply vqmmc-supply cd-gpios bus-width non-removable cap-power-off-card #iommu-cells ti,#tlb-entries interrupt-names ti,buffer-size #sound-dai-cells ti,no-reset-on-init ti,no-idle ti,timer-alwon assigned-clocks assigned-clock-parents ti,timer-dsp ti,timer-pwm ti,timer-secure port2-mode remote-wakeup-connected phys gpmc,num-cs gpmc,num-waitpins nand-bus-width gpmc,device-width ti,nand-ecc-opt gpmc,cs-on-ns gpmc,cs-rd-off-ns gpmc,cs-wr-off-ns gpmc,adv-on-ns gpmc,adv-rd-off-ns gpmc,adv-wr-off-ns gpmc,oe-on-ns gpmc,oe-off-ns gpmc,we-on-ns gpmc,we-off-ns gpmc,rd-cycle-ns gpmc,wr-cycle-ns gpmc,access-ns gpmc,wr-access-ns label multipoint num-eps ram-bits interface-type usb-phy phy-names power iommus ti,phy-type #thermal-sensor-cells opp-hz opp-microvolt opp-supported-hw opp-suspend turbo-mode polling-delay-passive polling-delay coefficients thermal-sensors temperature hysteresis trip cooling-device gpio startup-delay-us reset-gpios vcc-supply ti,model ti,mcbsp 