Đţí  Iú   H  E4   (            Ć  Dě                                                                        Aries/DENX MCV EVK        /   !denx,mcvevk altr,socfpga-cyclone5 altr,socfpga     aliases          ,/soc/serial0@ffc02000            4/soc/serial1@ffc03000            </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000             X/soc/ethernet@ff700000           b/soc/i2c@ffc04000/stmpe811@41         cpus                                       maltr,socfpga-smp       cpu@0            !arm,cortex-a9            {cpu                                            cpu@1            !arm,cortex-a9            {cpu                                              pmu@ff111000             !arm,cortex-a9-pmu            ¤            ľ       °          ą            Ŕ               ˙    ˙0          intc@fffed000            !arm,cortex-a9-gic            Ó             ä         ˙ţĐ    ˙ţÁ                      soc                                   !simple-bus           {soc          ¤             ů   amba             !simple-bus                                     ů   pdma@ffe01000            !arm,pl330 arm,primecell          ˙ŕ          `   ľ       h          i          j          k          l          m          n          o                                              '         	  .apb_pclk            :      <        Adma             3         base_fpga_region             !fpga-region         M                                  can@ffc00000             !bosch,d_can          ˙Ŕ           0   ľ                                                '           :      7        Vokay          can@ffc01000             !bosch,d_can          ˙Ŕ          0   ľ                                                '   	        :      8        Vokay          clkmgr@ffd04000          !altr,clk-mgr             ˙Đ@       clocks                               osc1            ]             !fixed-clock         j}x@            
      osc2            ]             !fixed-clock                   f2s_periph_ref_clk          ]             !fixed-clock                   f2s_sdram_ref_clk           ]             !fixed-clock                   main_pll@40                                   ]             !altr,socfpga-pll-clock          '   
            @               mpuclk@48           ]             !altr,socfpga-perip-clk          '           z   ŕ       	            H                  mainclk@4c          ]             !altr,socfpga-perip-clk          '           z   ä       	            L                  dbg_base_clk@50         ]             !altr,socfpga-perip-clk          '      
        z   č       	            P                  main_qspi_clk@54            ]             !altr,socfpga-perip-clk          '               T                  main_nand_sdmmc_clk@58          ]             !altr,socfpga-perip-clk          '               X                  cfg_h2f_usr0_clk@5c         ]             !altr,socfpga-perip-clk          '               \                     periph_pll@80                                     ]             !altr,socfpga-pll-clock          '   
                                 emac0_clk@88            ]             !altr,socfpga-perip-clk          '                                 emac1_clk@8c            ]             !altr,socfpga-perip-clk          '                                 per_qsi_clk@90          ]             !altr,socfpga-perip-clk          '                                  per_nand_mmc_clk@94         ]             !altr,socfpga-perip-clk          '                                 per_base_clk@98         ]             !altr,socfpga-perip-clk          '                                 h2f_usr1_clk@9c         ]             !altr,socfpga-perip-clk          '                                    sdram_pll@c0                                      ]             !altr,socfpga-pll-clock          '   
                  Ŕ               ddr_dqs_clk@c8          ]             !altr,socfpga-perip-clk          '               Č            !      ddr_2x_dqs_clk@cc           ]             !altr,socfpga-perip-clk          '               Ě            "      ddr_dq_clk@d0           ]             !altr,socfpga-perip-clk          '               Đ            #      h2f_usr2_clk@d4         ]             !altr,socfpga-perip-clk          '               Ô            $         mpu_periph_clk          ]             !altr,socfpga-perip-clk          '                          2      mpu_l2_ram_clk          ]             !altr,socfpga-perip-clk          '                    l4_main_clk         ]             !altr,socfpga-gate-clk           '              `                      l3_main_clk         ]             !altr,socfpga-perip-clk          '                    l3_mp_clk           ]             !altr,socfpga-gate-clk           '           z   d                  `                     l3_sp_clk           ]             !altr,socfpga-gate-clk           '           z   d            l4_mp_clk           ]             !altr,socfpga-gate-clk           '              z   d                 `               (      l4_sp_clk           ]             !altr,socfpga-gate-clk           '              z   d                 `               )      dbg_at_clk          ]             !altr,socfpga-gate-clk           '           z   h                  `                     dbg_clk         ]             !altr,socfpga-gate-clk           '           z   h                 `         dbg_trace_clk           ]             !altr,socfpga-gate-clk           '           z   l                  `         dbg_timer_clk           ]             !altr,socfpga-gate-clk           '              `         cfg_clk         ]             !altr,socfpga-gate-clk           '              `         h2f_user0_clk           ]             !altr,socfpga-gate-clk           '              `   	      emac_0_clk          ]             !altr,socfpga-gate-clk           '                               &      emac_1_clk          ]             !altr,socfpga-gate-clk           '                              '      usb_mp_clk          ]             !altr,socfpga-gate-clk           '                          z   ¤                   4      spi_m_clk           ]             !altr,socfpga-gate-clk           '                          z   ¤                  1      can0_clk            ]             !altr,socfpga-gate-clk           '                          z   ¤                        can1_clk            ]             !altr,socfpga-gate-clk           '                          z   ¤   	               	      gpio_db_clk         ]             !altr,socfpga-gate-clk           '                          z   ¨             h2f_user1_clk           ]             !altr,socfpga-gate-clk           '                        sdmmc_clk           ]             !altr,socfpga-gate-clk           '                                                         sdmmc_clk_divided           ]             !altr,socfpga-gate-clk           '                                         ,      nand_x_clk          ]             !altr,socfpga-gate-clk           '                        	                  nand_ecc_clk            ]             !altr,socfpga-gate-clk           '                  	            .      nand_clk            ]             !altr,socfpga-gate-clk           '                  
                       -      qspi_clk            ]             !altr,socfpga-gate-clk           '                                     /      ddr_dqs_clk_gate            ]             !altr,socfpga-gate-clk           '   !           Ř          ddr_2x_dqs_clk_gate         ]             !altr,socfpga-gate-clk           '   "           Ř         ddr_dq_clk_gate         ]             !altr,socfpga-gate-clk           '   #           Ř         h2f_user2_clk           ]             !altr,socfpga-gate-clk           '   $           Ř               fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           ˙@             :      a        '         	  Vdisabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             ˙P             :      `        '         	  Vdisabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             ˙`             :      b        '         	  Vdisabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           ˙ÂP         	  Vdisabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            ˙p`    ˙š              ľ       Ż                     ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         Ł   %   `             ˙p               ľ       s           śmacirq          Ć                '   &      
  .stmmaceth           :             
  Astmmaceth           Ň           í           	                      Vokay            %rgmii         ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         Ł   %   `            ˙p               ľ       x           śmacirq          Ć                '   '      
  .stmmaceth           :      !      
  Astmmaceth           Ň           í           	                    	  Vdisabled          gpio@ff708000                                      !snps,dw-apb-gpio             ˙p            '   (        :      9        Vokay       gpio-controller@0            !snps,dw-apb-gpio-port            .        >           J                          ä         Ó            ľ       ¤            gpio@ff709000                                      !snps,dw-apb-gpio             ˙p            '   (        :      :        Vokay       gpio-controller@0            !snps,dw-apb-gpio-port            .        >           J                          ä         Ó            ľ       Ľ               *         gpio@ff70a000                                      !snps,dw-apb-gpio             ˙p             '   (        :      ;        Vokay       gpio-controller@0            !snps,dw-apb-gpio-port            .        >           J                          ä         Ó            ľ       Ś            i2c@ffc04000                                       !snps,designware-i2c          ˙Ŕ@            :      ,        '   )         ľ                  Vokay            j     stmpe811@41          !st,stmpe811                                       A        X            [           b   *         stmpe_touchscreen            !st,stmpe-ts         k           z                                             ¨           ť           Ç           Ő               i2c@ffc05000                                       !snps,designware-i2c          ˙ŔP            :      -        '   )         ľ                	  Vdisabled          i2c@ffc06000                                       !snps,designware-i2c          ˙Ŕ`            :      .        '   )         ľ                 	  Vdisabled          i2c@ffc07000                                       !snps,designware-i2c          ˙Ŕp            :      /        '   )         ľ       Ą         	  Vdisabled          eccmgr           !altr,socfpga-ecc-manager                                       ů   l2-ecc@ffd08140          !altr,socfpga-l2-ecc          ˙Đ@            ľ       $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           ˙ĐD           ŕ   +         ľ       ˛          ł            cache-controller@fffef000            !arm,pl310-cache          ˙ţđ             ľ       &            ĺ        ó           ˙                                              .            =        Q           e            ~                       Š                     l3regs@0xff800000            !altr,l3regs syscon           ˙           dwmmc0@ff704000          !altr,socfpga-dw-mshc             ˙p@             ľ                                                       '   (   ,        .biu ciu         :      6        Vokay             ˝        Ç            Ń         ă      nand@ff900000                                      !altr,socfpga-denali-nand             ˙     ˙¸             ônand_data denali_reg             ľ                  '   -      .        .nand nand_x ecc         :      $      	  Vdisabled          sram@ffff0000         
   !mmio-sram            ˙˙                 +      spi@ff705000             !cdns,qspi-nor                                      ˙pP    ˙               ľ                  ţ                                  '   /        :      %      	  Vdisabled          rstmgr@ffd05000         3            !altr,rst-mgr             ˙ĐP            @                     snoop-control-unit@fffec000          !arm,cortex-a9-scu            ˙ţŔ          sdr@ffc25000             !altr,sdr-ctl syscon          ˙ÂP            :      =            0      sdramedac            !altr,sdram-edac         S   0         ľ       '         spi@fff00000             !snps,dw-apb-ssi                                    ˙đ              ľ                  c           '   1        :      2        Aspi       	  Vdisabled          spi@fff01000             !snps,dw-apb-ssi                                    ˙đ             ľ                  c           '   1        :      3        Aspi       	  Vdisabled          sysmgr@ffd08000          !altr,sys-mgr syscon          ˙Đ   @         j˙ĐÄ            %      timer@fffec600           !arm,cortex-a9-twd-timer          ˙ţĆ             ľ                '   2      timer0@ffc08000          !snps,dw-apb-timer            ľ       §            ˙Ŕ            '   )        .timer           :      *        Atimer         timer1@ffc09000          !snps,dw-apb-timer            ľ       ¨            ˙Ŕ            '   )        .timer           :      +        Atimer         timer2@ffd00000          !snps,dw-apb-timer            ľ       Š            ˙Đ             '   
        .timer           :      (        Atimer         timer3@ffd01000          !snps,dw-apb-timer            ľ       Ş            ˙Đ            '   
        .timer           :      )        Atimer         serial0@ffc02000             !snps,dw-apb-uart             ˙Ŕ              ľ       ˘           z                      '   )           3      3           tx rx           :      0        Vokay          serial1@ffc03000             !snps,dw-apb-uart             ˙Ŕ0             ľ       Ł           z                      '   )           3      3           tx rx           :      1      usbphy                        !usb-nop-xceiv           Vokay                5      usb@ffb00000          
   !snps,dwc2            ˙°    ˙˙         ľ       }           '   4        .otg         :      "        Adwc2            Ť   5      	  °usb2-phy          	  Vdisabled          usb@ffb40000          
   !snps,dwc2            ˙´    ˙˙         ľ                  '   4        .otg         :      #        Adwc2            Ť   5      	  °usb2-phy            Vokay          watchdog@ffd02000            !snps,dw-wdt          ˙Đ              ľ       Ť           '   
        :      &        Vokay          watchdog@ffd03000            !snps,dw-wdt          ˙Đ0             ľ       Ź           '   
        :      '      	  Vdisabled             memory@0             {memory               @         chosen          şserial0:115200n8             	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 ethernet0 stmpe-i2c0 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells #dma-channels #dma-requests clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate clk-phase altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth phy-mode gpio-controller #gpio-cells snps,nr-gpios id blocks irq-gpio ts,sample-time ts,mod-12b ts,ref-sel ts,adc-freq ts,ave-ctrl ts,touch-det-delay ts,settling ts,fraction-z ts,i-drive iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names stdout-path 