Đţí  T   H  N@   (            G  Mř                                                                        samtec VIN|ING FPGA       1   !samtec,vining altr,socfpga-cyclone5 altr,socfpga       aliases          ,/soc/serial0@ffc02000            4/soc/serial1@ffc03000            </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000             X/soc/ethernet@ff702000           b/soc/ethernet@ff700000        cpus                                       laltr,socfpga-smp       cpu@0            !arm,cortex-a9            zcpu                                            cpu@1            !arm,cortex-a9            zcpu                                              pmu@ff111000             !arm,cortex-a9-pmu            Ł            ´       °          ą            ż               ˙    ˙0          intc@fffed000            !arm,cortex-a9-gic            Ň             ă         ˙ţĐ    ˙ţÁ                      soc                                   !simple-bus           zsoc          Ł             ř   amba             !simple-bus                                     ř   pdma@ffe01000            !arm,pl330 arm,primecell          ˙ŕ          `   ´       h          i          j          k          l          m          n          o            ˙           
                       &         	  -apb_pclk            9      <        @dma             4         base_fpga_region             !fpga-region         L                                  can@ffc00000             !bosch,d_can          ˙Ŕ           0   ´                                                &           9      7      	  Udisabled          can@ffc01000             !bosch,d_can          ˙Ŕ          0   ´                                                &   	        9      8      	  Udisabled          clkmgr@ffd04000          !altr,clk-mgr             ˙Đ@       clocks                               osc1            \             !fixed-clock         i}x@            
      osc2            \             !fixed-clock                   f2s_periph_ref_clk          \             !fixed-clock                   f2s_sdram_ref_clk           \             !fixed-clock                   main_pll@40                                   \             !altr,socfpga-pll-clock          &   
            @               mpuclk@48           \             !altr,socfpga-perip-clk          &           y   ŕ       	            H                  mainclk@4c          \             !altr,socfpga-perip-clk          &           y   ä       	            L                  dbg_base_clk@50         \             !altr,socfpga-perip-clk          &      
        y   č       	            P                  main_qspi_clk@54            \             !altr,socfpga-perip-clk          &               T                  main_nand_sdmmc_clk@58          \             !altr,socfpga-perip-clk          &               X                  cfg_h2f_usr0_clk@5c         \             !altr,socfpga-perip-clk          &               \                     periph_pll@80                                     \             !altr,socfpga-pll-clock          &   
                                 emac0_clk@88            \             !altr,socfpga-perip-clk          &                                 emac1_clk@8c            \             !altr,socfpga-perip-clk          &                                 per_qsi_clk@90          \             !altr,socfpga-perip-clk          &                                  per_nand_mmc_clk@94         \             !altr,socfpga-perip-clk          &                                 per_base_clk@98         \             !altr,socfpga-perip-clk          &                                 h2f_usr1_clk@9c         \             !altr,socfpga-perip-clk          &                                    sdram_pll@c0                                      \             !altr,socfpga-pll-clock          &   
                  Ŕ               ddr_dqs_clk@c8          \             !altr,socfpga-perip-clk          &               Č            !      ddr_2x_dqs_clk@cc           \             !altr,socfpga-perip-clk          &               Ě            "      ddr_dq_clk@d0           \             !altr,socfpga-perip-clk          &               Đ            #      h2f_usr2_clk@d4         \             !altr,socfpga-perip-clk          &               Ô            $         mpu_periph_clk          \             !altr,socfpga-perip-clk          &                          3      mpu_l2_ram_clk          \             !altr,socfpga-perip-clk          &                    l4_main_clk         \             !altr,socfpga-gate-clk           &              `                      l3_main_clk         \             !altr,socfpga-perip-clk          &                    l3_mp_clk           \             !altr,socfpga-gate-clk           &           y   d                  `                     l3_sp_clk           \             !altr,socfpga-gate-clk           &           y   d            l4_mp_clk           \             !altr,socfpga-gate-clk           &              y   d                 `               *      l4_sp_clk           \             !altr,socfpga-gate-clk           &              y   d                 `               +      dbg_at_clk          \             !altr,socfpga-gate-clk           &           y   h                  `                     dbg_clk         \             !altr,socfpga-gate-clk           &           y   h                 `         dbg_trace_clk           \             !altr,socfpga-gate-clk           &           y   l                  `         dbg_timer_clk           \             !altr,socfpga-gate-clk           &              `         cfg_clk         \             !altr,socfpga-gate-clk           &              `         h2f_user0_clk           \             !altr,socfpga-gate-clk           &              `   	      emac_0_clk          \             !altr,socfpga-gate-clk           &                               &      emac_1_clk          \             !altr,socfpga-gate-clk           &                              '      usb_mp_clk          \             !altr,socfpga-gate-clk           &                          y   ¤                   5      spi_m_clk           \             !altr,socfpga-gate-clk           &                          y   ¤                  2      can0_clk            \             !altr,socfpga-gate-clk           &                          y   ¤                        can1_clk            \             !altr,socfpga-gate-clk           &                          y   ¤   	               	      gpio_db_clk         \             !altr,socfpga-gate-clk           &                          y   ¨             h2f_user1_clk           \             !altr,socfpga-gate-clk           &                        sdmmc_clk           \             !altr,socfpga-gate-clk           &                                                         sdmmc_clk_divided           \             !altr,socfpga-gate-clk           &                                         -      nand_x_clk          \             !altr,socfpga-gate-clk           &                        	                  nand_ecc_clk            \             !altr,socfpga-gate-clk           &                  	            /      nand_clk            \             !altr,socfpga-gate-clk           &                  
                       .      qspi_clk            \             !altr,socfpga-gate-clk           &                                     0      ddr_dqs_clk_gate            \             !altr,socfpga-gate-clk           &   !           Ř          ddr_2x_dqs_clk_gate         \             !altr,socfpga-gate-clk           &   "           Ř         ddr_dq_clk_gate         \             !altr,socfpga-gate-clk           &   #           Ř         h2f_user2_clk           \             !altr,socfpga-gate-clk           &   $           Ř               fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           ˙@             9      a        &         	  Udisabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             ˙P             9      `        &         	  Udisabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             ˙`             9      b        &         	  Udisabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           ˙ÂP         	  Udisabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            ˙p`    ˙š              ´       Ż                     ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         ˘   %   `             ˙p               ´       s           ľmacirq          Ĺ                &   &      
  -stmmaceth           9             
  @stmmaceth           Ń           ě                               	  Udisabled          ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         ˘   %   `            ˙p               ´       x           ľmacirq          Ĺ                &   '      
  -stmmaceth           9      !      
  @stmmaceth           Ń           ě                                 Uokay            $rgmii           -   (        8   )                H        ^  '  '  '   mdio0                                      !snps,dwmac-mdio    ethernet-phy@1                      s                                                §            ´            Á            Î            Ű            č  D        ô              D            (            gpio@ff708000                                      !snps,dw-apb-gpio             ˙p            &   *        9      9        Uokay       gpio-controller@0            !snps,dw-apb-gpio-port                               )                          ă         Ň            ´       ¤               )         gpio@ff709000                                      !snps,dw-apb-gpio             ˙p            &   *        9      :        Uokay       gpio-controller@0            !snps,dw-apb-gpio-port                               )                          ă         Ň            ´       Ľ               8         gpio@ff70a000                                      !snps,dw-apb-gpio             ˙p             &   *        9      ;        Uokay       gpio-controller@0            !snps,dw-apb-gpio-port                               )                          ă         Ň            ´       Ś               7         i2c@ffc04000                                       !snps,designware-i2c          ˙Ŕ@            9      ,        &   +         ´                  Uokay       pca9557@1f           !nxp,pca9557                                       lm75@48          !lm75                H      at24@50          !atmel,24c01         7               P      i2cswitch@70             !nxp,pca9548                                       p   i2c@0                                                i2c@1                                               i2c@2                                               i2c@3                                               i2c@4                                               i2c@5                                               i2c@6                                            eeprom@51            !atmel,24c01         7               Q         i2c@7                                            eeprom@51            !atmel,24c01         7               Q               i2c@ffc05000                                       !snps,designware-i2c          ˙ŔP            9      -        &   +         ´                  Uokay            i     at24@50          !atmel,24c02         7               P         i2c@ffc06000                                       !snps,designware-i2c          ˙Ŕ`            9      .        &   +         ´                 	  Udisabled          i2c@ffc07000                                       !snps,designware-i2c          ˙Ŕp            9      /        &   +         ´       Ą         	  Udisabled          eccmgr           !altr,socfpga-ecc-manager                                       ř   l2-ecc@ffd08140          !altr,socfpga-l2-ecc          ˙Đ@            ´       $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           ˙ĐD           @   ,         ´       ˛          ł            cache-controller@fffef000            !arm,pl310-cache          ˙ţđ             ´       &            E        S           _                 o                                                ą           Ĺ            Ţ           ÷            	                     l3regs@0xff800000            !altr,l3regs syscon           ˙           dwmmc0@ff704000          !altr,socfpga-dw-mshc             ˙p@             ´                                                       &   *   -        -biu ciu         9      6      	  Udisabled                     '            1         C      nand@ff900000                                      !altr,socfpga-denali-nand             ˙     ˙¸             Tnand_data denali_reg             ´                  &   .      /        -nand nand_x ecc         9      $      	  Udisabled          sram@ffff0000         
   !mmio-sram            ˙˙                 ,      spi@ff705000             !cdns,qspi-nor                                      ˙pP    ˙               ´                  ^           n           ~            &   0        9      %        Uokay       n25q128@0                                     !micron,n25q128 jedec,spi-nor                         őá          Ľ        ´           Ă           Ó           ă   2        ń   2        ˙                    n25q00@1                                      !micron,mt25qu02g jedec,spi-nor                      őá          Ľ        ´           Ă           Ó           ă   2        ń   2        ˙                       rstmgr@ffd05000                     !altr,rst-mgr             ˙ĐP            (                     snoop-control-unit@fffec000          !arm,cortex-a9-scu            ˙ţŔ          sdr@ffc25000             !altr,sdr-ctl syscon          ˙ÂP            9      =            1      sdramedac            !altr,sdram-edac         ;   1         ´       '         spi@fff00000             !snps,dw-apb-ssi                                    ˙đ              ´                  K           &   2        9      2        @spi       	  Udisabled          spi@fff01000             !snps,dw-apb-ssi                                    ˙đ             ´                  K           &   2        9      3        @spi       	  Udisabled          sysmgr@ffd08000          !altr,sys-mgr syscon          ˙Đ   @         R˙ĐÄ            %      timer@fffec600           !arm,cortex-a9-twd-timer          ˙ţĆ             ´                &   3      timer0@ffc08000          !snps,dw-apb-timer            ´       §            ˙Ŕ            &   +        -timer           9      *        @timer         timer1@ffc09000          !snps,dw-apb-timer            ´       ¨            ˙Ŕ            &   +        -timer           9      +        @timer         timer2@ffd00000          !snps,dw-apb-timer            ´       Š            ˙Đ             &   
        -timer           9      (        @timer         timer3@ffd01000          !snps,dw-apb-timer            ´       Ş            ˙Đ            &   
        -timer           9      )        @timer         serial0@ffc02000             !snps,dw-apb-uart             ˙Ŕ              ´       ˘           b           l           &   +        y   4      4           ~tx rx           9      0      serial1@ffc03000             !snps,dw-apb-uart             ˙Ŕ0             ´       Ł           b           l           &   +        y   4      4           ~tx rx           9      1      usbphy                       !usb-nop-xceiv           Uokay                6      usb@ffb00000          
   !snps,dwc2            ˙°    ˙˙         ´       }           &   5        -otg         9      "        @dwc2               6      	  usb2-phy            Uokay            ˘host          usb@ffb40000          
   !snps,dwc2            ˙´    ˙˙         ´                  &   5        -otg         9      #        @dwc2               6      	  usb2-phy            Uokay            ˘peripheral        watchdog@ffd02000            !snps,dw-wdt          ˙Đ              ´       Ť           &   
        9      &        Uokay          watchdog@ffd03000            !snps,dw-wdt          ˙Đ0             ´       Ź           &   
        9      '      	  Udisabled             chosen          Şearlyprintk         łserial0:115200n8          memory@0             zmemory               @         gpio-keys         
   !gpio-keys      hps_temp0           żBTN_0           1   7              Ĺ         hps_hkey0         
  żGP_SWITCH           1   7              Ĺ        hps_hkey1           żRESET_SWITCH            1   7              Ĺ        hps_hkey2           żPOWER_DOWN          1   7              Ĺ   t      hps_hkey3           żSENSE           1   )   	           Ĺ           regulator-usb-nrst           !regulator-fixed       	  Đusb_nrst            ß LK@        ÷ LK@        C   8                p                   3         	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 ethernet0 ethernet1 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells #dma-channels #dma-requests clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate clk-phase altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth phy-mode phy-handle snps,reset-gpio snps,reset-active-low snps,reset-delays-us rxd0-skew-ps rxd1-skew-ps rxd2-skew-ps rxd3-skew-ps txd0-skew-ps txd1-skew-ps txd2-skew-ps txd3-skew-ps txen-skew-ps txc-skew-ps rxdv-skew-ps rxc-skew-ps gpio-controller #gpio-cells snps,nr-gpios pagesize iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address spi-max-frequency m25p,fast-read cdns,page-size cdns,block-size cdns,read-delay cdns,tshsl-ns cdns,tsd2d-ns cdns,tchsh-ns cdns,tslch-ns #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names dr_mode bootargs stdout-path label linux,code regulator-name regulator-min-microvolt regulator-max-microvolt startup-delay-us enable-active-high regulator-always-on 