Ðþí  Gâ   8  C¼   (            &  C„                                                         Altera SOCFPGA VT            !altr,socfpga-vt altr,socfpga       aliases          ,/soc/serial0@ffc02000            4/soc/serial1@ffc03000            </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000          cpus                                       Xaltr,socfpga-smp       cpu@0            !arm,cortex-a9            fcpu          r             v            ‡         cpu@1            !arm,cortex-a9            fcpu          r            v            ‡            pmu@ff111000             !arm,cortex-a9-pmu                                °          ±            «               rÿ    ÿ0          intc@fffed000            !arm,cortex-a9-gic            ¾             Ï         rÿþÐ    ÿþÁ             ‡         soc                                   !simple-bus           fsoc                       ä   amba             !simple-bus                                     ä   pdma@ffe01000            !arm,pl330 arm,primecell          rÿà          `           h          i          j          k          l          m          n          o            ë            ö                                	  apb_pclk            %      <        ,dma          ‡   2         base_fpga_region             !fpga-region         8                                  can@ffc00000             !bosch,d_can          rÿÀ           0           ƒ          „          …          †                      %      7      	  Adisabled          can@ffc01000             !bosch,d_can          rÿÀ          0           ‡          ˆ          ‰          Š              	        %      8      	  Adisabled          clkmgr@ffd04000          !altr,clk-mgr             rÿÐ@       clocks                               osc1            H             !fixed-clock         U ˜–€         ‡   
      osc2            H             !fixed-clock          ‡         f2s_periph_ref_clk          H             !fixed-clock          ‡         f2s_sdram_ref_clk           H             !fixed-clock          ‡         main_pll@40                                   H             !altr,socfpga-pll-clock             
         r   @         ‡      mpuclk@48           H             !altr,socfpga-perip-clk                     e   à       	         r   H         ‡         mainclk@4c          H             !altr,socfpga-perip-clk                     e   ä       	         r   L         ‡         dbg_base_clk@50         H             !altr,socfpga-perip-clk                
        e   è       	         r   P         ‡         main_qspi_clk@54            H             !altr,socfpga-perip-clk                      r   T         ‡         main_nand_sdmmc_clk@58          H             !altr,socfpga-perip-clk                      r   X         ‡         cfg_h2f_usr0_clk@5c         H             !altr,socfpga-perip-clk                      r   \         ‡            periph_pll@80                                     H             !altr,socfpga-pll-clock             
               r   €         ‡      emac0_clk@88            H             !altr,socfpga-perip-clk                      r   ˆ         ‡         emac1_clk@8c            H             !altr,socfpga-perip-clk                      r   Œ         ‡         per_qsi_clk@90          H             !altr,socfpga-perip-clk                      r            ‡          per_nand_mmc_clk@94         H             !altr,socfpga-perip-clk                      r   ”         ‡         per_base_clk@98         H             !altr,socfpga-perip-clk                      r   ˜         ‡         h2f_usr1_clk@9c         H             !altr,socfpga-perip-clk                      r   œ         ‡            sdram_pll@c0                                      H             !altr,socfpga-pll-clock             
               r   À         ‡      ddr_dqs_clk@c8          H             !altr,socfpga-perip-clk                      r   È         ‡   !      ddr_2x_dqs_clk@cc           H             !altr,socfpga-perip-clk                      r   Ì         ‡   "      ddr_dq_clk@d0           H             !altr,socfpga-perip-clk                      r   Ð         ‡   #      h2f_usr2_clk@d4         H             !altr,socfpga-perip-clk                      r   Ô         ‡   $         mpu_periph_clk          H             !altr,socfpga-perip-clk                     m            ‡   1      mpu_l2_ram_clk          H             !altr,socfpga-perip-clk                     m         l4_main_clk         H             !altr,socfpga-gate-clk                      {   `             ‡         l3_main_clk         H             !altr,socfpga-perip-clk                     m         l3_mp_clk           H             !altr,socfpga-gate-clk                      e   d               {   `            ‡         l3_sp_clk           H             !altr,socfpga-gate-clk                      e   d            l4_mp_clk           H             !altr,socfpga-gate-clk                         e   d              {   `            ‡   (      l4_sp_clk           H             !altr,socfpga-gate-clk                         e   d              {   `            ‡   )      dbg_at_clk          H             !altr,socfpga-gate-clk                      e   h               {   `            ‡         dbg_clk         H             !altr,socfpga-gate-clk                      e   h              {   `         dbg_trace_clk           H             !altr,socfpga-gate-clk                      e   l               {   `         dbg_timer_clk           H             !altr,socfpga-gate-clk                      {   `         cfg_clk         H             !altr,socfpga-gate-clk                      {   `         h2f_user0_clk           H             !altr,socfpga-gate-clk                      {   `   	      emac_0_clk          H             !altr,socfpga-gate-clk                      {                 ‡   &      emac_1_clk          H             !altr,socfpga-gate-clk                      {                ‡   '      usb_mp_clk          H             !altr,socfpga-gate-clk                      {               e   ¤                ‡   3      spi_m_clk           H             !altr,socfpga-gate-clk                      {               e   ¤               ‡   0      can0_clk            H             !altr,socfpga-gate-clk                      {               e   ¤               ‡         can1_clk            H             !altr,socfpga-gate-clk                      {               e   ¤   	            ‡   	      gpio_db_clk         H             !altr,socfpga-gate-clk                      {               e   ¨             h2f_user1_clk           H             !altr,socfpga-gate-clk                      {             sdmmc_clk           H             !altr,socfpga-gate-clk                            {               „       ‡         ‡         sdmmc_clk_divided           H             !altr,socfpga-gate-clk                      {               m            ‡   +      nand_x_clk          H             !altr,socfpga-gate-clk                            {       	         ‡         nand_ecc_clk            H             !altr,socfpga-gate-clk                      {       	         ‡   -      nand_clk            H             !altr,socfpga-gate-clk                      {       
        m            ‡   ,      qspi_clk            H             !altr,socfpga-gate-clk                             {                ‡   .      ddr_dqs_clk_gate            H             !altr,socfpga-gate-clk              !        {   Ø          ddr_2x_dqs_clk_gate         H             !altr,socfpga-gate-clk              "        {   Ø         ddr_dq_clk_gate         H             !altr,socfpga-gate-clk              #        {   Ø         h2f_user2_clk           H             !altr,socfpga-gate-clk              $        {   Ø               fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           rÿ@             %      a                 	  Adisabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             rÿP             %      `                 	  Adisabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             rÿ`             %      b                 	  Adisabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           rÿÂP€         	  Adisabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            rÿp`    ÿ¹                      ¯            ‡         ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         Ž   %   `             rÿp                       s           ¡macirq          ±                   &      
  stmmaceth           %             
  ,stmmaceth           ½           Ø   €        ô                      Aokay            gmii          ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         Ž   %   `            rÿp                       x           ¡macirq          ±                   '      
  stmmaceth           %      !      
  ,stmmaceth           ½           Ø   €        ô                    	  Adisabled          gpio@ff708000                                      !snps,dw-apb-gpio             rÿp€               (        %      9      	  Adisabled       gpio-controller@0            !snps,dw-apb-gpio-port                    )           5            r              Ï         ¾                    ¤            gpio@ff709000                                      !snps,dw-apb-gpio             rÿp               (        %      :      	  Adisabled       gpio-controller@0            !snps,dw-apb-gpio-port                    )           5            r              Ï         ¾                    ¥            gpio@ff70a000                                      !snps,dw-apb-gpio             rÿp                (        %      ;      	  Adisabled       gpio-controller@0            !snps,dw-apb-gpio-port                    )           5            r              Ï         ¾                    ¦            i2c@ffc04000                                       !snps,designware-i2c          rÿÀ@            %      ,           )                 ž         	  Adisabled          i2c@ffc05000                                       !snps,designware-i2c          rÿÀP            %      -           )                 Ÿ         	  Adisabled          i2c@ffc06000                                       !snps,designware-i2c          rÿÀ`            %      .           )                           	  Adisabled          i2c@ffc07000                                       !snps,designware-i2c          rÿÀp            %      /           )                 ¡         	  Adisabled          eccmgr           !altr,socfpga-ecc-manager                                       ä   l2-ecc@ffd08140          !altr,socfpga-l2-ecc          rÿÐ@                    $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           rÿÐD           C   *                 ²          ³            cache-controller@fffef000            !arm,pl310-cache          rÿþð                     &            H        V           b                 r                 ƒ           ‘                     ´           È            á           ú                        ‡         l3regs@0xff800000            !altr,l3regs syscon           rÿ€           dwmmc0@ff704000          !altr,socfpga-dw-mshc             rÿp@                     ‹           ÷                                        (   +        biu ciu         %      6      	  Adisabled                      *            4         F      nand@ff900000                                      !altr,socfpga-denali-nand             rÿ     ÿ¸             Wnand_data denali_reg                                   ,      -        nand nand_x ecc         %      $      	  Adisabled          sram@ffff0000         
   !mmio-sram            rÿÿ              ‡   *      spi@ff705000             !cdns,qspi-nor                                      rÿpP    ÿ                       —           a   €        q                          .        %      %      	  Adisabled          rstmgr@ffd05000         –            !altr,rst-mgr             rÿÐP            £            ‡         snoop-control-unit@fffec000          !arm,cortex-a9-scu            rÿþÀ          sdr@ffc25000             !altr,sdr-ctl syscon          rÿÂP            %      =         ‡   /      sdramedac            !altr,sdram-edac         ¶   /                 '         spi@fff00000             !snps,dw-apb-ssi                                    rÿð                      š           Æ              0        %      2        ,spi       	  Adisabled          spi@fff01000             !snps,dw-apb-ssi                                    rÿð                     ›           Æ              0        %      3        ,spi       	  Adisabled          sysmgr@ffd08000          !altr,sys-mgr syscon          rÿÐ€   @         ÍÿÐ€         ‡   %      timer@fffec600           !arm,cortex-a9-twd-timer          rÿþÆ                                 1      timer0@ffc08000          !snps,dw-apb-timer                    §            rÿÀ€               )        timer           %      *        ,timer           U jÏÀ      timer1@ffc09000          !snps,dw-apb-timer                    ¨            rÿÀ               )        timer           %      +        ,timer           U jÏÀ      timer2@ffd00000          !snps,dw-apb-timer                    ©            rÿÐ                
        timer           %      (        ,timer           U jÏÀ      timer3@ffd01000          !snps,dw-apb-timer                    ª            rÿÐ               
        timer           %      )        ,timer           U jÏÀ      serial0@ffc02000             !snps,dw-apb-uart             rÿÀ                      ¢           Ý           ç              )        ô   2      2           ùtx rx           %      0        U p€       serial1@ffc03000             !snps,dw-apb-uart             rÿÀ0                     £           Ý           ç              )        ô   2      2           ùtx rx           %      1        U p€       usbphy                       !usb-nop-xceiv           Aokay             ‡   4      usb@ffb00000          
   !snps,dwc2            rÿ°    ÿÿ                 }              3        otg         %      "        ,dwc2               4      	  usb2-phy          	  Adisabled          usb@ffb40000          
   !snps,dwc2            rÿ´    ÿÿ                 €              3        otg         %      #        ,dwc2               4      	  usb2-phy          	  Adisabled          watchdog@ffd02000            !snps,dw-wdt          rÿÐ                      «              
        %      &      	  Adisabled          watchdog@ffd03000            !snps,dw-wdt          rÿÐ0                     ¬              
        %      '      	  Adisabled             chosen          console=ttyS0,57600       memory@0             fmemory           r    @            	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells #dma-channels #dma-requests clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate clk-phase altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth phy-mode gpio-controller #gpio-cells snps,nr-gpios iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names bootargs 