  L   8  I(   (              H                             $    mediatek,mt6795-evb mediatek,mt6795                                  +         !   7MediaTek MT6795 Evaluation Board          	   =embedded       aliases          J/soc/ovl@1400c000            O/soc/ovl@1400d000            T/soc/rdma@1400e000           Z/soc/rdma@1400f000           `/soc/rdma@14010000           f/soc/wdma@14011000           l/soc/wdma@14012000           r/soc/color@14013000          y/soc/color@14014000          /soc/split@14018000          /soc/split@14019000          /soc/dpi@1401d000            /soc/dsi@1401b000            /soc/dsi@1401c000            /soc/serial@11002000             /soc/serial@11003000             /soc/serial@11004000             /soc/serial@11005000          psci              arm,psci-0.2             smc       cpus                         +       cpu@0            cpu           arm,cortex-a53           psci                                                          cpu@1            cpu           arm,cortex-a53           psci                                                  @        +           8           E   @        W                                cpu@2            cpu           arm,cortex-a53           psci                                                  @        +           8           E   @        W                                cpu@3            cpu           arm,cortex-a53           psci                                                  @        +           8           E   @        W                          	      cpu@100          cpu           arm,cortex-a53           psci                                                  @        +           8           E   @        W                          
      cpu@101          cpu           arm,cortex-a53           psci                                                 @        +           8           E   @        W                                cpu@102          cpu           arm,cortex-a53           psci                                                 @        +           8           E   @        W                                cpu@103          cpu           arm,cortex-a53           psci                                                 @        +           8           E   @        W                                cpu-map    cluster0       core0           d         core1           d         core2           d         core3           d   	         cluster1       core0           d   
      core1           d         core2           d         core3           d               l2-cache0             cache           h                         @        -            t                 l2-cache1             cache           h                         @        -            t                    oscillator-26m            fixed-clock                             clk26m                   oscillator-32k            fixed-clock                       }         clk32k                   dummy13m              fixed-clock          ]@                             pmu           arm,cortex-a53-pmu        0                   	          
                                 	      timer             arm,armv8-timer                   0                                
        soc                      +             simple-bus              syscon@10000000            mediatek,mt6795-topckgen syscon                                                    syscon@10001000            mediatek,mt6795-infracfg syscon                                                              syscon@10003000           mediatek,mt6795-pericfg syscon                0                                               syscon@10006000           syscon simple-mfd                 `                      power-controller          !    mediatek,mt6795-power-controller                         +                             power-domain@1                            R        mm                    power-domain@2                            R      U        mm venc                   power-domain@3                            R        mm                    power-domain@0                             R        mm                               power-domain@4                            R      e        mm mjc                    power-domain@5                                power-domain@6                                 mfg                      +                  power-domain@7                                   +                  power-domain@8                                                       pinctrl@10005000              mediatek,mt6795-pinctrl                P                           
  base eint                                        '        7           C                       O        d                    watchdog@10007000             mediatek,mt6795-wdt               p                                             u         timer@10008000        ,    mediatek,mt6795-timer mediatek,mt6577-timer                                                             pwrap@1000d000            mediatek,mt6795-pwrap                                 pwrap                                           pwrap                 c         	  spi wrap          intpol-controller@10200620        .    mediatek,mt6795-sysirq mediatek,mt6577-sysirq            O        d                                                       timer@10200670            mediatek,mt6795-systimer                  p                      @                      clk13m        iommu@10205000            mediatek,mt6795-m4u               P                              bclk                                                                                     syscon@10209000       "    mediatek,mt6795-apmixedsys syscon                                               !      clock-controller@10209f00             mediatek,mt6795-fhctl                               	  disabled          mailbox@10212000          (    mediatek,mt6795-gce mediatek,mt8173-gce              !                                                 gce                             dsi-phy@10215000              mediatek,mt8173-mipi-tx              !P                           mipi_tx0_pll                                  	  disabled                     dsi-phy@10216000              mediatek,mt8173-mipi-tx              !`                           mipi_tx1_pll                                  	  disabled                      interrupt-controller@10221000             arm,gic-400         d                        O      @       "            "              "@             "`                       	                   cci@10390000              arm,cci-400                      +                9                         9        slave-if@1000             arm,cci-400-ctrl-if       	  ace-lite                         slave-if@4000             arm,cci-400-ctrl-if         ace            @                     slave-if@5000             arm,cci-400-ctrl-if         ace            P                     pmu@9000              arm,cci-400-pmu,r1                P       <         :          ;          <          =          >            serial@11002000       *    mediatek,mt6795-uart mediatek,mt6577-uart                                         [                             	  baud bus                                 tx rx           okay          serial@11003000       *    mediatek,mt6795-uart mediatek,mt6577-uart                 0                       \                             	  baud bus                                tx rx         	  disabled          dma-controller@11000380       2    mediatek,mt6795-uart-dma mediatek,mt6577-uart-dma                        `             `            `             `            `             `            `             `      `         g          h          i          j          k          l          m          n                                    apdma                                        serial@11004000       *    mediatek,mt6795-uart mediatek,mt6577-uart                 @                       ]                              	  baud bus                                tx rx         	  disabled          serial@11005000       *    mediatek,mt6795-uart mediatek,mt6577-uart                 P                       ^                 !            	  baud bus                                tx rx         	  disabled          pwm@11006000              mediatek,mt6795-pwm               `                &                  M         H        S      	                                                ,  top main pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7       	  disabled          i2c@11007000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                p        p                            T           1                             	  main dma                         +          	  disabled          i2c@11008000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                        p                           U           1                             	  main dma                         +          	  disabled          i2c@11009000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                        p                            V           1                             	  main dma                         +          	  disabled          i2c@11010000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                        p                           W           1                             	  main dma                         +          	  disabled          i2c@11011000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c                       p                            X           1                             	  main dma                         +          	  disabled          mmc@11230000              mediatek,mt6795-mmc              #                        O                       \      ]        source hclk source_cg         	  disabled          mmc@11240000              mediatek,mt6795-mmc              $                        P                       O        source hclk       	  disabled          mmc@11250000              mediatek,mt6795-mmc              %                        Q                       O        source hclk       	  disabled          mmc@11260000              mediatek,mt6795-mmc              &                        R                       O        source hclk       	  disabled          syscon@14000000           mediatek,mt6795-mmsys syscon                                                  ;      R        Kׄ                               `                           g                              ovl@1400c000          2    mediatek,mt6795-disp-ovl mediatek,mt8173-disp-ovl                                                                                               g                  ovl@1400d000          2    mediatek,mt6795-disp-ovl mediatek,mt8173-disp-ovl                                                                                              g                  rdma@1400e000         4    mediatek,mt6795-disp-rdma mediatek,mt8173-disp-rdma                                                                                            g                  rdma@1400f000         4    mediatek,mt6795-disp-rdma mediatek,mt8173-disp-rdma                                                                                            g                  rdma@14010000         4    mediatek,mt6795-disp-rdma mediatek,mt8173-disp-rdma                                                                                            g                   wdma@14011000         4    mediatek,mt6795-disp-wdma mediatek,mt8173-disp-wdma                                                                                           g                  wdma@14012000         4    mediatek,mt6795-disp-wdma mediatek,mt8173-disp-wdma                                                                                            g                   color@14013000        6    mediatek,mt6795-disp-color mediatek,mt8173-disp-color                0                                                               g        0          color@14014000        6    mediatek,mt6795-disp-color mediatek,mt8173-disp-color                @                                                               g        @          aal@14015000          2    mediatek,mt6795-disp-aal mediatek,mt8173-disp-aal                P                                                               g        P          gamma@14016000        6    mediatek,mt6795-disp-gamma mediatek,mt8173-disp-gamma                `                                                               g        `          merge@14017000        6    mediatek,mt6795-disp-merge mediatek,mt8173-disp-merge                p                                           split@14018000        6    mediatek,mt6795-disp-split mediatek,mt8173-disp-split                                                           split@14019000        6    mediatek,mt6795-disp-split mediatek,mt8173-disp-split                                                           ufoe@1401a000         4    mediatek,mt6795-disp-ufoe mediatek,mt8173-disp-ufoe                                                                             g                  dsi@1401b000          (    mediatek,mt6795-dsi mediatek,mt8173-dsi                                                                     $      %           engine digital hs                      dphy          	  disabled          dsi@1401c000          (    mediatek,mt6795-dsi mediatek,mt8173-dsi                                                                     &      '            engine digital hs                       dphy          	  disabled          dpi@1401d000          (    mediatek,mt6795-dpi mediatek,mt8183-dpi                                                                     (      )   !           pixel engine pll          	  disabled          pwm@1401e000          2    mediatek,mt6795-disp-pwm mediatek,mt8173-disp-pwm                                &                 !               main mm       	  disabled          pwm@1401f000          2    mediatek,mt6795-disp-pwm mediatek,mt8173-disp-pwm                                &                 #      "        main mm       	  disabled          mutex@14020000            mediatek,mt8173-disp-mutex                                                                                  4   5        g                   larb@14021000             mediatek,mt6795-smi-larb                                                      apb smi            "                                            smi@14022000              mediatek,mt6795-smi-common                                                                    apb smi            "      od@14023000       0    mediatek,mt6795-disp-od mediatek,mt8173-disp-od              0                              g        0          larb@15001000             mediatek,mt6795-smi-larb                                                       apb smi            "                                          clock-controller@16000000             mediatek,mt6795-vdecsys                                              #      larb@16010000             mediatek,mt6795-smi-larb                                     "                      #       #           apb smi                                clock-controller@18000000             mediatek,mt6795-vencsys                                              $      larb@18001000             mediatek,mt6795-smi-larb                                     $      $            apb smi            "                                             memory@40000000          memory               @               chosen          serial0:921600n8             	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl1 rdma0 rdma1 rdma2 wdma0 wdma1 color0 color1 split0 split1 dpi0 dsi0 dsi1 serial0 serial1 serial2 serial3 method device_type enable-method reg cci-control-port next-level-cache phandle i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets cpu cache-level cache-unified #clock-cells clock-frequency clock-output-names interrupts interrupt-affinity ranges #reset-cells #power-domain-cells clocks clock-names mediatek,infracfg reg-names gpio-controller #gpio-cells gpio-ranges interrupt-controller #interrupt-cells timeout-sec resets reset-names mediatek,larbs power-domains #iommu-cells status #mbox-cells #phy-cells interface-type dmas dma-names dma-requests mediatek,dma-33bits #dma-cells #pwm-cells clock-div assigned-clocks assigned-clock-rates mboxes mediatek,gce-client-reg iommus phys phy-names mediatek,gce-events mediatek,smi mediatek,larb-id stdout-path 